From 09aac7b1c30503522c67b0758408c7a849019aa8 Mon Sep 17 00:00:00 2001
From: Damien Wiame <wiamedams@Dams-MacBook-Pro.local>
Date: Wed, 9 Nov 2022 18:53:33 +0100
Subject: [PATCH] suite PIN
---
encoder.c | 26 ++++++++++++++++++--------
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/encoder.c b/encoder.c
index 211d311..fa3d97d 100644
--- a/encoder.c
+++ b/encoder.c
@@ -3,16 +3,26 @@
#include <wiringPi.h>
-const int MOSI_PIN = 12;
-const int MISO_PIN = 13;
-const int MOSI_PIN_FPGA = 14;
-const int MISO_PIN_FPGA = 16;
-const int ENC_PIN_1A = 38;
-const int ENC_PIN_1B = 36;
-const int ENC_PIN_2A = 35;
-const int ENC_PIN_2B = 34;
+const int MOSI_PIN = 12; //from RASPI to FPGA
+const int MISO_PIN = 13; //from RASPI to FPGA
+const int MOSI_PIN_FPGA = 14; //from RASPI to FPGA
+const int MISO_PIN_FPGA = 16; //from RASPI to FPGA
+const int VDD_PIN_FPGA = 29; //from FPGA to ENCODER -> ouput data from encoder
+const int ENC_PIN_1A = 38; //from FPGA to ENCODER -> ouput data from encoder
+const int ENC_PIN_1B = 36; //from FPGA to ENCODER -> ouput data from encoder
+const int ENC_PIN_2A = 35; //from FPGA to ENCODER -> ouput data from encoder
+const int ENC_PIN_2B = 34; //from FPGA to ENCODER -> ouput data from encoder
+const int SCK_PIN = 14; //from RASPI to FPGA -> clock signal
+const int SCK_PIN_FPGA = 13; //from FPGA to ENCODER -> clock signal
+const int SS_BAR_1 = 2; //from RASPI to FPGA -> enable encoder
+const int SS_BAR_2 = 3; //from RASPI to FPGA -> enable encoder
int main(int argc, char const *argv[])
{
+ pinMode(ENC_PIN_1A, INPUT);
+ pinMode(ENC_PIN_1B, INPUT);
+ pinMode(ENC_PIN_2A, INPUT);
+ pinMode(ENC_PIN_2B, INPUT);
+
return 0;
}
\ No newline at end of file
--
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