diff --git a/.vscode/settings.json b/.vscode/settings.json
index 5b671cb10dfe045c789cb0aa16d8f546e87fb1c1..6f571c2f02e783e89e60db5f37cde16c398431b9 100644
--- a/.vscode/settings.json
+++ b/.vscode/settings.json
@@ -1,6 +1,7 @@
{
"files.associations": {
"iostream": "cpp",
- "limits": "cpp"
+ "limits": "cpp",
+ "main.h": "c"
}
}
\ No newline at end of file
diff --git a/SPI/MyDE0_Nano.sv b/SPI/MyDE0_Nano.sv
deleted file mode 100644
index 64a073987bab61271dced6a8dd195ec1b6d25c67..0000000000000000000000000000000000000000
--- a/SPI/MyDE0_Nano.sv
+++ /dev/null
@@ -1,58 +0,0 @@
-module MyDE0_Nano(
-
-//////////// CLOCK //////////
-input logic CLOCK_50,
-
-//////////// LED //////////
-output logic [7:0] LED,
-
-//////////// KEY //////////
-input logic [1:0] KEY,
-
-//////////// 2x13 GPIO Header //////////
-inout logic [12:0] GPIO_2,
-input logic [2:0] GPIO_2_IN,
-
-//////////// GPIO_0, GPIO_0 connect to GPIO Default //////////
-inout logic [33:0] GPIO_0_PI,
-input logic [1:0] GPIO_0_PI_IN,
-
-//////////// GPIO_1, GPIO_1 connect to GPIO Default //////////
-inout logic [33:0] GPIO_1,
-input logic [1:0] GPIO_1_IN
-);
-
-//=======================================================
-// SPI
-//=======================================================
-
- logic spi_clk, spi_cs, spi_mosi, spi_miso;
- logic [31:0] DataToPI, DataFromPI;
-
- spi_slave spi_slave_instance(
- .sck(spi_clk),
- .mosi(spi_mosi),
- .miso(spi_miso),
- .reset(),
- .d(DataToPI),
- .q(DataFromPI)
- );
-
- assign spi_clk = GPIO_0_PI[8]; // SCLK = pin 13
- assign spi_cs = GPIO_0_PI[10]; // CE0 = pin 15
- assign spi_mosi = GPIO_0_PI[9]; // MOSI = pin 14
-
- assign GPIO_0_PI[11] = spi_cs ? 1'bz : spi_miso; // MISO = pin 16
-
- logic ENC_1A, ENC_1B, ENC_2A, ENC_2B;
-
- assign ENC_1A = GPIO_0_PI[31]; //pin 38
- assign ENC_1B = GPIO_0_PI[29]; //pin 36
- assign ENC_2A = GPIO_0_PI[28]; //pin 35
- assign ENC_2B = GPIO_0_PI[27]; //pin 34
-
- always_ff(negedge spi_clk)
- assign DataToPI = ENC_1A;
-
-endmodule
-
diff --git a/SPI/MyTestbench.sv b/SPI/MyTestbench.sv
deleted file mode 100644
index 293fd3e1a5b5aceb05d925dc39787b49bcff5a95..0000000000000000000000000000000000000000
--- a/SPI/MyTestbench.sv
+++ /dev/null
@@ -1,53 +0,0 @@
-module MyTestbench();
-
- logic clk;
- logic reset;
-
- logic [15:0] PC;
- logic [15:0] WriteData;
- logic [12:0] DataAdr;
- logic MemWrite;
-
- wire [33:0] GPIO_0_PI;
- wire [33:0] GPIO_1;
- wire [12:0] GPIO_2;
-
- // instantiate device to be tested
- MyDE0_Nano dut(
- .CLOCK_50(clk),
- .GPIO_0_PI(GPIO_0_PI),
- .GPIO_1(GPIO_1),
- .GPIO_2(GPIO_2)
- );
-
- assign GPIO_0_PI[1] = reset;
-
- // initialize test
- initial
- begin
- reset <= 1; # 22; reset <= 0;
- end
-
- // generate clock to sequence tests
- always
- begin
- clk <= 1; # 5; clk <= 0; # 5;
- end
-
- // check results
- always @(negedge clk)
- begin
- if(MemWrite) begin
- if(DataAdr === 128 & WriteData === 254) begin
- $display("Simulation succeeded");
- $stop;
- end else if (DataAdr === 128) begin
- $display("Simulation failed");
- $stop;
- end
- end
- end
-
- // Simulate SPI
-
-endmodule
\ No newline at end of file
diff --git a/SPI/SPI_test.qpf b/SPI/SPI_test.qpf
deleted file mode 100644
index 4449b85577e2412dc22869a65d2a417edae7629a..0000000000000000000000000000000000000000
--- a/SPI/SPI_test.qpf
+++ /dev/null
@@ -1,30 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2018 Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions
-# and other software and tools, and its AMPP partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Intel Program License
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel FPGA IP License Agreement, or other applicable license
-# agreement, including, without limitation, that your use is for
-# the sole purpose of programming logic devices manufactured by
-# Intel and sold by Intel or its authorized distributors. Please
-# refer to the applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
-# Date created = 11:33:52 November 14, 2022
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "18.1"
-DATE = "11:33:52 November 14, 2022"
-
-# Revisions
-
-PROJECT_REVISION = "SPI_test"
diff --git a/SPI/SPI_test.qsf b/SPI/SPI_test.qsf
deleted file mode 100644
index bcbfcb134ad427bb7b26da5c01010d2e0c7dbd7e..0000000000000000000000000000000000000000
--- a/SPI/SPI_test.qsf
+++ /dev/null
@@ -1,80 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2018 Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions
-# and other software and tools, and its AMPP partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Intel Program License
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel FPGA IP License Agreement, or other applicable license
-# agreement, including, without limitation, that your use is for
-# the sole purpose of programming logic devices manufactured by
-# Intel and sold by Intel or its authorized distributors. Please
-# refer to the applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
-# Date created = 11:33:52 November 14, 2022
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-# SPI_test_assignment_defaults.qdf
-# If this file doesn't exist, see file:
-# assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus Prime software
-# and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-set_global_assignment -name FAMILY "Cyclone IV E"
-set_global_assignment -name DEVICE EP4CE22F17C6
-set_global_assignment -name TOP_LEVEL_ENTITY MyDE0_Nano
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:33:52 NOVEMBER 14, 2022"
-set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
-set_global_assignment -name SYSTEMVERILOG_FILE MyTestbench.sv
-set_global_assignment -name SYSTEMVERILOG_FILE MySPI.sv
-set_global_assignment -name SYSTEMVERILOG_FILE MyDE0_Nano.sv
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
-set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
-set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_location_assignment PIN_R7 -to CLOCK_50
-set_location_assignment PIN_E1 -to KEY[1]
-set_location_assignment PIN_J15 -to KEY[0]
-set_location_assignment PIN_A15 -to LED[0]
-set_location_assignment PIN_D5 -to GPIO_0_PI[9]
-set_location_assignment PIN_A13 -to LED[1]
-set_location_assignment PIN_L3 -to LED[7]
-set_location_assignment PIN_A11 -to LED[3]
-set_location_assignment PIN_B1 -to LED[6]
-set_location_assignment PIN_B13 -to LED[2]
-set_location_assignment PIN_D1 -to LED[4]
-set_location_assignment PIN_F3 -to LED[5]
-set_location_assignment PIN_A5 -to GPIO_0_PI[5]
-set_location_assignment PIN_B6 -to GPIO_0_PI[17]
-set_location_assignment PIN_C11 -to GPIO_0_PI[28]
-set_location_assignment PIN_B11 -to GPIO_0_PI[29]
-set_location_assignment PIN_D11 -to GPIO_0_PI[31]
-set_location_assignment PIN_E10 -to GPIO_0_PI[27]
-set_location_assignment PIN_A6 -to GPIO_0_PI[11]
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/SPI/SPI_test.qws b/SPI/SPI_test.qws
deleted file mode 100644
index 23c0f1e9499e5cc962f47beb1a9c73dad5634711..0000000000000000000000000000000000000000
Binary files a/SPI/SPI_test.qws and /dev/null differ
diff --git a/SPI/SPI_test_description.txt b/SPI/SPI_test_description.txt
deleted file mode 100644
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..0000000000000000000000000000000000000000
diff --git a/SPI/cr_ie_info.json b/SPI/cr_ie_info.json
deleted file mode 100644
index 7b66cddba53bce653e3edfdda9ef08611128bbb9..0000000000000000000000000000000000000000
--- a/SPI/cr_ie_info.json
+++ /dev/null
@@ -1,22 +0,0 @@
-{
- "system" : {
- "platform" : "windows64",
- "os_name" : "Windows 10",
- "os_version" : "10.0"
- },
- "error" : {
- "executable" : "quartus_map",
- "comment" : "none",
- "error_message" : "cdb_is_connected(tri_data) && !tri_data->is_vcc_or_gnd()",
- "source_file" : "/quartus/synth/mls/mls_process_tri.cpp",
- "line" : "6076",
- "stack_trace" : "\t0x7ff8b4c22039: SYNTH_MLS + 0x82039 (?error_multiple_drivers@OPT_TRI_PROCESSOR@@AEAAXPEAVCDB_SGATE_OTERM@@PEAVCDB_SGATE_NODE@@1@Z + 0x38d)\n\t0x7ff8b4bc615a: SYNTH_MLS + 0x2615a (?process_tribus@OPT_TRI_PROCESSOR@@AEAA?AW4PROCESS_STATUS@@PEAVCDB_SGATE_TRI_BUS@@@Z + 0x352)\n\t0x7ff8b4bc7233: SYNTH_MLS + 0x27233 (?do_processing_loop@OPT_TRI_PROCESSOR@@AEAA?AW4PROCESS_STATUS@@XZ + 0x2b3)\n\t0x7ff8b4bc3143: SYNTH_MLS + 0x23143 (OPT_TRI_PROCESSOR::perform_function + 0x147)\n\t0x7ff8b4bc2c55: SYNTH_MLS + 0x22c55 (OPT_TRI_PROCESSOR::synthesize_tristates + 0x285)\n\t0x7ff8b4be37de: SYNTH_MLS + 0x437de (?opt_process_tri@@YA?AW4PROCESS_STATUS@@PEAVCDB_SGATE_NETLIST@@VMLS_CONFIGURATION@@PEAVCMP_FACADE@@@Z + 0x6e)\n\t0x7ff8b4bb0397: SYNTH_MLS + 0x10397 (?call_named_function@MLS_NETLIST@@QEAAXAEBV?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@00@Z + 0x1a37)\n\t0x7ff8b4bbd799: SYNTH_MLS + 0x1d799 (MLS_NETLIST::call_fn + 0x109)\n\t0x7ff8b4badd0b: SYNTH_MLS + 0xdd0b (MLS_NETLIST::run_script + 0x3d7)\n\t0x7ff8b4ba280b: SYNTH_MLS + 0x280b (MLS_ROOT::start_from_mls_netlist + 0x43)\n\t0x7ff8b3efa7f5: SYNTH_SCL + 0x5a7f5 (?synthesize_with_script@SCL_SYN_HIER@@AEAA_NPEAPEAVMLS_NETLIST@@PEAVCDB_SGATE_NETLIST@@AEBW4SCRIPT_TYPE@MLS_SCRIPT_MANAGER@@PEAPEAVCDB_ATOM_NETLIST@@@Z + 0x195)\n\t0x7ff8b3efb8f7: SYNTH_SCL + 0x5b8f7 (?work_normal_flow@SCL_SYN_HIER@@AEAA_NXZ + 0x637)\n\t0x7ff8b3ec3b25: SYNTH_SCL + 0x23b25 (?process_one_hierarchy@SCL_SYN_STATE@@AEAA_NPEAVCDB_SGATE_HIERARCHY@@PEAPEAVCDB_ATOM_NETLIST@@@Z + 0x95)\n\t0x7ff8b3ec68c6: SYNTH_SCL + 0x268c6 (?synthesize_design@SCL_SYN_STATE@@QEAA_NXZ + 0x446)\n\t0x7ff8b3ec553c: SYNTH_SCL + 0x2553c (?scl_execute_syn@@YA_NPEAVCMP_FACADE@@@Z + 0x9c)\n\t0x7ff8b3ea5794: SYNTH_SCL + 0x5794 (?scl_execute_normal_flow@@YA_NPEAVCMP_FACADE@@_N@Z + 0x134)\n\t0x7ff6f49e56a5: quartus_map + 0x56a5 (?qsyn_execute_scl@@YA_NPEAVQSYN_FRAMEWORK@@PEAVIDU_PARTITION@@_N@Z + 0x255)\n\t0x7ff6f4a0063d: quartus_map + 0x2063d (?scl_iteration@QSYN_FRAMEWORK@@AEAA_NXZ + 0xa8d)\n\t0x7ff6f49f4070: quartus_map + 0x14070 (?execute_core@QSYN_FRAMEWORK@@AEAA_NPEAVTHR_NAMED_PIPE@@0@Z + 0x200)\n\t0x7ff6f49f3aa6: quartus_map + 0x13aa6 (?execute@QSYN_FRAMEWORK@@UEAA_NXZ + 0x496)\n\t0x7ff93c6212bc: comp_qexe + 0x112bc (qexe_do_normal + 0x1ec)\n\t0x7ff93c626142: comp_qexe + 0x16142 (qexe_run + 0x432)\n\t0x7ff93c626e51: comp_qexe + 0x16e51 (?qexe_standard_main@@YAHPEAVQEXE_FRAMEWORK@@PEAPEBUQEXE_OPTION_DEFINITION@@HPEAPEBD@Z + 0xc1)\n\t0x7ff6f49fb08b: quartus_map + 0x1b08b (?qsyn_main@@YAHHPEAPEBD@Z + 0x51b)\n\t0x7ff954b32e98: CCL_MSG + 0x12e98 (?msg_main_thread@@YAPEAXPEAX@Z + 0x18)\n\t0x7ff954b3467e: CCL_MSG + 0x1467e (?msg_thread_wrapper@@YAPEAXP6APEAXPEAX@Z0@Z + 0x6e)\n\t0x7ff954c46660: ccl_mem + 0x16660 (?mem_thread_wrapper@@YAPEAXP6APEAXPEAX@Z0@Z + 0x70)\n\t0x7ff954b32761: CCL_MSG + 0x12761 (?msg_exe_main@@YAHHPEAPEBDP6AHH0@Z@Z + 0xa1)\n\t0x7ff6f4a09872: quartus_map + 0x29872 (__tmainCRTStartup + 0x10e)\n\t0x7ff96ae674b3: KERNEL32 + 0x174b3 (BaseThreadInitThunk + 0x13)\n\t0x7ff96b7226a0: ntdll + 0x526a0 (RtlUserThreadStart + 0x20)\n",
- "subsystem" : "MLS"
- },
- "quartus" : {
- "quartus_bits" : "64",
- "version" : "18.1.0",
- "build" : "625",
- "edition" : "Lite Edition"
- }
-}
\ No newline at end of file
diff --git a/SPI/db/.cmp.kpt b/SPI/db/.cmp.kpt
deleted file mode 100644
index 4455db73bd8b0c041cb9326c1a269345d8dc2f3a..0000000000000000000000000000000000000000
Binary files a/SPI/db/.cmp.kpt and /dev/null differ
diff --git a/SPI/db/SPI_test.(0).cnf.cdb b/SPI/db/SPI_test.(0).cnf.cdb
deleted file mode 100644
index d6e8080216e478b1df2563218919997acd45c05c..0000000000000000000000000000000000000000
Binary files a/SPI/db/SPI_test.(0).cnf.cdb and /dev/null differ
diff --git a/SPI/db/SPI_test.(0).cnf.hdb b/SPI/db/SPI_test.(0).cnf.hdb
deleted file mode 100644
index 2f2a7fabcd1e831df7b48fa90dfdcb72c740591b..0000000000000000000000000000000000000000
Binary files a/SPI/db/SPI_test.(0).cnf.hdb and /dev/null differ
diff --git a/SPI/db/SPI_test.(1).cnf.cdb b/SPI/db/SPI_test.(1).cnf.cdb
deleted file mode 100644
index 85d2aa310a7eb2a3d90fcc9ab61e34520f983286..0000000000000000000000000000000000000000
Binary files a/SPI/db/SPI_test.(1).cnf.cdb and /dev/null differ
diff --git a/SPI/db/SPI_test.(1).cnf.hdb b/SPI/db/SPI_test.(1).cnf.hdb
deleted file mode 100644
index c634230d27b5e70ee9aa4d39f8208078e5682b28..0000000000000000000000000000000000000000
Binary files a/SPI/db/SPI_test.(1).cnf.hdb and /dev/null differ
diff --git a/SPI/db/SPI_test.asm.qmsg b/SPI/db/SPI_test.asm.qmsg
deleted file mode 100644
index 03072b883c581c43ff640a621269032113a48fe3..0000000000000000000000000000000000000000
--- a/SPI/db/SPI_test.asm.qmsg
+++ /dev/null
@@ -1,7 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1668613902148 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1668613902155 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 16 16:51:42 2022 " "Processing started: Wed Nov 16 16:51:42 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1668613902155 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1668613902155 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off SPI_test -c SPI_test " "Command: quartus_asm --read_settings_files=off --write_settings_files=off SPI_test -c SPI_test" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1668613902156 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1668613902439 ""}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1668613902988 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1668613903012 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4674 " "Peak virtual memory: 4674 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1668613903151 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 16 16:51:43 2022 " "Processing ended: Wed Nov 16 16:51:43 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1668613903151 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1668613903151 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1668613903151 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1668613903151 ""}
diff --git a/SPI/db/SPI_test.asm.rdb b/SPI/db/SPI_test.asm.rdb
deleted file mode 100644
index f76c0db57929b9eb462d08867a8a1401ff5693ec..0000000000000000000000000000000000000000
Binary files a/SPI/db/SPI_test.asm.rdb and /dev/null differ
diff --git a/SPI/db/SPI_test.asm_labs.ddb b/SPI/db/SPI_test.asm_labs.ddb
deleted file mode 100644
index d1622c9f9a6f6353d96b8c1b6110ffd1b5f189b1..0000000000000000000000000000000000000000
Binary files a/SPI/db/SPI_test.asm_labs.ddb and /dev/null differ
diff --git a/SPI/db/SPI_test.cbx.xml b/SPI/db/SPI_test.cbx.xml
deleted file mode 100644
index 8ee924701db99e1cb52991b61905fc6e9c5e133f..0000000000000000000000000000000000000000
--- a/SPI/db/SPI_test.cbx.xml
+++ /dev/null
@@ -1,5 +0,0 @@
-<?xml version="1.0" ?>
-<LOG_ROOT>
- <PROJECT NAME="SPI_test">
- </PROJECT>
-</LOG_ROOT>
diff --git a/SPI/db/SPI_test.cmp.bpm b/SPI/db/SPI_test.cmp.bpm
deleted file mode 100644
index d447d3c1b62cc872c6d2589830b33b961baf77b6..0000000000000000000000000000000000000000
Binary files a/SPI/db/SPI_test.cmp.bpm and /dev/null differ
diff --git a/SPI/db/SPI_test.cmp.cdb b/SPI/db/SPI_test.cmp.cdb
deleted file mode 100644
index b3e4dcebb183d478e6f742a85f4c4bcb08f43345..0000000000000000000000000000000000000000
Binary files a/SPI/db/SPI_test.cmp.cdb and /dev/null differ
diff --git a/SPI/db/SPI_test.cmp.hdb b/SPI/db/SPI_test.cmp.hdb
deleted file mode 100644
index 2a35a95cf8493ae032f68e49bda7179a53820d48..0000000000000000000000000000000000000000
Binary files a/SPI/db/SPI_test.cmp.hdb and /dev/null differ
diff --git a/SPI/db/SPI_test.cmp.idb b/SPI/db/SPI_test.cmp.idb
deleted file mode 100644
index 483dfa7520c0a80a1b34d128c3a1993ca1c3fcca..0000000000000000000000000000000000000000
Binary files a/SPI/db/SPI_test.cmp.idb and /dev/null differ
diff --git a/SPI/db/SPI_test.cmp.logdb b/SPI/db/SPI_test.cmp.logdb
deleted file mode 100644
index 395bd5a3ef7821e3ca5c40ad0f095b12b7b2fe46..0000000000000000000000000000000000000000
--- a/SPI/db/SPI_test.cmp.logdb
+++ /dev/null
@@ -1,141 +0,0 @@
-v1
-IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
-IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,PASS,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
-IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
-IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
-IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042,
-IO_RULES_MATRIX,Total Pass,19;0;19;0;0;99;19;0;99;99;0;89;0;0;91;0;89;91;0;0;80;89;0;0;0;0;0;99;0;0,
-IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,Total Inapplicable,80;99;80;99;99;0;80;99;0;0;99;10;99;99;8;99;10;8;99;99;19;10;99;99;99;99;99;0;99;99,
-IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,CLOCK_50,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LED[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LED[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LED[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LED[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LED[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LED[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LED[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LED[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,KEY[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,KEY[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_2_IN[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_2_IN[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_2_IN[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_0_PI_IN[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_0_PI_IN[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_1_IN[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_1_IN[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_2[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_2[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_2[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_2[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_2[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_2[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_2[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_2[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_2[8],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_2[9],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_2[10],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_2[11],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_2[12],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_0_PI[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_0_PI[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_0_PI[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_0_PI[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_0_PI[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_0_PI[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_0_PI[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_0_PI[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_0_PI[12],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_0_PI[13],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_0_PI[14],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_0_PI[15],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_0_PI[16],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_0_PI[17],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_0_PI[18],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_0_PI[19],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_0_PI[20],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_0_PI[21],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_0_PI[22],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_0_PI[23],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_0_PI[24],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_0_PI[25],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_0_PI[26],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_0_PI[27],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_0_PI[28],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_0_PI[29],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_0_PI[30],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_0_PI[32],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_0_PI[33],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_1[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_1[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_1[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_1[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_1[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_1[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_1[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_1[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_1[8],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_1[9],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_1[10],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_1[11],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_1[12],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_1[13],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_1[14],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_1[15],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_1[16],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_1[17],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_1[18],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_1[19],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_1[20],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_1[21],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_1[22],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_1[23],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_1[24],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_1[25],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_1[26],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_1[27],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_1[28],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_1[29],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_1[30],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_1[31],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_1[32],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_1[33],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_0_PI[8],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_0_PI[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_0_PI[10],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_0_PI[11],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,GPIO_0_PI[31],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_SUMMARY,Total I/O Rules,30,
-IO_RULES_SUMMARY,Number of I/O Rules Passed,13,
-IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
-IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
-IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,17,
diff --git a/SPI/db/SPI_test.cmp.rdb b/SPI/db/SPI_test.cmp.rdb
deleted file mode 100644
index 6c7d89d129f0d69356a37607b20b550056d23f25..0000000000000000000000000000000000000000
Binary files a/SPI/db/SPI_test.cmp.rdb and /dev/null differ
diff --git a/SPI/db/SPI_test.cmp_merge.kpt b/SPI/db/SPI_test.cmp_merge.kpt
deleted file mode 100644
index f231fff3a467dddb1cff80f033c334e4043f6046..0000000000000000000000000000000000000000
Binary files a/SPI/db/SPI_test.cmp_merge.kpt and /dev/null differ
diff --git a/SPI/db/SPI_test.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd b/SPI/db/SPI_test.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
deleted file mode 100644
index c79e2f780bb890bb2ebb1e244d20664b2f531291..0000000000000000000000000000000000000000
Binary files a/SPI/db/SPI_test.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd and /dev/null differ
diff --git a/SPI/db/SPI_test.cycloneive_io_sim_cache.45um_tt_1200mv_0c_slow.hsd b/SPI/db/SPI_test.cycloneive_io_sim_cache.45um_tt_1200mv_0c_slow.hsd
deleted file mode 100644
index 63bf1a8894c79c29ec0b4fd174f933e92783f93f..0000000000000000000000000000000000000000
Binary files a/SPI/db/SPI_test.cycloneive_io_sim_cache.45um_tt_1200mv_0c_slow.hsd and /dev/null differ
diff --git a/SPI/db/SPI_test.cycloneive_io_sim_cache.45um_tt_1200mv_85c_slow.hsd b/SPI/db/SPI_test.cycloneive_io_sim_cache.45um_tt_1200mv_85c_slow.hsd
deleted file mode 100644
index 780a596afe53ae11715fa23a417ccf61412b742c..0000000000000000000000000000000000000000
Binary files a/SPI/db/SPI_test.cycloneive_io_sim_cache.45um_tt_1200mv_85c_slow.hsd and /dev/null differ
diff --git a/SPI/db/SPI_test.db_info b/SPI/db/SPI_test.db_info
deleted file mode 100644
index 17c5075cb7ae39f842a5079297c26d5dbd225096..0000000000000000000000000000000000000000
--- a/SPI/db/SPI_test.db_info
+++ /dev/null
@@ -1,3 +0,0 @@
-Quartus_Version = Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
-Version_Index = 486699264
-Creation_Time = Wed Nov 16 15:08:01 2022
diff --git a/SPI/db/SPI_test.eda.qmsg b/SPI/db/SPI_test.eda.qmsg
deleted file mode 100644
index 27e5f718d972fd3c4d115aa608f43c27dd9bda9c..0000000000000000000000000000000000000000
--- a/SPI/db/SPI_test.eda.qmsg
+++ /dev/null
@@ -1,13 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1668613907481 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1668613907487 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 16 16:51:47 2022 " "Processing started: Wed Nov 16 16:51:47 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1668613907487 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1668613907487 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off SPI_test -c SPI_test " "Command: quartus_eda --read_settings_files=off --write_settings_files=off SPI_test -c SPI_test" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1668613907487 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1668613908108 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "SPI_test_6_1200mv_85c_slow.svo C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/ simulation " "Generated file SPI_test_6_1200mv_85c_slow.svo in folder \"C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1668613908223 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "SPI_test_6_1200mv_0c_slow.svo C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/ simulation " "Generated file SPI_test_6_1200mv_0c_slow.svo in folder \"C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1668613908245 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "SPI_test_min_1200mv_0c_fast.svo C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/ simulation " "Generated file SPI_test_min_1200mv_0c_fast.svo in folder \"C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1668613908266 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "SPI_test.svo C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/ simulation " "Generated file SPI_test.svo in folder \"C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1668613908286 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "SPI_test_6_1200mv_85c_v_slow.sdo C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/ simulation " "Generated file SPI_test_6_1200mv_85c_v_slow.sdo in folder \"C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1668613908307 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "SPI_test_6_1200mv_0c_v_slow.sdo C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/ simulation " "Generated file SPI_test_6_1200mv_0c_v_slow.sdo in folder \"C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1668613908327 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "SPI_test_min_1200mv_0c_v_fast.sdo C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/ simulation " "Generated file SPI_test_min_1200mv_0c_v_fast.sdo in folder \"C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1668613908344 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "SPI_test_v.sdo C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/ simulation " "Generated file SPI_test_v.sdo in folder \"C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1668613908361 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4635 " "Peak virtual memory: 4635 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1668613908422 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 16 16:51:48 2022 " "Processing ended: Wed Nov 16 16:51:48 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1668613908422 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1668613908422 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1668613908422 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1668613908422 ""}
diff --git a/SPI/db/SPI_test.fit.qmsg b/SPI/db/SPI_test.fit.qmsg
deleted file mode 100644
index 3f777e71c73040f1f977c2eac07d7e776a7bbee1..0000000000000000000000000000000000000000
--- a/SPI/db/SPI_test.fit.qmsg
+++ /dev/null
@@ -1,49 +0,0 @@
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1668613894215 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1668613894215 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "SPI_test EP4CE22F17C6 " "Selected device EP4CE22F17C6 for design \"SPI_test\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1668613894224 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1668613894273 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1668613894273 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1668613894410 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1668613894418 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10F17C6 " "Device EP4CE10F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1668613894739 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C6 " "Device EP4CE6F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1668613894739 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C6 " "Device EP4CE15F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1668613894739 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1668613894739 ""}
-{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 381 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1668613894742 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 383 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1668613894742 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 385 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1668613894742 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 387 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1668613894742 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 389 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1668613894742 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1668613894742 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1668613894744 ""}
-{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "80 99 " "No exact pin location assignment(s) for 80 pins of 99 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1668613895033 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "SPI_test.sdc " "Synopsys Design Constraints File file not found: 'SPI_test.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1668613895228 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1668613895228 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1668613895230 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1668613895230 ""}
-{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1668613895230 ""}
-{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "GPIO_0_PI\[8\]~input (placed in PIN G2 (DIFFIO_L6p, DQS0L/CQ1L,DPCLK0)) " "Automatically promoted node GPIO_0_PI\[8\]~input (placed in PIN G2 (DIFFIO_L6p, DQS0L/CQ1L,DPCLK0))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G0 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G0" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1668613895248 ""} } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 372 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1668613895248 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1668613895450 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1668613895450 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1668613895450 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1668613895451 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1668613895452 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1668613895452 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1668613895452 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1668613895452 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1668613895463 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1668613895464 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1668613895464 ""}
-{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "79 unused 2.5V 7 0 72 " "Number of I/O pins in group: 79 (unused VREF, 2.5V VCCIO, 7 input, 0 output, 72 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Design Software" 0 -1 1668613895467 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Design Software" 0 -1 1668613895467 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1668613895467 ""}
-{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 2.5V 9 5 " "I/O bank number 1 does not use VREF pins and has 2.5V VCCIO pins. 9 total pin(s) used -- 5 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1668613895468 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 2.5V 1 15 " "I/O bank number 2 does not use VREF pins and has 2.5V VCCIO pins. 1 total pin(s) used -- 15 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1668613895468 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 1 24 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 24 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1668613895468 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 20 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 20 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1668613895468 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 1 17 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 17 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1668613895468 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 12 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 12 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1668613895468 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use 2.5V 8 16 " "I/O bank number 7 does not use VREF pins and has 2.5V VCCIO pins. 8 total pin(s) used -- 16 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1668613895468 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use 2.5V 4 20 " "I/O bank number 8 does not use VREF pins and has 2.5V VCCIO pins. 4 total pin(s) used -- 20 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1668613895468 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Design Software" 0 -1 1668613895468 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1668613895468 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1668613895974 ""}
-{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1668613895979 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1668613896613 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1668613896690 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1668613896715 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1668613898460 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Fitter placement operations ending: elapsed time is 00:00:02" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1668613898460 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1668613898688 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X10_Y23 X20_Y34 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X10_Y23 to location X20_Y34" { } { { "loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X10_Y23 to location X20_Y34"} { { 12 { 0 ""} 10 23 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1668613899331 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1668613899331 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1668613899715 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1668613899715 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1668613899718 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.11 " "Total time spent on timing analysis during the Fitter is 0.11 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1668613899824 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1668613899831 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1668613900003 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1668613900003 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1668613900129 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1668613900481 ""}
-{ "Warning" "WFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE" "80 " "Following 80 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_2\[0\] a permanently disabled " "Pin GPIO_2\[0\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_2[0] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 23 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_2\[1\] a permanently disabled " "Pin GPIO_2\[1\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_2[1] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 24 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_2\[2\] a permanently disabled " "Pin GPIO_2\[2\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_2[2] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 25 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_2\[3\] a permanently disabled " "Pin GPIO_2\[3\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_2[3] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 26 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_2\[4\] a permanently disabled " "Pin GPIO_2\[4\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_2[4] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 27 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_2\[5\] a permanently disabled " "Pin GPIO_2\[5\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_2[5] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 28 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_2\[6\] a permanently disabled " "Pin GPIO_2\[6\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_2[6] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 29 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_2\[7\] a permanently disabled " "Pin GPIO_2\[7\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_2[7] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 30 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_2\[8\] a permanently disabled " "Pin GPIO_2\[8\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_2[8] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 31 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_2\[9\] a permanently disabled " "Pin GPIO_2\[9\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_2[9] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 32 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_2\[10\] a permanently disabled " "Pin GPIO_2\[10\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_2[10] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 33 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_2\[11\] a permanently disabled " "Pin GPIO_2\[11\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_2[11] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 34 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_2\[12\] a permanently disabled " "Pin GPIO_2\[12\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_2[12] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 35 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[0\] a permanently disabled " "Pin GPIO_0_PI\[0\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[0] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 39 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[1\] a permanently disabled " "Pin GPIO_0_PI\[1\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[1] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 40 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[2\] a permanently disabled " "Pin GPIO_0_PI\[2\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[2] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 41 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[3\] a permanently disabled " "Pin GPIO_0_PI\[3\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[3] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 42 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[4\] a permanently disabled " "Pin GPIO_0_PI\[4\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[4] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 43 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[5\] a permanently disabled " "Pin GPIO_0_PI\[5\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[5] } } } { "c:/intelfpga_lite/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0_PI\[5\]" } } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 44 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[6\] a permanently disabled " "Pin GPIO_0_PI\[6\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[6] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 45 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[7\] a permanently disabled " "Pin GPIO_0_PI\[7\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[7] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 46 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[12\] a permanently disabled " "Pin GPIO_0_PI\[12\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[12] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 50 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[13\] a permanently disabled " "Pin GPIO_0_PI\[13\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[13] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 51 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[14\] a permanently disabled " "Pin GPIO_0_PI\[14\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[14] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 52 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[15\] a permanently disabled " "Pin GPIO_0_PI\[15\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[15] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 53 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[16\] a permanently disabled " "Pin GPIO_0_PI\[16\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[16] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 54 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[17\] a permanently disabled " "Pin GPIO_0_PI\[17\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[17] } } } { "c:/intelfpga_lite/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0_PI\[17\]" } } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 55 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[18\] a permanently disabled " "Pin GPIO_0_PI\[18\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[18] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 56 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[19\] a permanently disabled " "Pin GPIO_0_PI\[19\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[19] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 57 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[20\] a permanently disabled " "Pin GPIO_0_PI\[20\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[20] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 58 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[21\] a permanently disabled " "Pin GPIO_0_PI\[21\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[21] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 59 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[22\] a permanently disabled " "Pin GPIO_0_PI\[22\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[22] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 60 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[23\] a permanently disabled " "Pin GPIO_0_PI\[23\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[23] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 61 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[24\] a permanently disabled " "Pin GPIO_0_PI\[24\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[24] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 62 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[25\] a permanently disabled " "Pin GPIO_0_PI\[25\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[25] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 63 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[26\] a permanently disabled " "Pin GPIO_0_PI\[26\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[26] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 64 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[27\] a permanently disabled " "Pin GPIO_0_PI\[27\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[27] } } } { "c:/intelfpga_lite/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0_PI\[27\]" } } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 65 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[28\] a permanently disabled " "Pin GPIO_0_PI\[28\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[28] } } } { "c:/intelfpga_lite/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0_PI\[28\]" } } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 66 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[29\] a permanently disabled " "Pin GPIO_0_PI\[29\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[29] } } } { "c:/intelfpga_lite/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0_PI\[29\]" } } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 67 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[30\] a permanently disabled " "Pin GPIO_0_PI\[30\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[30] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 68 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[32\] a permanently disabled " "Pin GPIO_0_PI\[32\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[32] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 70 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[33\] a permanently disabled " "Pin GPIO_0_PI\[33\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[33] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 71 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[0\] a permanently disabled " "Pin GPIO_1\[0\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[0] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 74 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[1\] a permanently disabled " "Pin GPIO_1\[1\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[1] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 75 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[2\] a permanently disabled " "Pin GPIO_1\[2\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[2] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 76 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[3\] a permanently disabled " "Pin GPIO_1\[3\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[3] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 77 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[4\] a permanently disabled " "Pin GPIO_1\[4\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[4] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 78 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[5\] a permanently disabled " "Pin GPIO_1\[5\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[5] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 79 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[6\] a permanently disabled " "Pin GPIO_1\[6\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[6] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 80 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[7\] a permanently disabled " "Pin GPIO_1\[7\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[7] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 81 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[8\] a permanently disabled " "Pin GPIO_1\[8\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[8] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 82 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[9\] a permanently disabled " "Pin GPIO_1\[9\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[9] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 83 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[10\] a permanently disabled " "Pin GPIO_1\[10\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[10] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 84 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[11\] a permanently disabled " "Pin GPIO_1\[11\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[11] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 85 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[12\] a permanently disabled " "Pin GPIO_1\[12\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[12] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 86 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[13\] a permanently disabled " "Pin GPIO_1\[13\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[13] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 87 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[14\] a permanently disabled " "Pin GPIO_1\[14\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[14] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 88 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[15\] a permanently disabled " "Pin GPIO_1\[15\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[15] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 89 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[16\] a permanently disabled " "Pin GPIO_1\[16\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[16] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 90 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[17\] a permanently disabled " "Pin GPIO_1\[17\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[17] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 91 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[18\] a permanently disabled " "Pin GPIO_1\[18\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[18] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 92 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[19\] a permanently disabled " "Pin GPIO_1\[19\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[19] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 93 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[20\] a permanently disabled " "Pin GPIO_1\[20\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[20] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 94 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[21\] a permanently disabled " "Pin GPIO_1\[21\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[21] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 95 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[22\] a permanently disabled " "Pin GPIO_1\[22\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[22] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 96 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[23\] a permanently disabled " "Pin GPIO_1\[23\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[23] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 97 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[24\] a permanently disabled " "Pin GPIO_1\[24\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[24] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 98 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[25\] a permanently disabled " "Pin GPIO_1\[25\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[25] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 99 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[26\] a permanently disabled " "Pin GPIO_1\[26\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[26] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 100 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[27\] a permanently disabled " "Pin GPIO_1\[27\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[27] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 101 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[28\] a permanently disabled " "Pin GPIO_1\[28\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[28] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 102 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[29\] a permanently disabled " "Pin GPIO_1\[29\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[29] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 103 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[30\] a permanently disabled " "Pin GPIO_1\[30\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[30] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 104 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[31\] a permanently disabled " "Pin GPIO_1\[31\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[31] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 105 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[32\] a permanently disabled " "Pin GPIO_1\[32\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[32] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 106 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[33\] a permanently disabled " "Pin GPIO_1\[33\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[33] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 107 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[8\] a permanently disabled " "Pin GPIO_0_PI\[8\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[8] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 47 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[9\] a permanently disabled " "Pin GPIO_0_PI\[9\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[9] } } } { "c:/intelfpga_lite/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0_PI\[9\]" } } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 48 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[10\] a permanently disabled " "Pin GPIO_0_PI\[10\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[10] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 49 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[31\] a permanently disabled " "Pin GPIO_0_PI\[31\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[31] } } } { "c:/intelfpga_lite/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0_PI\[31\]" } } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 69 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613900700 ""} } { } 0 169064 "Following %1!d! pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" 0 0 "Fitter" 0 -1 1668613900700 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/damie/Documents/Minibot/SPI/output_files/SPI_test.fit.smsg " "Generated suppressed messages file C:/Users/damie/Documents/Minibot/SPI/output_files/SPI_test.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1668613900754 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5515 " "Peak virtual memory: 5515 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1668613900983 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 16 16:51:40 2022 " "Processing ended: Wed Nov 16 16:51:40 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1668613900983 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1668613900983 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Total CPU time (on all processors): 00:00:09" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1668613900983 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1668613900983 ""}
diff --git a/SPI/db/SPI_test.hier_info b/SPI/db/SPI_test.hier_info
deleted file mode 100644
index a57aecdb29b44c87451940b809a82978691fd4ef..0000000000000000000000000000000000000000
--- a/SPI/db/SPI_test.hier_info
+++ /dev/null
@@ -1,210 +0,0 @@
-|MyDE0_Nano
-CLOCK_50 => ~NO_FANOUT~
-LED[0] << <GND>
-LED[1] << <GND>
-LED[2] << <GND>
-LED[3] << <GND>
-LED[4] << <GND>
-LED[5] << <GND>
-LED[6] << <GND>
-LED[7] << <GND>
-KEY[0] => ~NO_FANOUT~
-KEY[1] => ~NO_FANOUT~
-GPIO_2[0] <> <UNC>
-GPIO_2[1] <> <UNC>
-GPIO_2[2] <> <UNC>
-GPIO_2[3] <> <UNC>
-GPIO_2[4] <> <UNC>
-GPIO_2[5] <> <UNC>
-GPIO_2[6] <> <UNC>
-GPIO_2[7] <> <UNC>
-GPIO_2[8] <> <UNC>
-GPIO_2[9] <> <UNC>
-GPIO_2[10] <> <UNC>
-GPIO_2[11] <> <UNC>
-GPIO_2[12] <> <UNC>
-GPIO_2_IN[0] => ~NO_FANOUT~
-GPIO_2_IN[1] => ~NO_FANOUT~
-GPIO_2_IN[2] => ~NO_FANOUT~
-GPIO_0_PI[0] <> <UNC>
-GPIO_0_PI[1] <> <UNC>
-GPIO_0_PI[2] <> <UNC>
-GPIO_0_PI[3] <> <UNC>
-GPIO_0_PI[4] <> <UNC>
-GPIO_0_PI[5] <> <UNC>
-GPIO_0_PI[6] <> <UNC>
-GPIO_0_PI[7] <> <UNC>
-GPIO_0_PI[11] <> GPIO_0_PI[11]
-GPIO_0_PI[12] <> <UNC>
-GPIO_0_PI[13] <> <UNC>
-GPIO_0_PI[14] <> <UNC>
-GPIO_0_PI[15] <> <UNC>
-GPIO_0_PI[16] <> <UNC>
-GPIO_0_PI[17] <> <UNC>
-GPIO_0_PI[18] <> <UNC>
-GPIO_0_PI[19] <> <UNC>
-GPIO_0_PI[20] <> <UNC>
-GPIO_0_PI[21] <> <UNC>
-GPIO_0_PI[22] <> <UNC>
-GPIO_0_PI[23] <> <UNC>
-GPIO_0_PI[24] <> <UNC>
-GPIO_0_PI[25] <> <UNC>
-GPIO_0_PI[26] <> <UNC>
-GPIO_0_PI[27] <> <UNC>
-GPIO_0_PI[28] <> <UNC>
-GPIO_0_PI[29] <> <UNC>
-GPIO_0_PI[30] <> <UNC>
-GPIO_0_PI[32] <> <UNC>
-GPIO_0_PI[33] <> <UNC>
-GPIO_0_PI_IN[0] => ~NO_FANOUT~
-GPIO_0_PI_IN[1] => ~NO_FANOUT~
-GPIO_1[0] <> <UNC>
-GPIO_1[1] <> <UNC>
-GPIO_1[2] <> <UNC>
-GPIO_1[3] <> <UNC>
-GPIO_1[4] <> <UNC>
-GPIO_1[5] <> <UNC>
-GPIO_1[6] <> <UNC>
-GPIO_1[7] <> <UNC>
-GPIO_1[8] <> <UNC>
-GPIO_1[9] <> <UNC>
-GPIO_1[10] <> <UNC>
-GPIO_1[11] <> <UNC>
-GPIO_1[12] <> <UNC>
-GPIO_1[13] <> <UNC>
-GPIO_1[14] <> <UNC>
-GPIO_1[15] <> <UNC>
-GPIO_1[16] <> <UNC>
-GPIO_1[17] <> <UNC>
-GPIO_1[18] <> <UNC>
-GPIO_1[19] <> <UNC>
-GPIO_1[20] <> <UNC>
-GPIO_1[21] <> <UNC>
-GPIO_1[22] <> <UNC>
-GPIO_1[23] <> <UNC>
-GPIO_1[24] <> <UNC>
-GPIO_1[25] <> <UNC>
-GPIO_1[26] <> <UNC>
-GPIO_1[27] <> <UNC>
-GPIO_1[28] <> <UNC>
-GPIO_1[29] <> <UNC>
-GPIO_1[30] <> <UNC>
-GPIO_1[31] <> <UNC>
-GPIO_1[32] <> <UNC>
-GPIO_1[33] <> <UNC>
-GPIO_1_IN[0] => ~NO_FANOUT~
-GPIO_1_IN[1] => ~NO_FANOUT~
-
-
-|MyDE0_Nano|spi_slave:spi_slave_instance
-sck => q[0]~reg0.CLK
-sck => q[1]~reg0.CLK
-sck => q[2]~reg0.CLK
-sck => q[3]~reg0.CLK
-sck => q[4]~reg0.CLK
-sck => q[5]~reg0.CLK
-sck => q[6]~reg0.CLK
-sck => q[7]~reg0.CLK
-sck => q[8]~reg0.CLK
-sck => q[9]~reg0.CLK
-sck => q[10]~reg0.CLK
-sck => q[11]~reg0.CLK
-sck => q[12]~reg0.CLK
-sck => q[13]~reg0.CLK
-sck => q[14]~reg0.CLK
-sck => q[15]~reg0.CLK
-sck => q[16]~reg0.CLK
-sck => q[17]~reg0.CLK
-sck => q[18]~reg0.CLK
-sck => q[19]~reg0.CLK
-sck => q[20]~reg0.CLK
-sck => q[21]~reg0.CLK
-sck => q[22]~reg0.CLK
-sck => q[23]~reg0.CLK
-sck => q[24]~reg0.CLK
-sck => q[25]~reg0.CLK
-sck => q[26]~reg0.CLK
-sck => q[27]~reg0.CLK
-sck => q[28]~reg0.CLK
-sck => q[29]~reg0.CLK
-sck => q[30]~reg0.CLK
-sck => q[31]~reg0.CLK
-sck => cnt[0].CLK
-sck => cnt[1].CLK
-sck => cnt[2].CLK
-sck => cnt[3].CLK
-sck => cnt[4].CLK
-sck => qdelayed.CLK
-mosi => q[0]~reg0.DATAIN
-miso <= miso.DB_MAX_OUTPUT_PORT_TYPE
-reset => cnt[0].ACLR
-reset => cnt[1].ACLR
-reset => cnt[2].ACLR
-reset => cnt[3].ACLR
-reset => cnt[4].ACLR
-d[0] => q.DATAB
-d[1] => q.DATAB
-d[2] => q.DATAB
-d[3] => q.DATAB
-d[4] => q.DATAB
-d[5] => q.DATAB
-d[6] => q.DATAB
-d[7] => q.DATAB
-d[8] => q.DATAB
-d[9] => q.DATAB
-d[10] => q.DATAB
-d[11] => q.DATAB
-d[12] => q.DATAB
-d[13] => q.DATAB
-d[14] => q.DATAB
-d[15] => q.DATAB
-d[16] => q.DATAB
-d[17] => q.DATAB
-d[18] => q.DATAB
-d[19] => q.DATAB
-d[20] => q.DATAB
-d[21] => q.DATAB
-d[22] => q.DATAB
-d[23] => q.DATAB
-d[24] => q.DATAB
-d[25] => q.DATAB
-d[26] => q.DATAB
-d[27] => q.DATAB
-d[28] => q.DATAB
-d[29] => q.DATAB
-d[30] => q.DATAB
-d[31] => miso.DATAB
-q[0] <= q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-q[1] <= q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-q[2] <= q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-q[3] <= q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-q[4] <= q[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-q[5] <= q[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-q[6] <= q[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-q[7] <= q[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-q[8] <= q[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-q[9] <= q[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-q[10] <= q[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-q[11] <= q[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-q[12] <= q[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-q[13] <= q[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-q[14] <= q[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-q[15] <= q[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-q[16] <= q[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-q[17] <= q[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-q[18] <= q[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-q[19] <= q[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-q[20] <= q[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-q[21] <= q[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-q[22] <= q[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-q[23] <= q[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-q[24] <= q[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-q[25] <= q[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-q[26] <= q[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-q[27] <= q[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-q[28] <= q[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-q[29] <= q[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-q[30] <= q[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-q[31] <= q[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-
-
diff --git a/SPI/db/SPI_test.hif b/SPI/db/SPI_test.hif
deleted file mode 100644
index c01f133156ca856025528f1b9b406ca09edc6451..0000000000000000000000000000000000000000
Binary files a/SPI/db/SPI_test.hif and /dev/null differ
diff --git a/SPI/db/SPI_test.lpc.html b/SPI/db/SPI_test.lpc.html
deleted file mode 100644
index 45dbcf5802437c6d583d2076834e65a506487566..0000000000000000000000000000000000000000
--- a/SPI/db/SPI_test.lpc.html
+++ /dev/null
@@ -1,34 +0,0 @@
-<TABLE>
-<TR bgcolor="#C0C0C0">
-<TH>Hierarchy</TH>
-<TH>Input</TH>
-<TH>Constant Input</TH>
-<TH>Unused Input</TH>
-<TH>Floating Input</TH>
-<TH>Output</TH>
-<TH>Constant Output</TH>
-<TH>Unused Output</TH>
-<TH>Floating Output</TH>
-<TH>Bidir</TH>
-<TH>Constant Bidir</TH>
-<TH>Unused Bidir</TH>
-<TH>Input only Bidir</TH>
-<TH>Output only Bidir</TH>
-</TR>
-<TR >
-<TD >spi_slave_instance</TD>
-<TD >34</TD>
-<TD >31</TD>
-<TD >0</TD>
-<TD >31</TD>
-<TD >33</TD>
-<TD >31</TD>
-<TD >31</TD>
-<TD >31</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-</TABLE>
diff --git a/SPI/db/SPI_test.lpc.rdb b/SPI/db/SPI_test.lpc.rdb
deleted file mode 100644
index 06df00748447d62c3625085380b363150edbff41..0000000000000000000000000000000000000000
Binary files a/SPI/db/SPI_test.lpc.rdb and /dev/null differ
diff --git a/SPI/db/SPI_test.lpc.txt b/SPI/db/SPI_test.lpc.txt
deleted file mode 100644
index d1d548f3974446d1b4cd730dbc80b53bc26ea22d..0000000000000000000000000000000000000000
--- a/SPI/db/SPI_test.lpc.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Legal Partition Candidates ;
-+--------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
-+--------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; spi_slave_instance ; 34 ; 31 ; 0 ; 31 ; 33 ; 31 ; 31 ; 31 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-+--------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/SPI/db/SPI_test.map.ammdb b/SPI/db/SPI_test.map.ammdb
deleted file mode 100644
index 46055fc4bff834e7f8d7332b55c408fdc3d36685..0000000000000000000000000000000000000000
Binary files a/SPI/db/SPI_test.map.ammdb and /dev/null differ
diff --git a/SPI/db/SPI_test.map.bpm b/SPI/db/SPI_test.map.bpm
deleted file mode 100644
index 45f3acd37f54f21532bf60075db14ee187dcb40b..0000000000000000000000000000000000000000
Binary files a/SPI/db/SPI_test.map.bpm and /dev/null differ
diff --git a/SPI/db/SPI_test.map.cdb b/SPI/db/SPI_test.map.cdb
deleted file mode 100644
index cff4a2060259c339f188c7ba0d1735c3e28444ab..0000000000000000000000000000000000000000
Binary files a/SPI/db/SPI_test.map.cdb and /dev/null differ
diff --git a/SPI/db/SPI_test.map.hdb b/SPI/db/SPI_test.map.hdb
deleted file mode 100644
index f5a14bf4489d7e335bb8a836e4ea593c649f632a..0000000000000000000000000000000000000000
Binary files a/SPI/db/SPI_test.map.hdb and /dev/null differ
diff --git a/SPI/db/SPI_test.map.kpt b/SPI/db/SPI_test.map.kpt
deleted file mode 100644
index 82a0a9187b21a934d54cf265f0f636bc3c3b39dc..0000000000000000000000000000000000000000
Binary files a/SPI/db/SPI_test.map.kpt and /dev/null differ
diff --git a/SPI/db/SPI_test.map.logdb b/SPI/db/SPI_test.map.logdb
deleted file mode 100644
index 626799f0f85326a8c1fc522db584e86cdfccd51f..0000000000000000000000000000000000000000
--- a/SPI/db/SPI_test.map.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/SPI/db/SPI_test.map.qmsg b/SPI/db/SPI_test.map.qmsg
deleted file mode 100644
index cedeba08a095824a167615a81f3e85692b1823c7..0000000000000000000000000000000000000000
--- a/SPI/db/SPI_test.map.qmsg
+++ /dev/null
@@ -1,21 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1668613881605 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1668613881612 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 16 16:51:21 2022 " "Processing started: Wed Nov 16 16:51:21 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1668613881612 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1668613881612 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off SPI_test -c SPI_test " "Command: quartus_map --read_settings_files=on --write_settings_files=off SPI_test -c SPI_test" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1668613881612 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1668613882179 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1668613882179 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mytestbench.sv 1 1 " "Found 1 design units, including 1 entities, in source file mytestbench.sv" { { "Info" "ISGN_ENTITY_NAME" "1 MyTestbench " "Found entity 1: MyTestbench" { } { { "MyTestbench.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyTestbench.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1668613891804 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1668613891804 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "myspi.sv 1 1 " "Found 1 design units, including 1 entities, in source file myspi.sv" { { "Info" "ISGN_ENTITY_NAME" "1 spi_slave " "Found entity 1: spi_slave" { } { { "MySPI.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MySPI.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1668613891808 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1668613891808 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "myde0_nano.sv 1 1 " "Found 1 design units, including 1 entities, in source file myde0_nano.sv" { { "Info" "ISGN_ENTITY_NAME" "1 MyDE0_Nano " "Found entity 1: MyDE0_Nano" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1668613891812 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1668613891812 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "MyDE0_Nano " "Elaborating entity \"MyDE0_Nano\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1668613891845 ""}
-{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "ENC_1B MyDE0_Nano.sv(47) " "Verilog HDL or VHDL warning at MyDE0_Nano.sv(47): object \"ENC_1B\" assigned a value but never read" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 47 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1668613891846 "|MyDE0_Nano"}
-{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "ENC_2A MyDE0_Nano.sv(47) " "Verilog HDL or VHDL warning at MyDE0_Nano.sv(47): object \"ENC_2A\" assigned a value but never read" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 47 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1668613891846 "|MyDE0_Nano"}
-{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "ENC_2B MyDE0_Nano.sv(47) " "Verilog HDL or VHDL warning at MyDE0_Nano.sv(47): object \"ENC_2B\" assigned a value but never read" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 47 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1668613891846 "|MyDE0_Nano"}
-{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LED MyDE0_Nano.sv(7) " "Output port \"LED\" at MyDE0_Nano.sv(7) has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 7 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1668613891846 "|MyDE0_Nano"}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spi_slave spi_slave:spi_slave_instance " "Elaborating entity \"spi_slave\" for hierarchy \"spi_slave:spi_slave_instance\"" { } { { "MyDE0_Nano.sv" "spi_slave_instance" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 39 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1668613891847 ""}
-{ "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI_HDR" "" "The following bidirectional pins have no drivers" { { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[8\] " "bidirectional pin \"GPIO_0_PI\[8\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[9\] " "bidirectional pin \"GPIO_0_PI\[9\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[10\] " "bidirectional pin \"GPIO_0_PI\[10\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[31\] " "bidirectional pin \"GPIO_0_PI\[31\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_2\[0\] " "bidirectional pin \"GPIO_2\[0\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_2\[1\] " "bidirectional pin \"GPIO_2\[1\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_2\[2\] " "bidirectional pin \"GPIO_2\[2\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_2\[3\] " "bidirectional pin \"GPIO_2\[3\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_2\[4\] " "bidirectional pin \"GPIO_2\[4\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_2\[5\] " "bidirectional pin \"GPIO_2\[5\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_2\[6\] " "bidirectional pin \"GPIO_2\[6\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_2\[7\] " "bidirectional pin \"GPIO_2\[7\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_2\[8\] " "bidirectional pin \"GPIO_2\[8\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_2\[9\] " "bidirectional pin \"GPIO_2\[9\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_2\[10\] " "bidirectional pin \"GPIO_2\[10\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_2\[11\] " "bidirectional pin \"GPIO_2\[11\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_2\[12\] " "bidirectional pin \"GPIO_2\[12\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[0\] " "bidirectional pin \"GPIO_0_PI\[0\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[1\] " "bidirectional pin \"GPIO_0_PI\[1\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[2\] " "bidirectional pin \"GPIO_0_PI\[2\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[3\] " "bidirectional pin \"GPIO_0_PI\[3\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[4\] " "bidirectional pin \"GPIO_0_PI\[4\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[5\] " "bidirectional pin \"GPIO_0_PI\[5\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[6\] " "bidirectional pin \"GPIO_0_PI\[6\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[7\] " "bidirectional pin \"GPIO_0_PI\[7\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[12\] " "bidirectional pin \"GPIO_0_PI\[12\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[13\] " "bidirectional pin \"GPIO_0_PI\[13\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[14\] " "bidirectional pin \"GPIO_0_PI\[14\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[15\] " "bidirectional pin \"GPIO_0_PI\[15\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[16\] " "bidirectional pin \"GPIO_0_PI\[16\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[17\] " "bidirectional pin \"GPIO_0_PI\[17\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[18\] " "bidirectional pin \"GPIO_0_PI\[18\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[19\] " "bidirectional pin \"GPIO_0_PI\[19\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[20\] " "bidirectional pin \"GPIO_0_PI\[20\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[21\] " "bidirectional pin \"GPIO_0_PI\[21\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[22\] " "bidirectional pin \"GPIO_0_PI\[22\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[23\] " "bidirectional pin \"GPIO_0_PI\[23\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[24\] " "bidirectional pin \"GPIO_0_PI\[24\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[25\] " "bidirectional pin \"GPIO_0_PI\[25\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[26\] " "bidirectional pin \"GPIO_0_PI\[26\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[27\] " "bidirectional pin \"GPIO_0_PI\[27\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[28\] " "bidirectional pin \"GPIO_0_PI\[28\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[29\] " "bidirectional pin \"GPIO_0_PI\[29\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[30\] " "bidirectional pin \"GPIO_0_PI\[30\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[32\] " "bidirectional pin \"GPIO_0_PI\[32\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[33\] " "bidirectional pin \"GPIO_0_PI\[33\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[0\] " "bidirectional pin \"GPIO_1\[0\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[1\] " "bidirectional pin \"GPIO_1\[1\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[2\] " "bidirectional pin \"GPIO_1\[2\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[3\] " "bidirectional pin \"GPIO_1\[3\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[4\] " "bidirectional pin \"GPIO_1\[4\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[5\] " "bidirectional pin \"GPIO_1\[5\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[6\] " "bidirectional pin \"GPIO_1\[6\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[7\] " "bidirectional pin \"GPIO_1\[7\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[8\] " "bidirectional pin \"GPIO_1\[8\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[9\] " "bidirectional pin \"GPIO_1\[9\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[10\] " "bidirectional pin \"GPIO_1\[10\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[11\] " "bidirectional pin \"GPIO_1\[11\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[12\] " "bidirectional pin \"GPIO_1\[12\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[13\] " "bidirectional pin \"GPIO_1\[13\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[14\] " "bidirectional pin \"GPIO_1\[14\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[15\] " "bidirectional pin \"GPIO_1\[15\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[16\] " "bidirectional pin \"GPIO_1\[16\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[17\] " "bidirectional pin \"GPIO_1\[17\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[18\] " "bidirectional pin \"GPIO_1\[18\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[19\] " "bidirectional pin \"GPIO_1\[19\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[20\] " "bidirectional pin \"GPIO_1\[20\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[21\] " "bidirectional pin \"GPIO_1\[21\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[22\] " "bidirectional pin \"GPIO_1\[22\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[23\] " "bidirectional pin \"GPIO_1\[23\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[24\] " "bidirectional pin \"GPIO_1\[24\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[25\] " "bidirectional pin \"GPIO_1\[25\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[26\] " "bidirectional pin \"GPIO_1\[26\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[27\] " "bidirectional pin \"GPIO_1\[27\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[28\] " "bidirectional pin \"GPIO_1\[28\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[29\] " "bidirectional pin \"GPIO_1\[29\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[30\] " "bidirectional pin \"GPIO_1\[30\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[31\] " "bidirectional pin \"GPIO_1\[31\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[32\] " "bidirectional pin \"GPIO_1\[32\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[33\] " "bidirectional pin \"GPIO_1\[33\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613892180 ""} } { } 0 13039 "The following bidirectional pins have no drivers" 0 0 "Analysis & Synthesis" 0 -1 1668613892180 ""}
-{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[0\] GND " "Pin \"LED\[0\]\" is stuck at GND" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 7 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1668613892196 "|MyDE0_Nano|LED[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[1\] GND " "Pin \"LED\[1\]\" is stuck at GND" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 7 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1668613892196 "|MyDE0_Nano|LED[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[2\] GND " "Pin \"LED\[2\]\" is stuck at GND" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 7 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1668613892196 "|MyDE0_Nano|LED[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[3\] GND " "Pin \"LED\[3\]\" is stuck at GND" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 7 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1668613892196 "|MyDE0_Nano|LED[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[4\] GND " "Pin \"LED\[4\]\" is stuck at GND" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 7 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1668613892196 "|MyDE0_Nano|LED[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[5\] GND " "Pin \"LED\[5\]\" is stuck at GND" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 7 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1668613892196 "|MyDE0_Nano|LED[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[6\] GND " "Pin \"LED\[6\]\" is stuck at GND" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 7 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1668613892196 "|MyDE0_Nano|LED[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[7\] GND " "Pin \"LED\[7\]\" is stuck at GND" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 7 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1668613892196 "|MyDE0_Nano|LED[7]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1668613892196 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1668613892253 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1668613892619 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1668613892619 ""}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "10 " "Design contains 10 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "CLOCK_50 " "No output dependent on input pin \"CLOCK_50\"" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 4 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1668613892653 "|MyDE0_Nano|CLOCK_50"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[0\] " "No output dependent on input pin \"KEY\[0\]\"" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 10 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1668613892653 "|MyDE0_Nano|KEY[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[1\] " "No output dependent on input pin \"KEY\[1\]\"" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 10 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1668613892653 "|MyDE0_Nano|KEY[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "GPIO_2_IN\[0\] " "No output dependent on input pin \"GPIO_2_IN\[0\]\"" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 14 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1668613892653 "|MyDE0_Nano|GPIO_2_IN[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "GPIO_2_IN\[1\] " "No output dependent on input pin \"GPIO_2_IN\[1\]\"" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 14 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1668613892653 "|MyDE0_Nano|GPIO_2_IN[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "GPIO_2_IN\[2\] " "No output dependent on input pin \"GPIO_2_IN\[2\]\"" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 14 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1668613892653 "|MyDE0_Nano|GPIO_2_IN[2]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "GPIO_0_PI_IN\[0\] " "No output dependent on input pin \"GPIO_0_PI_IN\[0\]\"" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 18 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1668613892653 "|MyDE0_Nano|GPIO_0_PI_IN[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "GPIO_0_PI_IN\[1\] " "No output dependent on input pin \"GPIO_0_PI_IN\[1\]\"" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 18 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1668613892653 "|MyDE0_Nano|GPIO_0_PI_IN[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "GPIO_1_IN\[0\] " "No output dependent on input pin \"GPIO_1_IN\[0\]\"" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 23 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1668613892653 "|MyDE0_Nano|GPIO_1_IN[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "GPIO_1_IN\[1\] " "No output dependent on input pin \"GPIO_1_IN\[1\]\"" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 23 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1668613892653 "|MyDE0_Nano|GPIO_1_IN[1]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1668613892653 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "140 " "Implemented 140 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Implemented 10 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1668613892654 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1668613892654 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "81 " "Implemented 81 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1668613892654 ""} { "Info" "ICUT_CUT_TM_LCELLS" "41 " "Implemented 41 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1668613892654 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1668613892654 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 106 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 106 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4777 " "Peak virtual memory: 4777 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1668613892673 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 16 16:51:32 2022 " "Processing ended: Wed Nov 16 16:51:32 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1668613892673 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1668613892673 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:23 " "Total CPU time (on all processors): 00:00:23" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1668613892673 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1668613892673 ""}
diff --git a/SPI/db/SPI_test.map.rdb b/SPI/db/SPI_test.map.rdb
deleted file mode 100644
index e76804913bac17ed8cbc40938bca92d9f97537d3..0000000000000000000000000000000000000000
Binary files a/SPI/db/SPI_test.map.rdb and /dev/null differ
diff --git a/SPI/db/SPI_test.map_bb.cdb b/SPI/db/SPI_test.map_bb.cdb
deleted file mode 100644
index f87e016c593be6e316c61c363472104b1f883753..0000000000000000000000000000000000000000
Binary files a/SPI/db/SPI_test.map_bb.cdb and /dev/null differ
diff --git a/SPI/db/SPI_test.map_bb.hdb b/SPI/db/SPI_test.map_bb.hdb
deleted file mode 100644
index dc5670f57eeecc248ec08a74816d7ca28b75513d..0000000000000000000000000000000000000000
Binary files a/SPI/db/SPI_test.map_bb.hdb and /dev/null differ
diff --git a/SPI/db/SPI_test.map_bb.logdb b/SPI/db/SPI_test.map_bb.logdb
deleted file mode 100644
index 626799f0f85326a8c1fc522db584e86cdfccd51f..0000000000000000000000000000000000000000
--- a/SPI/db/SPI_test.map_bb.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/SPI/db/SPI_test.pplq.rdb b/SPI/db/SPI_test.pplq.rdb
deleted file mode 100644
index bb748194d4d76101d8ebb16e4b542b3db57ae70d..0000000000000000000000000000000000000000
Binary files a/SPI/db/SPI_test.pplq.rdb and /dev/null differ
diff --git a/SPI/db/SPI_test.pre_map.hdb b/SPI/db/SPI_test.pre_map.hdb
deleted file mode 100644
index ba4ac9845e271d0992a3b387f78c9057f7ddde68..0000000000000000000000000000000000000000
Binary files a/SPI/db/SPI_test.pre_map.hdb and /dev/null differ
diff --git a/SPI/db/SPI_test.root_partition.map.reg_db.cdb b/SPI/db/SPI_test.root_partition.map.reg_db.cdb
deleted file mode 100644
index 5db08b38bd4e187bed26a5555ef3a969f8030680..0000000000000000000000000000000000000000
Binary files a/SPI/db/SPI_test.root_partition.map.reg_db.cdb and /dev/null differ
diff --git a/SPI/db/SPI_test.routing.rdb b/SPI/db/SPI_test.routing.rdb
deleted file mode 100644
index 04b6a0da824cb9ad98a08f7d88eb30b745fadaf2..0000000000000000000000000000000000000000
Binary files a/SPI/db/SPI_test.routing.rdb and /dev/null differ
diff --git a/SPI/db/SPI_test.rtlv.hdb b/SPI/db/SPI_test.rtlv.hdb
deleted file mode 100644
index 37bec240f7c38572b03bee7f7e0f775754e25976..0000000000000000000000000000000000000000
Binary files a/SPI/db/SPI_test.rtlv.hdb and /dev/null differ
diff --git a/SPI/db/SPI_test.rtlv_sg.cdb b/SPI/db/SPI_test.rtlv_sg.cdb
deleted file mode 100644
index b31f18fb948a86fe116504b60334726844dfbf1e..0000000000000000000000000000000000000000
Binary files a/SPI/db/SPI_test.rtlv_sg.cdb and /dev/null differ
diff --git a/SPI/db/SPI_test.rtlv_sg_swap.cdb b/SPI/db/SPI_test.rtlv_sg_swap.cdb
deleted file mode 100644
index 497131c6b2f44d5937b05c7370eea33a25d77eca..0000000000000000000000000000000000000000
Binary files a/SPI/db/SPI_test.rtlv_sg_swap.cdb and /dev/null differ
diff --git a/SPI/db/SPI_test.sld_design_entry.sci b/SPI/db/SPI_test.sld_design_entry.sci
deleted file mode 100644
index 1d07f50023aee25013d9cdf677917eb9c483fadb..0000000000000000000000000000000000000000
Binary files a/SPI/db/SPI_test.sld_design_entry.sci and /dev/null differ
diff --git a/SPI/db/SPI_test.sld_design_entry_dsc.sci b/SPI/db/SPI_test.sld_design_entry_dsc.sci
deleted file mode 100644
index 1d07f50023aee25013d9cdf677917eb9c483fadb..0000000000000000000000000000000000000000
Binary files a/SPI/db/SPI_test.sld_design_entry_dsc.sci and /dev/null differ
diff --git a/SPI/db/SPI_test.smart_action.txt b/SPI/db/SPI_test.smart_action.txt
deleted file mode 100644
index c8e8a135c9291129f28f1fcaa018fa29a7cc96fe..0000000000000000000000000000000000000000
--- a/SPI/db/SPI_test.smart_action.txt
+++ /dev/null
@@ -1 +0,0 @@
-DONE
diff --git a/SPI/db/SPI_test.sta.qmsg b/SPI/db/SPI_test.sta.qmsg
deleted file mode 100644
index 299fef0f255f3f1b6f144067f9d5793f75ee80bb..0000000000000000000000000000000000000000
--- a/SPI/db/SPI_test.sta.qmsg
+++ /dev/null
@@ -1,42 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1668613904438 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1668613904444 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 16 16:51:44 2022 " "Processing started: Wed Nov 16 16:51:44 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1668613904444 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1668613904444 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta SPI_test -c SPI_test " "Command: quartus_sta SPI_test -c SPI_test" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1668613904444 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1668613904600 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1668613904931 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1668613904931 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1668613904976 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1668613904976 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "SPI_test.sdc " "Synopsys Design Constraints File file not found: 'SPI_test.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1668613905169 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1668613905169 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name GPIO_0_PI\[8\] GPIO_0_PI\[8\] " "create_clock -period 1.000 -name GPIO_0_PI\[8\] GPIO_0_PI\[8\]" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1668613905170 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1668613905170 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1668613905171 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1668613905171 ""}
-{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1668613905172 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1668613905181 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1668613905193 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1668613905193 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.327 " "Worst-case setup slack is -1.327" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613905197 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613905197 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.327 -40.855 GPIO_0_PI\[8\] " " -1.327 -40.855 GPIO_0_PI\[8\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613905197 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1668613905197 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.360 " "Worst-case hold slack is 0.360" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613905200 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613905200 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.360 0.000 GPIO_0_PI\[8\] " " 0.360 0.000 GPIO_0_PI\[8\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613905200 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1668613905200 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668613905205 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668613905208 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613905213 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613905213 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -41.000 GPIO_0_PI\[8\] " " -3.000 -41.000 GPIO_0_PI\[8\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613905213 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1668613905213 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1668613905236 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1668613905255 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1668613905579 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1668613905604 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1668613905608 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1668613905608 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.141 " "Worst-case setup slack is -1.141" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613905615 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613905615 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.141 -34.310 GPIO_0_PI\[8\] " " -1.141 -34.310 GPIO_0_PI\[8\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613905615 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1668613905615 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.320 " "Worst-case hold slack is 0.320" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613905641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613905641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.320 0.000 GPIO_0_PI\[8\] " " 0.320 0.000 GPIO_0_PI\[8\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613905641 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1668613905641 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668613905647 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668613905659 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613905668 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613905668 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -41.000 GPIO_0_PI\[8\] " " -3.000 -41.000 GPIO_0_PI\[8\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613905668 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1668613905668 ""}
-{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1668613905719 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1668613905817 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1668613905818 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1668613905818 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.818 " "Worst-case setup slack is -0.818" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613905821 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613905821 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.818 -23.965 GPIO_0_PI\[8\] " " -0.818 -23.965 GPIO_0_PI\[8\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613905821 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1668613905821 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.192 " "Worst-case hold slack is 0.192" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613905828 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613905828 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.192 0.000 GPIO_0_PI\[8\] " " 0.192 0.000 GPIO_0_PI\[8\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613905828 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1668613905828 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668613905833 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668613905836 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613905842 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613905842 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -43.505 GPIO_0_PI\[8\] " " -3.000 -43.505 GPIO_0_PI\[8\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613905842 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1668613905842 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1668613906289 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1668613906289 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4775 " "Peak virtual memory: 4775 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1668613906353 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 16 16:51:46 2022 " "Processing ended: Wed Nov 16 16:51:46 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1668613906353 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1668613906353 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1668613906353 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1668613906353 ""}
diff --git a/SPI/db/SPI_test.sta.rdb b/SPI/db/SPI_test.sta.rdb
deleted file mode 100644
index 388407b7486309c08d5a879a8ef9f79e6f45f04a..0000000000000000000000000000000000000000
Binary files a/SPI/db/SPI_test.sta.rdb and /dev/null differ
diff --git a/SPI/db/SPI_test.sta_cmp.6_slow_1200mv_85c.tdb b/SPI/db/SPI_test.sta_cmp.6_slow_1200mv_85c.tdb
deleted file mode 100644
index 95109a7f1f43de643114a3f5635cec9533094cef..0000000000000000000000000000000000000000
Binary files a/SPI/db/SPI_test.sta_cmp.6_slow_1200mv_85c.tdb and /dev/null differ
diff --git a/SPI/db/SPI_test.tis_db_list.ddb b/SPI/db/SPI_test.tis_db_list.ddb
deleted file mode 100644
index 2f1b02611082278cb88c6539ebb22d8569ef42fc..0000000000000000000000000000000000000000
Binary files a/SPI/db/SPI_test.tis_db_list.ddb and /dev/null differ
diff --git a/SPI/db/SPI_test.tiscmp.fast_1200mv_0c.ddb b/SPI/db/SPI_test.tiscmp.fast_1200mv_0c.ddb
deleted file mode 100644
index 5e75d2df51b19497f1523ad2824dad6d31704650..0000000000000000000000000000000000000000
Binary files a/SPI/db/SPI_test.tiscmp.fast_1200mv_0c.ddb and /dev/null differ
diff --git a/SPI/db/SPI_test.tiscmp.slow_1200mv_0c.ddb b/SPI/db/SPI_test.tiscmp.slow_1200mv_0c.ddb
deleted file mode 100644
index 1344d2e59baaf2e218b3c4b91db0408cbb5cbe58..0000000000000000000000000000000000000000
Binary files a/SPI/db/SPI_test.tiscmp.slow_1200mv_0c.ddb and /dev/null differ
diff --git a/SPI/db/SPI_test.tiscmp.slow_1200mv_85c.ddb b/SPI/db/SPI_test.tiscmp.slow_1200mv_85c.ddb
deleted file mode 100644
index 6d9c4251772fe2d7e5bb4bbfc6aefe282bc1053a..0000000000000000000000000000000000000000
Binary files a/SPI/db/SPI_test.tiscmp.slow_1200mv_85c.ddb and /dev/null differ
diff --git a/SPI/db/SPI_test.tmw_info b/SPI/db/SPI_test.tmw_info
deleted file mode 100644
index 0d68568977666b89faed039f2ee0c140e389b09c..0000000000000000000000000000000000000000
--- a/SPI/db/SPI_test.tmw_info
+++ /dev/null
@@ -1,7 +0,0 @@
-start_full_compilation:s:00:00:28
-start_analysis_synthesis:s:00:00:12-start_full_compilation
-start_analysis_elaboration:s-start_full_compilation
-start_fitter:s:00:00:08-start_full_compilation
-start_assembler:s:00:00:02-start_full_compilation
-start_timing_analyzer:s:00:00:04-start_full_compilation
-start_eda_netlist_writer:s:00:00:02-start_full_compilation
diff --git a/SPI/db/SPI_test.vpr.ammdb b/SPI/db/SPI_test.vpr.ammdb
deleted file mode 100644
index 8f7b228f96809069924730202d289353597627c8..0000000000000000000000000000000000000000
Binary files a/SPI/db/SPI_test.vpr.ammdb and /dev/null differ
diff --git a/SPI/db/SPI_test_partition_pins.json b/SPI/db/SPI_test_partition_pins.json
deleted file mode 100644
index 23b547a9767b88d29baa74b60437427cccf5959b..0000000000000000000000000000000000000000
--- a/SPI/db/SPI_test_partition_pins.json
+++ /dev/null
@@ -1,29 +0,0 @@
-{
- "partitions" : [
- {
- "name" : "Top",
- "pins" : [
- {
- "name" : "GPIO_0_PI[8]",
- "strict" : false
- },
- {
- "name" : "GPIO_0_PI[9]",
- "strict" : false
- },
- {
- "name" : "GPIO_0_PI[10]",
- "strict" : false
- },
- {
- "name" : "GPIO_0_PI[11]",
- "strict" : false
- },
- {
- "name" : "GPIO_0_PI[31]",
- "strict" : false
- }
- ]
- }
- ]
-}
\ No newline at end of file
diff --git a/SPI/db/prev_cmp_SPI_test.qmsg b/SPI/db/prev_cmp_SPI_test.qmsg
deleted file mode 100644
index 8e06d85b39c078ba6065f03e870610e02b96f831..0000000000000000000000000000000000000000
--- a/SPI/db/prev_cmp_SPI_test.qmsg
+++ /dev/null
@@ -1,140 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1668613487597 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1668613487604 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 16 16:44:47 2022 " "Processing started: Wed Nov 16 16:44:47 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1668613487604 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1668613487604 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off SPI_test -c SPI_test " "Command: quartus_map --read_settings_files=on --write_settings_files=off SPI_test -c SPI_test" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1668613487604 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1668613488282 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1668613488283 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mytestbench.sv 1 1 " "Found 1 design units, including 1 entities, in source file mytestbench.sv" { { "Info" "ISGN_ENTITY_NAME" "1 MyTestbench " "Found entity 1: MyTestbench" { } { { "MyTestbench.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyTestbench.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1668613498431 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1668613498431 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "myspi.sv 1 1 " "Found 1 design units, including 1 entities, in source file myspi.sv" { { "Info" "ISGN_ENTITY_NAME" "1 spi_slave " "Found entity 1: spi_slave" { } { { "MySPI.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MySPI.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1668613498436 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1668613498436 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "myde0_nano.sv 1 1 " "Found 1 design units, including 1 entities, in source file myde0_nano.sv" { { "Info" "ISGN_ENTITY_NAME" "1 MyDE0_Nano " "Found entity 1: MyDE0_Nano" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1668613498441 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1668613498441 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "MyDE0_Nano " "Elaborating entity \"MyDE0_Nano\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1668613498494 ""}
-{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "ENC_1B MyDE0_Nano.sv(47) " "Verilog HDL or VHDL warning at MyDE0_Nano.sv(47): object \"ENC_1B\" assigned a value but never read" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 47 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1668613498500 "|MyDE0_Nano"}
-{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "ENC_2A MyDE0_Nano.sv(47) " "Verilog HDL or VHDL warning at MyDE0_Nano.sv(47): object \"ENC_2A\" assigned a value but never read" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 47 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1668613498500 "|MyDE0_Nano"}
-{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "ENC_2B MyDE0_Nano.sv(47) " "Verilog HDL or VHDL warning at MyDE0_Nano.sv(47): object \"ENC_2B\" assigned a value but never read" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 47 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1668613498500 "|MyDE0_Nano"}
-{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LED MyDE0_Nano.sv(7) " "Output port \"LED\" at MyDE0_Nano.sv(7) has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 7 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1668613498502 "|MyDE0_Nano"}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spi_slave spi_slave:spi_slave_instance " "Elaborating entity \"spi_slave\" for hierarchy \"spi_slave:spi_slave_instance\"" { } { { "MyDE0_Nano.sv" "spi_slave_instance" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 39 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1668613498529 ""}
-{ "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI_HDR" "" "The following bidirectional pins have no drivers" { { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[8\] " "bidirectional pin \"GPIO_0_PI\[8\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[9\] " "bidirectional pin \"GPIO_0_PI\[9\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[10\] " "bidirectional pin \"GPIO_0_PI\[10\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[31\] " "bidirectional pin \"GPIO_0_PI\[31\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_2\[0\] " "bidirectional pin \"GPIO_2\[0\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_2\[1\] " "bidirectional pin \"GPIO_2\[1\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_2\[2\] " "bidirectional pin \"GPIO_2\[2\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_2\[3\] " "bidirectional pin \"GPIO_2\[3\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_2\[4\] " "bidirectional pin \"GPIO_2\[4\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_2\[5\] " "bidirectional pin \"GPIO_2\[5\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_2\[6\] " "bidirectional pin \"GPIO_2\[6\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_2\[7\] " "bidirectional pin \"GPIO_2\[7\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_2\[8\] " "bidirectional pin \"GPIO_2\[8\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_2\[9\] " "bidirectional pin \"GPIO_2\[9\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_2\[10\] " "bidirectional pin \"GPIO_2\[10\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_2\[11\] " "bidirectional pin \"GPIO_2\[11\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_2\[12\] " "bidirectional pin \"GPIO_2\[12\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[0\] " "bidirectional pin \"GPIO_0_PI\[0\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[1\] " "bidirectional pin \"GPIO_0_PI\[1\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[2\] " "bidirectional pin \"GPIO_0_PI\[2\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[3\] " "bidirectional pin \"GPIO_0_PI\[3\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[4\] " "bidirectional pin \"GPIO_0_PI\[4\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[5\] " "bidirectional pin \"GPIO_0_PI\[5\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[6\] " "bidirectional pin \"GPIO_0_PI\[6\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[7\] " "bidirectional pin \"GPIO_0_PI\[7\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[12\] " "bidirectional pin \"GPIO_0_PI\[12\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[13\] " "bidirectional pin \"GPIO_0_PI\[13\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[14\] " "bidirectional pin \"GPIO_0_PI\[14\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[15\] " "bidirectional pin \"GPIO_0_PI\[15\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[16\] " "bidirectional pin \"GPIO_0_PI\[16\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[17\] " "bidirectional pin \"GPIO_0_PI\[17\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[18\] " "bidirectional pin \"GPIO_0_PI\[18\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[19\] " "bidirectional pin \"GPIO_0_PI\[19\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[20\] " "bidirectional pin \"GPIO_0_PI\[20\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[21\] " "bidirectional pin \"GPIO_0_PI\[21\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[22\] " "bidirectional pin \"GPIO_0_PI\[22\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[23\] " "bidirectional pin \"GPIO_0_PI\[23\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[24\] " "bidirectional pin \"GPIO_0_PI\[24\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[25\] " "bidirectional pin \"GPIO_0_PI\[25\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[26\] " "bidirectional pin \"GPIO_0_PI\[26\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[27\] " "bidirectional pin \"GPIO_0_PI\[27\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[28\] " "bidirectional pin \"GPIO_0_PI\[28\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[29\] " "bidirectional pin \"GPIO_0_PI\[29\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[30\] " "bidirectional pin \"GPIO_0_PI\[30\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[32\] " "bidirectional pin \"GPIO_0_PI\[32\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0_PI\[33\] " "bidirectional pin \"GPIO_0_PI\[33\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[0\] " "bidirectional pin \"GPIO_1\[0\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[1\] " "bidirectional pin \"GPIO_1\[1\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[2\] " "bidirectional pin \"GPIO_1\[2\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[3\] " "bidirectional pin \"GPIO_1\[3\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[4\] " "bidirectional pin \"GPIO_1\[4\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[5\] " "bidirectional pin \"GPIO_1\[5\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[6\] " "bidirectional pin \"GPIO_1\[6\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[7\] " "bidirectional pin \"GPIO_1\[7\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[8\] " "bidirectional pin \"GPIO_1\[8\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[9\] " "bidirectional pin \"GPIO_1\[9\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[10\] " "bidirectional pin \"GPIO_1\[10\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[11\] " "bidirectional pin \"GPIO_1\[11\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[12\] " "bidirectional pin \"GPIO_1\[12\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[13\] " "bidirectional pin \"GPIO_1\[13\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[14\] " "bidirectional pin \"GPIO_1\[14\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[15\] " "bidirectional pin \"GPIO_1\[15\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[16\] " "bidirectional pin \"GPIO_1\[16\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[17\] " "bidirectional pin \"GPIO_1\[17\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[18\] " "bidirectional pin \"GPIO_1\[18\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[19\] " "bidirectional pin \"GPIO_1\[19\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[20\] " "bidirectional pin \"GPIO_1\[20\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[21\] " "bidirectional pin \"GPIO_1\[21\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[22\] " "bidirectional pin \"GPIO_1\[22\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[23\] " "bidirectional pin \"GPIO_1\[23\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[24\] " "bidirectional pin \"GPIO_1\[24\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[25\] " "bidirectional pin \"GPIO_1\[25\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[26\] " "bidirectional pin \"GPIO_1\[26\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[27\] " "bidirectional pin \"GPIO_1\[27\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[28\] " "bidirectional pin \"GPIO_1\[28\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[29\] " "bidirectional pin \"GPIO_1\[29\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[30\] " "bidirectional pin \"GPIO_1\[30\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[31\] " "bidirectional pin \"GPIO_1\[31\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[32\] " "bidirectional pin \"GPIO_1\[32\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[33\] " "bidirectional pin \"GPIO_1\[33\]\" has no driver" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 -1 0 } } } 0 13040 "bidirectional pin \"%1!s!\" has no driver" 0 0 "Design Software" 0 -1 1668613499032 ""} } { } 0 13039 "The following bidirectional pins have no drivers" 0 0 "Analysis & Synthesis" 0 -1 1668613499032 ""}
-{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[0\] GND " "Pin \"LED\[0\]\" is stuck at GND" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 7 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1668613499052 "|MyDE0_Nano|LED[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[1\] GND " "Pin \"LED\[1\]\" is stuck at GND" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 7 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1668613499052 "|MyDE0_Nano|LED[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[2\] GND " "Pin \"LED\[2\]\" is stuck at GND" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 7 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1668613499052 "|MyDE0_Nano|LED[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[3\] GND " "Pin \"LED\[3\]\" is stuck at GND" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 7 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1668613499052 "|MyDE0_Nano|LED[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[4\] GND " "Pin \"LED\[4\]\" is stuck at GND" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 7 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1668613499052 "|MyDE0_Nano|LED[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[5\] GND " "Pin \"LED\[5\]\" is stuck at GND" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 7 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1668613499052 "|MyDE0_Nano|LED[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[6\] GND " "Pin \"LED\[6\]\" is stuck at GND" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 7 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1668613499052 "|MyDE0_Nano|LED[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[7\] GND " "Pin \"LED\[7\]\" is stuck at GND" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 7 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1668613499052 "|MyDE0_Nano|LED[7]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1668613499052 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1668613499127 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1668613499717 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1668613499717 ""}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "10 " "Design contains 10 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "CLOCK_50 " "No output dependent on input pin \"CLOCK_50\"" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 4 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1668613499878 "|MyDE0_Nano|CLOCK_50"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[0\] " "No output dependent on input pin \"KEY\[0\]\"" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 10 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1668613499878 "|MyDE0_Nano|KEY[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[1\] " "No output dependent on input pin \"KEY\[1\]\"" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 10 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1668613499878 "|MyDE0_Nano|KEY[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "GPIO_2_IN\[0\] " "No output dependent on input pin \"GPIO_2_IN\[0\]\"" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 14 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1668613499878 "|MyDE0_Nano|GPIO_2_IN[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "GPIO_2_IN\[1\] " "No output dependent on input pin \"GPIO_2_IN\[1\]\"" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 14 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1668613499878 "|MyDE0_Nano|GPIO_2_IN[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "GPIO_2_IN\[2\] " "No output dependent on input pin \"GPIO_2_IN\[2\]\"" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 14 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1668613499878 "|MyDE0_Nano|GPIO_2_IN[2]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "GPIO_0_PI_IN\[0\] " "No output dependent on input pin \"GPIO_0_PI_IN\[0\]\"" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 18 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1668613499878 "|MyDE0_Nano|GPIO_0_PI_IN[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "GPIO_0_PI_IN\[1\] " "No output dependent on input pin \"GPIO_0_PI_IN\[1\]\"" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 18 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1668613499878 "|MyDE0_Nano|GPIO_0_PI_IN[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "GPIO_1_IN\[0\] " "No output dependent on input pin \"GPIO_1_IN\[0\]\"" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 23 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1668613499878 "|MyDE0_Nano|GPIO_1_IN[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "GPIO_1_IN\[1\] " "No output dependent on input pin \"GPIO_1_IN\[1\]\"" { } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 23 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1668613499878 "|MyDE0_Nano|GPIO_1_IN[1]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1668613499878 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "140 " "Implemented 140 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Implemented 10 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1668613499879 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1668613499879 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "81 " "Implemented 81 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1668613499879 ""} { "Info" "ICUT_CUT_TM_LCELLS" "41 " "Implemented 41 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1668613499879 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1668613499879 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 106 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 106 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4760 " "Peak virtual memory: 4760 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1668613499898 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 16 16:44:59 2022 " "Processing ended: Wed Nov 16 16:44:59 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1668613499898 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Elapsed time: 00:00:12" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1668613499898 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:25 " "Total CPU time (on all processors): 00:00:25" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1668613499898 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1668613499898 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1668613501597 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1668613501603 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 16 16:45:00 2022 " "Processing started: Wed Nov 16 16:45:00 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1668613501603 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1668613501603 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off SPI_test -c SPI_test " "Command: quartus_fit --read_settings_files=off --write_settings_files=off SPI_test -c SPI_test" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1668613501603 ""}
-{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1668613502685 ""}
-{ "Info" "0" "" "Project = SPI_test" { } { } 0 0 "Project = SPI_test" 0 0 "Fitter" 0 0 1668613502686 ""}
-{ "Info" "0" "" "Revision = SPI_test" { } { } 0 0 "Revision = SPI_test" 0 0 "Fitter" 0 0 1668613502687 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1668613502761 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1668613502762 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "SPI_test EP4CE22F17C6 " "Selected device EP4CE22F17C6 for design \"SPI_test\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1668613502775 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1668613502830 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1668613502830 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1668613503077 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1668613503119 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10F17C6 " "Device EP4CE10F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1668613503699 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C6 " "Device EP4CE6F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1668613503699 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C6 " "Device EP4CE15F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1668613503699 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1668613503699 ""}
-{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 381 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1668613503718 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 383 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1668613503718 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 385 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1668613503718 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 387 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1668613503718 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 389 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1668613503718 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1668613503718 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1668613503728 ""}
-{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "87 99 " "No exact pin location assignment(s) for 87 pins of 99 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1668613504120 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "SPI_test.sdc " "Synopsys Design Constraints File file not found: 'SPI_test.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1668613504396 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1668613504396 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1668613504398 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1668613504398 ""}
-{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1668613504399 ""}
-{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "GPIO_0_PI\[8\]~input (placed in PIN G2 (DIFFIO_L6p, DQS0L/CQ1L,DPCLK0)) " "Automatically promoted node GPIO_0_PI\[8\]~input (placed in PIN G2 (DIFFIO_L6p, DQS0L/CQ1L,DPCLK0))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G0 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G0" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1668613504418 ""} } { { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 372 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1668613504418 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1668613504654 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1668613504655 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1668613504655 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1668613504655 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1668613504656 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1668613504657 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1668613504657 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1668613504657 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1668613504668 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1668613504668 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1668613504668 ""}
-{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "86 unused 2.5V 7 0 79 " "Number of I/O pins in group: 86 (unused VREF, 2.5V VCCIO, 7 input, 0 output, 79 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Design Software" 0 -1 1668613504673 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Design Software" 0 -1 1668613504673 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1668613504673 ""}
-{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 2.5V 9 5 " "I/O bank number 1 does not use VREF pins and has 2.5V VCCIO pins. 9 total pin(s) used -- 5 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1668613504674 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 2.5V 1 15 " "I/O bank number 2 does not use VREF pins and has 2.5V VCCIO pins. 1 total pin(s) used -- 15 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1668613504674 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 1 24 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 24 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1668613504674 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 20 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 20 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1668613504674 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 1 17 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 17 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1668613504674 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 12 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 12 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1668613504674 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use 2.5V 4 20 " "I/O bank number 7 does not use VREF pins and has 2.5V VCCIO pins. 4 total pin(s) used -- 20 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1668613504674 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use 2.5V 1 23 " "I/O bank number 8 does not use VREF pins and has 2.5V VCCIO pins. 1 total pin(s) used -- 23 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1668613504674 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Design Software" 0 -1 1668613504674 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1668613504674 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:02 " "Fitter preparation operations ending: elapsed time is 00:00:02" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1668613505385 ""}
-{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1668613505399 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1668613506079 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1668613506152 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1668613506181 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1668613508111 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Fitter placement operations ending: elapsed time is 00:00:02" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1668613508111 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1668613508345 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y23 X9_Y34 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y23 to location X9_Y34" { } { { "loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y23 to location X9_Y34"} { { 12 { 0 ""} 0 23 10 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1668613508994 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1668613508994 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1668613509430 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1668613509430 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1668613509433 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.12 " "Total time spent on timing analysis during the Fitter is 0.12 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1668613509550 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1668613509559 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1668613509725 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1668613509725 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1668613509849 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1668613510262 ""}
-{ "Warning" "WFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE" "80 " "Following 80 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_2\[0\] a permanently disabled " "Pin GPIO_2\[0\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_2[0] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 23 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_2\[1\] a permanently disabled " "Pin GPIO_2\[1\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_2[1] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 24 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_2\[2\] a permanently disabled " "Pin GPIO_2\[2\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_2[2] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 25 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_2\[3\] a permanently disabled " "Pin GPIO_2\[3\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_2[3] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 26 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_2\[4\] a permanently disabled " "Pin GPIO_2\[4\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_2[4] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 27 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_2\[5\] a permanently disabled " "Pin GPIO_2\[5\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_2[5] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 28 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_2\[6\] a permanently disabled " "Pin GPIO_2\[6\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_2[6] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 29 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_2\[7\] a permanently disabled " "Pin GPIO_2\[7\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_2[7] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 30 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_2\[8\] a permanently disabled " "Pin GPIO_2\[8\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_2[8] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 31 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_2\[9\] a permanently disabled " "Pin GPIO_2\[9\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_2[9] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 32 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_2\[10\] a permanently disabled " "Pin GPIO_2\[10\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_2[10] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 33 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_2\[11\] a permanently disabled " "Pin GPIO_2\[11\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_2[11] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 34 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_2\[12\] a permanently disabled " "Pin GPIO_2\[12\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_2[12] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 13 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 35 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[0\] a permanently disabled " "Pin GPIO_0_PI\[0\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[0] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 39 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[1\] a permanently disabled " "Pin GPIO_0_PI\[1\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[1] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 40 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[2\] a permanently disabled " "Pin GPIO_0_PI\[2\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[2] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 41 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[3\] a permanently disabled " "Pin GPIO_0_PI\[3\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[3] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 42 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[4\] a permanently disabled " "Pin GPIO_0_PI\[4\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[4] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 43 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[5\] a permanently disabled " "Pin GPIO_0_PI\[5\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[5] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 44 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[6\] a permanently disabled " "Pin GPIO_0_PI\[6\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[6] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 45 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[7\] a permanently disabled " "Pin GPIO_0_PI\[7\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[7] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 46 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[12\] a permanently disabled " "Pin GPIO_0_PI\[12\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[12] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 50 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[13\] a permanently disabled " "Pin GPIO_0_PI\[13\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[13] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 51 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[14\] a permanently disabled " "Pin GPIO_0_PI\[14\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[14] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 52 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[15\] a permanently disabled " "Pin GPIO_0_PI\[15\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[15] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 53 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[16\] a permanently disabled " "Pin GPIO_0_PI\[16\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[16] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 54 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[17\] a permanently disabled " "Pin GPIO_0_PI\[17\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[17] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 55 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[18\] a permanently disabled " "Pin GPIO_0_PI\[18\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[18] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 56 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[19\] a permanently disabled " "Pin GPIO_0_PI\[19\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[19] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 57 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[20\] a permanently disabled " "Pin GPIO_0_PI\[20\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[20] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 58 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[21\] a permanently disabled " "Pin GPIO_0_PI\[21\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[21] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 59 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[22\] a permanently disabled " "Pin GPIO_0_PI\[22\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[22] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 60 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[23\] a permanently disabled " "Pin GPIO_0_PI\[23\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[23] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 61 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[24\] a permanently disabled " "Pin GPIO_0_PI\[24\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[24] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 62 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[25\] a permanently disabled " "Pin GPIO_0_PI\[25\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[25] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 63 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[26\] a permanently disabled " "Pin GPIO_0_PI\[26\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[26] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 64 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[27\] a permanently disabled " "Pin GPIO_0_PI\[27\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[27] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 65 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[28\] a permanently disabled " "Pin GPIO_0_PI\[28\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[28] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 66 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[29\] a permanently disabled " "Pin GPIO_0_PI\[29\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[29] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 67 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[30\] a permanently disabled " "Pin GPIO_0_PI\[30\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[30] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 68 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[32\] a permanently disabled " "Pin GPIO_0_PI\[32\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[32] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 70 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[33\] a permanently disabled " "Pin GPIO_0_PI\[33\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[33] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 71 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[0\] a permanently disabled " "Pin GPIO_1\[0\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[0] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 74 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[1\] a permanently disabled " "Pin GPIO_1\[1\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[1] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 75 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[2\] a permanently disabled " "Pin GPIO_1\[2\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[2] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 76 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[3\] a permanently disabled " "Pin GPIO_1\[3\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[3] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 77 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[4\] a permanently disabled " "Pin GPIO_1\[4\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[4] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 78 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[5\] a permanently disabled " "Pin GPIO_1\[5\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[5] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 79 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[6\] a permanently disabled " "Pin GPIO_1\[6\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[6] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 80 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[7\] a permanently disabled " "Pin GPIO_1\[7\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[7] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 81 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[8\] a permanently disabled " "Pin GPIO_1\[8\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[8] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 82 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[9\] a permanently disabled " "Pin GPIO_1\[9\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[9] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 83 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[10\] a permanently disabled " "Pin GPIO_1\[10\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[10] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 84 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[11\] a permanently disabled " "Pin GPIO_1\[11\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[11] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 85 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[12\] a permanently disabled " "Pin GPIO_1\[12\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[12] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 86 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[13\] a permanently disabled " "Pin GPIO_1\[13\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[13] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 87 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[14\] a permanently disabled " "Pin GPIO_1\[14\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[14] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 88 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[15\] a permanently disabled " "Pin GPIO_1\[15\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[15] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 89 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[16\] a permanently disabled " "Pin GPIO_1\[16\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[16] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 90 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[17\] a permanently disabled " "Pin GPIO_1\[17\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[17] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 91 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[18\] a permanently disabled " "Pin GPIO_1\[18\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[18] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 92 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[19\] a permanently disabled " "Pin GPIO_1\[19\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[19] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 93 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[20\] a permanently disabled " "Pin GPIO_1\[20\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[20] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 94 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[21\] a permanently disabled " "Pin GPIO_1\[21\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[21] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 95 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[22\] a permanently disabled " "Pin GPIO_1\[22\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[22] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 96 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[23\] a permanently disabled " "Pin GPIO_1\[23\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[23] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 97 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[24\] a permanently disabled " "Pin GPIO_1\[24\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[24] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 98 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[25\] a permanently disabled " "Pin GPIO_1\[25\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[25] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 99 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[26\] a permanently disabled " "Pin GPIO_1\[26\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[26] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 100 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[27\] a permanently disabled " "Pin GPIO_1\[27\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[27] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 101 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[28\] a permanently disabled " "Pin GPIO_1\[28\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[28] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 102 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[29\] a permanently disabled " "Pin GPIO_1\[29\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[29] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 103 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[30\] a permanently disabled " "Pin GPIO_1\[30\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[30] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 104 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[31\] a permanently disabled " "Pin GPIO_1\[31\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[31] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 105 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[32\] a permanently disabled " "Pin GPIO_1\[32\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[32] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 106 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[33\] a permanently disabled " "Pin GPIO_1\[33\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_1[33] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 21 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 107 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[8\] a permanently disabled " "Pin GPIO_0_PI\[8\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[8] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 47 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[9\] a permanently disabled " "Pin GPIO_0_PI\[9\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[9] } } } { "c:/intelfpga_lite/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0_PI\[9\]" } } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 48 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[10\] a permanently disabled " "Pin GPIO_0_PI\[10\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[10] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 49 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0_PI\[31\] a permanently disabled " "Pin GPIO_0_PI\[31\] has a permanently disabled output enable" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { GPIO_0_PI[31] } } } { "MyDE0_Nano.sv" "" { Text "C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv" 17 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/damie/Documents/Minibot/SPI/" { { 0 { 0 ""} 0 69 14177 15141 0 0 "" 0 "" "" } } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Design Software" 0 -1 1668613510497 ""} } { } 0 169064 "Following %1!d! pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" 0 0 "Fitter" 0 -1 1668613510497 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/damie/Documents/Minibot/SPI/output_files/SPI_test.fit.smsg " "Generated suppressed messages file C:/Users/damie/Documents/Minibot/SPI/output_files/SPI_test.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1668613510562 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5526 " "Peak virtual memory: 5526 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1668613510880 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 16 16:45:10 2022 " "Processing ended: Wed Nov 16 16:45:10 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1668613510880 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1668613510880 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:10 " "Total CPU time (on all processors): 00:00:10" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1668613510880 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1668613510880 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1668613512199 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1668613512207 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 16 16:45:12 2022 " "Processing started: Wed Nov 16 16:45:12 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1668613512207 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1668613512207 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off SPI_test -c SPI_test " "Command: quartus_asm --read_settings_files=off --write_settings_files=off SPI_test -c SPI_test" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1668613512207 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1668613512496 ""}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1668613513150 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1668613513180 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4674 " "Peak virtual memory: 4674 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1668613513399 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 16 16:45:13 2022 " "Processing ended: Wed Nov 16 16:45:13 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1668613513399 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1668613513399 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1668613513399 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1668613513399 ""}
-{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1668613514048 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1668613514778 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1668613514783 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 16 16:45:14 2022 " "Processing started: Wed Nov 16 16:45:14 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1668613514783 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1668613514783 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta SPI_test -c SPI_test " "Command: quartus_sta SPI_test -c SPI_test" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1668613514783 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1668613514955 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1668613515287 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1668613515287 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1668613515334 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1668613515334 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "SPI_test.sdc " "Synopsys Design Constraints File file not found: 'SPI_test.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1668613515517 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1668613515517 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name GPIO_0_PI\[8\] GPIO_0_PI\[8\] " "create_clock -period 1.000 -name GPIO_0_PI\[8\] GPIO_0_PI\[8\]" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1668613515518 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1668613515518 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1668613515518 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1668613515519 ""}
-{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1668613515520 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1668613515535 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1668613515551 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1668613515551 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.334 " "Worst-case setup slack is -1.334" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613515557 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613515557 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.334 -42.751 GPIO_0_PI\[8\] " " -1.334 -42.751 GPIO_0_PI\[8\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613515557 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1668613515557 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.360 " "Worst-case hold slack is 0.360" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613515560 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613515560 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.360 0.000 GPIO_0_PI\[8\] " " 0.360 0.000 GPIO_0_PI\[8\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613515560 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1668613515560 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668613515565 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668613515570 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613515576 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613515576 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -41.000 GPIO_0_PI\[8\] " " -3.000 -41.000 GPIO_0_PI\[8\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613515576 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1668613515576 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1668613515608 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1668613515631 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1668613516018 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1668613516043 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1668613516049 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1668613516049 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.134 " "Worst-case setup slack is -1.134" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613516054 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613516054 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.134 -35.714 GPIO_0_PI\[8\] " " -1.134 -35.714 GPIO_0_PI\[8\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613516054 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1668613516054 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.320 " "Worst-case hold slack is 0.320" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613516058 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613516058 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.320 0.000 GPIO_0_PI\[8\] " " 0.320 0.000 GPIO_0_PI\[8\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613516058 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1668613516058 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668613516064 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668613516067 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613516072 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613516072 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -41.000 GPIO_0_PI\[8\] " " -3.000 -41.000 GPIO_0_PI\[8\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613516072 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1668613516072 ""}
-{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1668613516092 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1668613516161 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1668613516163 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1668613516163 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.817 " "Worst-case setup slack is -0.817" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613516166 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613516166 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.817 -24.691 GPIO_0_PI\[8\] " " -0.817 -24.691 GPIO_0_PI\[8\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613516166 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1668613516166 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.193 " "Worst-case hold slack is 0.193" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613516175 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613516175 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.193 0.000 GPIO_0_PI\[8\] " " 0.193 0.000 GPIO_0_PI\[8\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613516175 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1668613516175 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668613516178 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668613516183 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613516188 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613516188 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -43.502 GPIO_0_PI\[8\] " " -3.000 -43.502 GPIO_0_PI\[8\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1668613516188 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1668613516188 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1668613516606 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1668613516607 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4774 " "Peak virtual memory: 4774 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1668613516673 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 16 16:45:16 2022 " "Processing ended: Wed Nov 16 16:45:16 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1668613516673 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1668613516673 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1668613516673 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1668613516673 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Timing Analyzer" 0 -1 1668613517923 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1668613517931 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 16 16:45:17 2022 " "Processing started: Wed Nov 16 16:45:17 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1668613517931 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1668613517931 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off SPI_test -c SPI_test " "Command: quartus_eda --read_settings_files=off --write_settings_files=off SPI_test -c SPI_test" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1668613517931 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1668613518566 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "SPI_test_6_1200mv_85c_slow.svo C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/ simulation " "Generated file SPI_test_6_1200mv_85c_slow.svo in folder \"C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1668613518705 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "SPI_test_6_1200mv_0c_slow.svo C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/ simulation " "Generated file SPI_test_6_1200mv_0c_slow.svo in folder \"C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1668613518726 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "SPI_test_min_1200mv_0c_fast.svo C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/ simulation " "Generated file SPI_test_min_1200mv_0c_fast.svo in folder \"C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1668613518753 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "SPI_test.svo C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/ simulation " "Generated file SPI_test.svo in folder \"C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1668613518787 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "SPI_test_6_1200mv_85c_v_slow.sdo C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/ simulation " "Generated file SPI_test_6_1200mv_85c_v_slow.sdo in folder \"C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1668613518813 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "SPI_test_6_1200mv_0c_v_slow.sdo C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/ simulation " "Generated file SPI_test_6_1200mv_0c_v_slow.sdo in folder \"C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1668613518847 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "SPI_test_min_1200mv_0c_v_fast.sdo C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/ simulation " "Generated file SPI_test_min_1200mv_0c_v_fast.sdo in folder \"C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1668613518868 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "SPI_test_v.sdo C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/ simulation " "Generated file SPI_test_v.sdo in folder \"C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1668613518887 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4639 " "Peak virtual memory: 4639 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1668613518924 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 16 16:45:18 2022 " "Processing ended: Wed Nov 16 16:45:18 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1668613518924 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1668613518924 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1668613518924 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1668613518924 ""}
-{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 119 s " "Quartus Prime Full Compilation was successful. 0 errors, 119 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1668613519574 ""}
diff --git a/SPI/incremental_db/README b/SPI/incremental_db/README
deleted file mode 100644
index 9f62dcda0512fec7b5b55c11a13d70f91548996f..0000000000000000000000000000000000000000
--- a/SPI/incremental_db/README
+++ /dev/null
@@ -1,11 +0,0 @@
-This folder contains data for incremental compilation.
-
-The compiled_partitions sub-folder contains previous compilation results for each partition.
-As long as this folder is preserved, incremental compilation results from earlier compiles
-can be re-used. To perform a clean compilation from source files for all partitions, both
-the db and incremental_db folder should be removed.
-
-The imported_partitions sub-folder contains the last imported QXP for each imported partition.
-As long as this folder is preserved, imported partitions will be automatically re-imported
-when the db or incremental_db/compiled_partitions folders are removed.
-
diff --git a/SPI/incremental_db/compiled_partitions/SPI_test.db_info b/SPI/incremental_db/compiled_partitions/SPI_test.db_info
deleted file mode 100644
index eef7047c22fdd6e9294f0a71ca8ebdb01c38461b..0000000000000000000000000000000000000000
--- a/SPI/incremental_db/compiled_partitions/SPI_test.db_info
+++ /dev/null
@@ -1,3 +0,0 @@
-Quartus_Version = Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
-Version_Index = 486699264
-Creation_Time = Mon Nov 14 12:03:56 2022
diff --git a/SPI/incremental_db/compiled_partitions/SPI_test.root_partition.cmp.ammdb b/SPI/incremental_db/compiled_partitions/SPI_test.root_partition.cmp.ammdb
deleted file mode 100644
index ad2841647fac329cddbcd82b2e953a255bd1df02..0000000000000000000000000000000000000000
Binary files a/SPI/incremental_db/compiled_partitions/SPI_test.root_partition.cmp.ammdb and /dev/null differ
diff --git a/SPI/incremental_db/compiled_partitions/SPI_test.root_partition.cmp.cdb b/SPI/incremental_db/compiled_partitions/SPI_test.root_partition.cmp.cdb
deleted file mode 100644
index ca29230bcba69cbf39b883f65ca51d8f4d22b9b6..0000000000000000000000000000000000000000
Binary files a/SPI/incremental_db/compiled_partitions/SPI_test.root_partition.cmp.cdb and /dev/null differ
diff --git a/SPI/incremental_db/compiled_partitions/SPI_test.root_partition.cmp.dfp b/SPI/incremental_db/compiled_partitions/SPI_test.root_partition.cmp.dfp
deleted file mode 100644
index b1c67d625638bb473b681fa4acb00be38889ece3..0000000000000000000000000000000000000000
Binary files a/SPI/incremental_db/compiled_partitions/SPI_test.root_partition.cmp.dfp and /dev/null differ
diff --git a/SPI/incremental_db/compiled_partitions/SPI_test.root_partition.cmp.hdb b/SPI/incremental_db/compiled_partitions/SPI_test.root_partition.cmp.hdb
deleted file mode 100644
index 4615269c1b68fc7c87a17948fd782093a7c676d6..0000000000000000000000000000000000000000
Binary files a/SPI/incremental_db/compiled_partitions/SPI_test.root_partition.cmp.hdb and /dev/null differ
diff --git a/SPI/incremental_db/compiled_partitions/SPI_test.root_partition.cmp.logdb b/SPI/incremental_db/compiled_partitions/SPI_test.root_partition.cmp.logdb
deleted file mode 100644
index 626799f0f85326a8c1fc522db584e86cdfccd51f..0000000000000000000000000000000000000000
--- a/SPI/incremental_db/compiled_partitions/SPI_test.root_partition.cmp.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/SPI/incremental_db/compiled_partitions/SPI_test.root_partition.cmp.rcfdb b/SPI/incremental_db/compiled_partitions/SPI_test.root_partition.cmp.rcfdb
deleted file mode 100644
index ce6d691506364c808a7d16cd0bb3b907fb2d4748..0000000000000000000000000000000000000000
Binary files a/SPI/incremental_db/compiled_partitions/SPI_test.root_partition.cmp.rcfdb and /dev/null differ
diff --git a/SPI/incremental_db/compiled_partitions/SPI_test.root_partition.map.cdb b/SPI/incremental_db/compiled_partitions/SPI_test.root_partition.map.cdb
deleted file mode 100644
index be12f84a474aa56ac8233f24062f9b06d1341711..0000000000000000000000000000000000000000
Binary files a/SPI/incremental_db/compiled_partitions/SPI_test.root_partition.map.cdb and /dev/null differ
diff --git a/SPI/incremental_db/compiled_partitions/SPI_test.root_partition.map.dpi b/SPI/incremental_db/compiled_partitions/SPI_test.root_partition.map.dpi
deleted file mode 100644
index 603a775ab61cd4c7b081678f972dad1e4f2aebc4..0000000000000000000000000000000000000000
Binary files a/SPI/incremental_db/compiled_partitions/SPI_test.root_partition.map.dpi and /dev/null differ
diff --git a/SPI/incremental_db/compiled_partitions/SPI_test.root_partition.map.hbdb.cdb b/SPI/incremental_db/compiled_partitions/SPI_test.root_partition.map.hbdb.cdb
deleted file mode 100644
index a5571e9a5e2ca6eb6e6f370664d4afbae1e99f8e..0000000000000000000000000000000000000000
Binary files a/SPI/incremental_db/compiled_partitions/SPI_test.root_partition.map.hbdb.cdb and /dev/null differ
diff --git a/SPI/incremental_db/compiled_partitions/SPI_test.root_partition.map.hbdb.hb_info b/SPI/incremental_db/compiled_partitions/SPI_test.root_partition.map.hbdb.hb_info
deleted file mode 100644
index 8210c55998f9226aeba57897397a9e541102c45e..0000000000000000000000000000000000000000
Binary files a/SPI/incremental_db/compiled_partitions/SPI_test.root_partition.map.hbdb.hb_info and /dev/null differ
diff --git a/SPI/incremental_db/compiled_partitions/SPI_test.root_partition.map.hbdb.hdb b/SPI/incremental_db/compiled_partitions/SPI_test.root_partition.map.hbdb.hdb
deleted file mode 100644
index 5055f309652eeb1d68d6a686a39b7cb8b311ad1a..0000000000000000000000000000000000000000
Binary files a/SPI/incremental_db/compiled_partitions/SPI_test.root_partition.map.hbdb.hdb and /dev/null differ
diff --git a/SPI/incremental_db/compiled_partitions/SPI_test.root_partition.map.hbdb.sig b/SPI/incremental_db/compiled_partitions/SPI_test.root_partition.map.hbdb.sig
deleted file mode 100644
index 6c0af65a11537a2c90318684dc37b453e575c4c8..0000000000000000000000000000000000000000
--- a/SPI/incremental_db/compiled_partitions/SPI_test.root_partition.map.hbdb.sig
+++ /dev/null
@@ -1 +0,0 @@
-c5eb7f6cdd530884c3b884e0a3668ea4
\ No newline at end of file
diff --git a/SPI/incremental_db/compiled_partitions/SPI_test.root_partition.map.hdb b/SPI/incremental_db/compiled_partitions/SPI_test.root_partition.map.hdb
deleted file mode 100644
index c9ee0ba43f7482e7e3762d301549c03d6b54a9dd..0000000000000000000000000000000000000000
Binary files a/SPI/incremental_db/compiled_partitions/SPI_test.root_partition.map.hdb and /dev/null differ
diff --git a/SPI/incremental_db/compiled_partitions/SPI_test.root_partition.map.kpt b/SPI/incremental_db/compiled_partitions/SPI_test.root_partition.map.kpt
deleted file mode 100644
index fe5dbd49c83ad08d0d338d12fd17b22a30e60f64..0000000000000000000000000000000000000000
Binary files a/SPI/incremental_db/compiled_partitions/SPI_test.root_partition.map.kpt and /dev/null differ
diff --git a/SPI/incremental_db/compiled_partitions/SPI_test.rrp.hdb b/SPI/incremental_db/compiled_partitions/SPI_test.rrp.hdb
deleted file mode 100644
index dda12fea99d17fc0074772f58af513037e0d904c..0000000000000000000000000000000000000000
Binary files a/SPI/incremental_db/compiled_partitions/SPI_test.rrp.hdb and /dev/null differ
diff --git a/SPI/output_files/SPI_test.asm.rpt b/SPI/output_files/SPI_test.asm.rpt
deleted file mode 100644
index 9aed80ebc510fbc7e4949df9fa208a216e6dcffc..0000000000000000000000000000000000000000
--- a/SPI/output_files/SPI_test.asm.rpt
+++ /dev/null
@@ -1,91 +0,0 @@
-Assembler report for SPI_test
-Wed Nov 16 16:51:43 2022
-Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Assembler Summary
- 3. Assembler Settings
- 4. Assembler Generated Files
- 5. Assembler Device Options: C:/Users/damie/Documents/Minibot/SPI/output_files/SPI_test.sof
- 6. Assembler Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2018 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details.
-
-
-
-+---------------------------------------------------------------+
-; Assembler Summary ;
-+-----------------------+---------------------------------------+
-; Assembler Status ; Successful - Wed Nov 16 16:51:43 2022 ;
-; Revision Name ; SPI_test ;
-; Top-level Entity Name ; MyDE0_Nano ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE22F17C6 ;
-+-----------------------+---------------------------------------+
-
-
-+----------------------------------+
-; Assembler Settings ;
-+--------+---------+---------------+
-; Option ; Setting ; Default Value ;
-+--------+---------+---------------+
-
-
-+----------------------------------------------------------------+
-; Assembler Generated Files ;
-+----------------------------------------------------------------+
-; File Name ;
-+----------------------------------------------------------------+
-; C:/Users/damie/Documents/Minibot/SPI/output_files/SPI_test.sof ;
-+----------------------------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------+
-; Assembler Device Options: C:/Users/damie/Documents/Minibot/SPI/output_files/SPI_test.sof ;
-+----------------+-------------------------------------------------------------------------+
-; Option ; Setting ;
-+----------------+-------------------------------------------------------------------------+
-; JTAG usercode ; 0x0013DBF0 ;
-; Checksum ; 0x0013DBF0 ;
-+----------------+-------------------------------------------------------------------------+
-
-
-+--------------------+
-; Assembler Messages ;
-+--------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Assembler
- Info: Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
- Info: Processing started: Wed Nov 16 16:51:42 2022
-Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off SPI_test -c SPI_test
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (115031): Writing out detailed assembly data for power analysis
-Info (115030): Assembler is generating device programming files
-Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 4674 megabytes
- Info: Processing ended: Wed Nov 16 16:51:43 2022
- Info: Elapsed time: 00:00:01
- Info: Total CPU time (on all processors): 00:00:01
-
-
diff --git a/SPI/output_files/SPI_test.cdf b/SPI/output_files/SPI_test.cdf
deleted file mode 100644
index 24a800ce2fde3ed52e6fbf7b2305771735d255b3..0000000000000000000000000000000000000000
--- a/SPI/output_files/SPI_test.cdf
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition */
-JedecChain;
- FileRevision(JESD32A);
- DefaultMfr(6E);
-
- P ActionCode(Cfg)
- Device PartName(EP4CE22) Path("C:/Users/damie/Documents/Minibot/SPI/output_files/") File("output_file.jic") MfrSpec(OpMask(1) SEC_Device(EPCS64) Child_OpMask(1 7));
-
-ChainEnd;
-
-AlteraBegin;
- ChainType(JTAG);
-AlteraEnd;
diff --git a/SPI/output_files/SPI_test.done b/SPI/output_files/SPI_test.done
deleted file mode 100644
index 20bb6c7e410d1fde0b90870b89332d91fc0d88b7..0000000000000000000000000000000000000000
--- a/SPI/output_files/SPI_test.done
+++ /dev/null
@@ -1 +0,0 @@
-Wed Nov 16 16:51:49 2022
diff --git a/SPI/output_files/SPI_test.eda.rpt b/SPI/output_files/SPI_test.eda.rpt
deleted file mode 100644
index 63588a6fe41a79f8b07bc46f4d9e6273bb2e202b..0000000000000000000000000000000000000000
--- a/SPI/output_files/SPI_test.eda.rpt
+++ /dev/null
@@ -1,108 +0,0 @@
-EDA Netlist Writer report for SPI_test
-Wed Nov 16 16:51:48 2022
-Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. EDA Netlist Writer Summary
- 3. Simulation Settings
- 4. Simulation Generated Files
- 5. EDA Netlist Writer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2018 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details.
-
-
-
-+-------------------------------------------------------------------+
-; EDA Netlist Writer Summary ;
-+---------------------------+---------------------------------------+
-; EDA Netlist Writer Status ; Successful - Wed Nov 16 16:51:48 2022 ;
-; Revision Name ; SPI_test ;
-; Top-level Entity Name ; MyDE0_Nano ;
-; Family ; Cyclone IV E ;
-; Simulation Files Creation ; Successful ;
-+---------------------------+---------------------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------+
-; Simulation Settings ;
-+---------------------------------------------------------------------------------------------------+---------------------------------+
-; Option ; Setting ;
-+---------------------------------------------------------------------------------------------------+---------------------------------+
-; Tool Name ; ModelSim-Altera (SystemVerilog) ;
-; Generate functional simulation netlist ; Off ;
-; Time scale ; 1 ps ;
-; Truncate long hierarchy paths ; Off ;
-; Map illegal HDL characters ; Off ;
-; Flatten buses into individual nodes ; Off ;
-; Maintain hierarchy ; Off ;
-; Bring out device-wide set/reset signals as ports ; Off ;
-; Enable glitch filtering ; Off ;
-; Do not write top level VHDL entity ; Off ;
-; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
-; Architecture name in VHDL output netlist ; structure ;
-; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
-; Generate third-party EDA tool command script for gate-level simulation ; Off ;
-+---------------------------------------------------------------------------------------------------+---------------------------------+
-
-
-+--------------------------------------------------------------------------------------------+
-; Simulation Generated Files ;
-+--------------------------------------------------------------------------------------------+
-; Generated Files ;
-+--------------------------------------------------------------------------------------------+
-; C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/SPI_test_6_1200mv_85c_slow.svo ;
-; C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/SPI_test_6_1200mv_0c_slow.svo ;
-; C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/SPI_test_min_1200mv_0c_fast.svo ;
-; C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/SPI_test.svo ;
-; C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/SPI_test_6_1200mv_85c_v_slow.sdo ;
-; C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/SPI_test_6_1200mv_0c_v_slow.sdo ;
-; C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/SPI_test_min_1200mv_0c_v_fast.sdo ;
-; C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/SPI_test_v.sdo ;
-+--------------------------------------------------------------------------------------------+
-
-
-+-----------------------------+
-; EDA Netlist Writer Messages ;
-+-----------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime EDA Netlist Writer
- Info: Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
- Info: Processing started: Wed Nov 16 16:51:47 2022
-Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off SPI_test -c SPI_test
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (204019): Generated file SPI_test_6_1200mv_85c_slow.svo in folder "C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/" for EDA simulation tool
-Info (204019): Generated file SPI_test_6_1200mv_0c_slow.svo in folder "C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/" for EDA simulation tool
-Info (204019): Generated file SPI_test_min_1200mv_0c_fast.svo in folder "C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/" for EDA simulation tool
-Info (204019): Generated file SPI_test.svo in folder "C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/" for EDA simulation tool
-Info (204019): Generated file SPI_test_6_1200mv_85c_v_slow.sdo in folder "C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/" for EDA simulation tool
-Info (204019): Generated file SPI_test_6_1200mv_0c_v_slow.sdo in folder "C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/" for EDA simulation tool
-Info (204019): Generated file SPI_test_min_1200mv_0c_v_fast.sdo in folder "C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/" for EDA simulation tool
-Info (204019): Generated file SPI_test_v.sdo in folder "C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/" for EDA simulation tool
-Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 4635 megabytes
- Info: Processing ended: Wed Nov 16 16:51:48 2022
- Info: Elapsed time: 00:00:01
- Info: Total CPU time (on all processors): 00:00:01
-
-
diff --git a/SPI/output_files/SPI_test.fit.rpt b/SPI/output_files/SPI_test.fit.rpt
deleted file mode 100644
index f6d07b0404d214f0c7cc3431c37c6eb0213e2bb2..0000000000000000000000000000000000000000
--- a/SPI/output_files/SPI_test.fit.rpt
+++ /dev/null
@@ -1,1686 +0,0 @@
-Fitter report for SPI_test
-Wed Nov 16 16:51:40 2022
-Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Fitter Summary
- 3. Fitter Settings
- 4. Parallel Compilation
- 5. Incremental Compilation Preservation Summary
- 6. Incremental Compilation Partition Settings
- 7. Incremental Compilation Placement Preservation
- 8. Pin-Out File
- 9. Fitter Resource Usage Summary
- 10. Fitter Partition Statistics
- 11. Input Pins
- 12. Output Pins
- 13. Bidir Pins
- 14. Dual Purpose and Dedicated Pins
- 15. I/O Bank Usage
- 16. All Package Pins
- 17. I/O Assignment Warnings
- 18. Fitter Resource Utilization by Entity
- 19. Delay Chain Summary
- 20. Pad To Core Delay Chain Fanout
- 21. Control Signals
- 22. Global & Other Fast Signals
- 23. Routing Usage Summary
- 24. LAB Logic Elements
- 25. LAB-wide Signals
- 26. LAB Signals Sourced
- 27. LAB Signals Sourced Out
- 28. LAB Distinct Inputs
- 29. I/O Rules Summary
- 30. I/O Rules Details
- 31. I/O Rules Matrix
- 32. Fitter Device Options
- 33. Operating Settings and Conditions
- 34. Fitter Messages
- 35. Fitter Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2018 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details.
-
-
-
-+----------------------------------------------------------------------------------+
-; Fitter Summary ;
-+------------------------------------+---------------------------------------------+
-; Fitter Status ; Successful - Wed Nov 16 16:51:40 2022 ;
-; Quartus Prime Version ; 18.1.0 Build 625 09/12/2018 SJ Lite Edition ;
-; Revision Name ; SPI_test ;
-; Top-level Entity Name ; MyDE0_Nano ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE22F17C6 ;
-; Timing Models ; Final ;
-; Total logic elements ; 40 / 22,320 ( < 1 % ) ;
-; Total combinational functions ; 39 / 22,320 ( < 1 % ) ;
-; Dedicated logic registers ; 38 / 22,320 ( < 1 % ) ;
-; Total registers ; 38 ;
-; Total pins ; 99 / 154 ( 64 % ) ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 / 608,256 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ;
-; Total PLLs ; 0 / 4 ( 0 % ) ;
-+------------------------------------+---------------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Settings ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Option ; Setting ; Default Value ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Device ; EP4CE22F17C6 ; ;
-; Nominal Core Supply Voltage ; 1.2V ; ;
-; Minimum Core Junction Temperature ; 0 ; ;
-; Maximum Core Junction Temperature ; 85 ; ;
-; Fit Attempts to Skip ; 0 ; 0.0 ;
-; Use smart compilation ; Off ; Off ;
-; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
-; Enable compact report table ; Off ; Off ;
-; Auto Merge PLLs ; On ; On ;
-; Router Timing Optimization Level ; Normal ; Normal ;
-; Perform Clocking Topology Analysis During Routing ; Off ; Off ;
-; Placement Effort Multiplier ; 1.0 ; 1.0 ;
-; Router Effort Multiplier ; 1.0 ; 1.0 ;
-; Optimize Hold Timing ; All Paths ; All Paths ;
-; Optimize Multi-Corner Timing ; On ; On ;
-; Power Optimization During Fitting ; Normal compilation ; Normal compilation ;
-; SSN Optimization ; Off ; Off ;
-; Optimize Timing ; Normal compilation ; Normal compilation ;
-; Optimize Timing for ECOs ; Off ; Off ;
-; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ;
-; Optimize IOC Register Placement for Timing ; Normal ; Normal ;
-; Limit to One Fitting Attempt ; Off ; Off ;
-; Final Placement Optimizations ; Automatically ; Automatically ;
-; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
-; Fitter Initial Placement Seed ; 1 ; 1 ;
-; Periphery to Core Placement and Routing Optimization ; Off ; Off ;
-; PCI I/O ; Off ; Off ;
-; Weak Pull-Up Resistor ; Off ; Off ;
-; Enable Bus-Hold Circuitry ; Off ; Off ;
-; Auto Packed Registers ; Auto ; Auto ;
-; Auto Delay Chains ; On ; On ;
-; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ;
-; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ;
-; Treat Bidirectional Pin as Output Pin ; Off ; Off ;
-; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;
-; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
-; Perform Register Duplication for Performance ; Off ; Off ;
-; Perform Logic to Memory Mapping for Fitting ; Off ; Off ;
-; Perform Register Retiming for Performance ; Off ; Off ;
-; Perform Asynchronous Signal Pipelining ; Off ; Off ;
-; Fitter Effort ; Auto Fit ; Auto Fit ;
-; Physical Synthesis Effort Level ; Normal ; Normal ;
-; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
-; Auto Register Duplication ; Auto ; Auto ;
-; Auto Global Clock ; On ; On ;
-; Auto Global Register Control Signals ; On ; On ;
-; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
-; Synchronizer Identification ; Auto ; Auto ;
-; Enable Beneficial Skew Optimization ; On ; On ;
-; Optimize Design for Metastability ; On ; On ;
-; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
-; Enable input tri-state on active configuration pins in user mode ; Off ; Off ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.01 ;
-; Maximum used ; 4 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processors 2-4 ; 0.2% ;
-+----------------------------+-------------+
-
-
-+--------------------------------------------------------------------------------------------------+
-; Incremental Compilation Preservation Summary ;
-+---------------------+--------------------+----------------------------+--------------------------+
-; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
-+---------------------+--------------------+----------------------------+--------------------------+
-; Placement (by node) ; ; ; ;
-; -- Requested ; 0.00 % ( 0 / 368 ) ; 0.00 % ( 0 / 368 ) ; 0.00 % ( 0 / 368 ) ;
-; -- Achieved ; 0.00 % ( 0 / 368 ) ; 0.00 % ( 0 / 368 ) ; 0.00 % ( 0 / 368 ) ;
-; ; ; ; ;
-; Routing (by net) ; ; ; ;
-; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
-; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
-+---------------------+--------------------+----------------------------+--------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Partition Settings ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;
-; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Placement Preservation ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Top ; 0.00 % ( 0 / 358 ) ; N/A ; Source File ; N/A ; ;
-; hard_block:auto_generated_inst ; 0.00 % ( 0 / 10 ) ; N/A ; Source File ; N/A ; ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-
-
-+--------------+
-; Pin-Out File ;
-+--------------+
-The pin-out file can be found in C:/Users/damie/Documents/Minibot/SPI/output_files/SPI_test.pin.
-
-
-+---------------------------------------------------------------------+
-; Fitter Resource Usage Summary ;
-+---------------------------------------------+-----------------------+
-; Resource ; Usage ;
-+---------------------------------------------+-----------------------+
-; Total logic elements ; 40 / 22,320 ( < 1 % ) ;
-; -- Combinational with no register ; 2 ;
-; -- Register only ; 1 ;
-; -- Combinational with a register ; 37 ;
-; ; ;
-; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 3 ;
-; -- 3 input functions ; 32 ;
-; -- <=2 input functions ; 4 ;
-; -- Register only ; 1 ;
-; ; ;
-; Logic elements by mode ; ;
-; -- normal mode ; 36 ;
-; -- arithmetic mode ; 3 ;
-; ; ;
-; Total registers* ; 38 / 23,018 ( < 1 % ) ;
-; -- Dedicated logic registers ; 38 / 22,320 ( < 1 % ) ;
-; -- I/O registers ; 0 / 698 ( 0 % ) ;
-; ; ;
-; Total LABs: partially or completely used ; 3 / 1,395 ( < 1 % ) ;
-; Virtual pins ; 0 ;
-; I/O pins ; 99 / 154 ( 64 % ) ;
-; -- Clock pins ; 2 / 7 ( 29 % ) ;
-; -- Dedicated input pins ; 0 / 9 ( 0 % ) ;
-; ; ;
-; M9Ks ; 0 / 66 ( 0 % ) ;
-; Total block memory bits ; 0 / 608,256 ( 0 % ) ;
-; Total block memory implementation bits ; 0 / 608,256 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ;
-; PLLs ; 0 / 4 ( 0 % ) ;
-; Global signals ; 1 ;
-; -- Global clocks ; 1 / 20 ( 5 % ) ;
-; JTAGs ; 0 / 1 ( 0 % ) ;
-; CRC blocks ; 0 / 1 ( 0 % ) ;
-; ASMI blocks ; 0 / 1 ( 0 % ) ;
-; Oscillator blocks ; 0 / 1 ( 0 % ) ;
-; Impedance control blocks ; 0 / 4 ( 0 % ) ;
-; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.0% ;
-; Peak interconnect usage (total/H/V) ; 0.1% / 0.1% / 0.1% ;
-; Maximum fan-out ; 38 ;
-; Highest non-global fan-out ; 33 ;
-; Total fan-out ; 378 ;
-; Average fan-out ; 1.03 ;
-+---------------------------------------------+-----------------------+
-* Register count does not include registers inside RAM blocks or DSP blocks.
-
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Fitter Partition Statistics ;
-+---------------------------------------------+----------------------+--------------------------------+
-; Statistic ; Top ; hard_block:auto_generated_inst ;
-+---------------------------------------------+----------------------+--------------------------------+
-; Difficulty Clustering Region ; Low ; Low ;
-; ; ; ;
-; Total logic elements ; 40 / 22320 ( < 1 % ) ; 0 / 22320 ( 0 % ) ;
-; -- Combinational with no register ; 2 ; 0 ;
-; -- Register only ; 1 ; 0 ;
-; -- Combinational with a register ; 37 ; 0 ;
-; ; ; ;
-; Logic element usage by number of LUT inputs ; ; ;
-; -- 4 input functions ; 3 ; 0 ;
-; -- 3 input functions ; 32 ; 0 ;
-; -- <=2 input functions ; 4 ; 0 ;
-; -- Register only ; 1 ; 0 ;
-; ; ; ;
-; Logic elements by mode ; ; ;
-; -- normal mode ; 36 ; 0 ;
-; -- arithmetic mode ; 3 ; 0 ;
-; ; ; ;
-; Total registers ; 38 ; 0 ;
-; -- Dedicated logic registers ; 38 / 22320 ( < 1 % ) ; 0 / 22320 ( 0 % ) ;
-; -- I/O registers ; 0 ; 0 ;
-; ; ; ;
-; Total LABs: partially or completely used ; 3 / 1395 ( < 1 % ) ; 0 / 1395 ( 0 % ) ;
-; ; ; ;
-; Virtual pins ; 0 ; 0 ;
-; I/O pins ; 99 ; 0 ;
-; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ; 0 / 132 ( 0 % ) ;
-; Total memory bits ; 0 ; 0 ;
-; Total RAM block bits ; 0 ; 0 ;
-; Clock control block ; 1 / 24 ( 4 % ) ; 0 / 24 ( 0 % ) ;
-; ; ; ;
-; Connections ; ; ;
-; -- Input Connections ; 81 ; 0 ;
-; -- Registered Input Connections ; 0 ; 0 ;
-; -- Output Connections ; 81 ; 0 ;
-; -- Registered Output Connections ; 0 ; 0 ;
-; ; ; ;
-; Internal Connections ; ; ;
-; -- Total Connections ; 373 ; 5 ;
-; -- Registered Connections ; 79 ; 0 ;
-; ; ; ;
-; External Connections ; ; ;
-; -- Top ; 162 ; 0 ;
-; -- hard_block:auto_generated_inst ; 0 ; 0 ;
-; ; ; ;
-; Partition Interface ; ; ;
-; -- Input Ports ; 10 ; 0 ;
-; -- Output Ports ; 8 ; 0 ;
-; -- Bidir Ports ; 81 ; 0 ;
-; ; ; ;
-; Registered Ports ; ; ;
-; -- Registered Input Ports ; 0 ; 0 ;
-; -- Registered Output Ports ; 0 ; 0 ;
-; ; ; ;
-; Port Connectivity ; ; ;
-; -- Input Ports driven by GND ; 0 ; 0 ;
-; -- Output Ports driven by GND ; 0 ; 0 ;
-; -- Input Ports driven by VCC ; 0 ; 0 ;
-; -- Output Ports driven by VCC ; 0 ; 0 ;
-; -- Input Ports with no Source ; 0 ; 0 ;
-; -- Output Ports with no Source ; 0 ; 0 ;
-; -- Input Ports with no Fanout ; 0 ; 0 ;
-; -- Output Ports with no Fanout ; 0 ; 0 ;
-+---------------------------------------------+----------------------+--------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Input Pins ;
-+-----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ;
-+-----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-; CLOCK_50 ; R7 ; 3 ; 16 ; 0 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; GPIO_0_PI_IN[0] ; E6 ; 8 ; 14 ; 34 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ;
-; GPIO_0_PI_IN[1] ; C14 ; 7 ; 51 ; 34 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ;
-; GPIO_1_IN[0] ; A12 ; 7 ; 43 ; 34 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ;
-; GPIO_1_IN[1] ; T10 ; 4 ; 34 ; 0 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ;
-; GPIO_2_IN[0] ; E16 ; 6 ; 53 ; 17 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ;
-; GPIO_2_IN[1] ; E15 ; 6 ; 53 ; 17 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ;
-; GPIO_2_IN[2] ; D6 ; 8 ; 9 ; 34 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ;
-; KEY[0] ; J15 ; 5 ; 53 ; 14 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-; KEY[1] ; E1 ; 1 ; 0 ; 16 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
-+-----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Output Pins ;
-+--------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
-+--------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-; LED[0] ; A15 ; 7 ; 38 ; 34 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LED[1] ; A13 ; 7 ; 49 ; 34 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LED[2] ; B13 ; 7 ; 49 ; 34 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LED[3] ; A11 ; 7 ; 40 ; 34 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LED[4] ; D1 ; 1 ; 0 ; 25 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LED[5] ; F3 ; 1 ; 0 ; 26 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LED[6] ; B1 ; 1 ; 0 ; 28 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-; LED[7] ; L3 ; 2 ; 0 ; 10 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
-+--------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Bidir Pins ;
-+---------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+----------------------+----------------------+---------------------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Output Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Location assigned by ; Output Enable Source ; Output Enable Group ;
-+---------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+----------------------+----------------------+---------------------+
-; GPIO_0_PI[0] ; A10 ; 7 ; 34 ; 34 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_0_PI[10] ; E7 ; 8 ; 16 ; 34 ; 14 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_0_PI[11] ; A6 ; 8 ; 16 ; 34 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; GPIO_0_PI[10]~input ;
-; GPIO_0_PI[12] ; P1 ; 2 ; 0 ; 4 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_0_PI[13] ; R16 ; 5 ; 53 ; 8 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_0_PI[14] ; C3 ; 8 ; 1 ; 34 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_0_PI[15] ; B10 ; 7 ; 34 ; 34 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_0_PI[16] ; F9 ; 7 ; 34 ; 34 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_0_PI[17] ; B6 ; 8 ; 16 ; 34 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ;
-; GPIO_0_PI[18] ; R3 ; 3 ; 1 ; 0 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_0_PI[19] ; T12 ; 4 ; 36 ; 0 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_0_PI[1] ; P2 ; 2 ; 0 ; 4 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_0_PI[20] ; J1 ; 2 ; 0 ; 15 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_0_PI[21] ; A14 ; 7 ; 47 ; 34 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_0_PI[22] ; R6 ; 3 ; 14 ; 0 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_0_PI[23] ; A7 ; 8 ; 20 ; 34 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_0_PI[24] ; B14 ; 7 ; 45 ; 34 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_0_PI[25] ; R13 ; 4 ; 40 ; 0 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_0_PI[26] ; L8 ; 3 ; 18 ; 0 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_0_PI[27] ; E10 ; 7 ; 45 ; 34 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ;
-; GPIO_0_PI[28] ; C11 ; 7 ; 38 ; 34 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ;
-; GPIO_0_PI[29] ; B11 ; 7 ; 40 ; 34 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ;
-; GPIO_0_PI[2] ; R1 ; 2 ; 0 ; 5 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_0_PI[30] ; B7 ; 8 ; 18 ; 34 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_0_PI[31] ; D11 ; 7 ; 51 ; 34 ; 14 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ;
-; GPIO_0_PI[32] ; D8 ; 8 ; 23 ; 34 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_0_PI[33] ; B16 ; 6 ; 53 ; 22 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_0_PI[3] ; C6 ; 8 ; 18 ; 34 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_0_PI[4] ; T5 ; 3 ; 14 ; 0 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_0_PI[5] ; A5 ; 8 ; 14 ; 34 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ;
-; GPIO_0_PI[6] ; P15 ; 5 ; 53 ; 6 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_0_PI[7] ; R5 ; 3 ; 14 ; 0 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_0_PI[8] ; G2 ; 1 ; 0 ; 23 ; 14 ; 38 ; 0 ; yes ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_0_PI[9] ; D5 ; 8 ; 5 ; 34 ; 14 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; User ; 0 pF ; - ;
-; GPIO_1[0] ; T6 ; 3 ; 14 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_1[10] ; L1 ; 2 ; 0 ; 11 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_1[11] ; E11 ; 7 ; 45 ; 34 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_1[12] ; D15 ; 6 ; 53 ; 26 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_1[13] ; T13 ; 4 ; 40 ; 0 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_1[14] ; K16 ; 5 ; 53 ; 12 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_1[15] ; C15 ; 6 ; 53 ; 30 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_1[16] ; P8 ; 3 ; 25 ; 0 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_1[17] ; R10 ; 4 ; 34 ; 0 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_1[18] ; N1 ; 2 ; 0 ; 7 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_1[19] ; C16 ; 6 ; 53 ; 30 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_1[1] ; N3 ; 3 ; 1 ; 0 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_1[20] ; C2 ; 1 ; 0 ; 27 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_1[21] ; N12 ; 4 ; 47 ; 0 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_1[22] ; B5 ; 8 ; 11 ; 34 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_1[23] ; M8 ; 3 ; 20 ; 0 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_1[24] ; N6 ; 3 ; 5 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_1[25] ; F13 ; 6 ; 53 ; 21 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_1[26] ; P3 ; 3 ; 1 ; 0 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_1[27] ; M6 ; 3 ; 7 ; 0 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_1[28] ; G1 ; 1 ; 0 ; 23 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_1[29] ; J16 ; 5 ; 53 ; 14 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_1[2] ; G16 ; 6 ; 53 ; 20 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_1[30] ; T14 ; 4 ; 45 ; 0 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_1[31] ; R14 ; 4 ; 49 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_1[32] ; C9 ; 7 ; 31 ; 34 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_1[33] ; L4 ; 2 ; 0 ; 6 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_1[3] ; F1 ; 1 ; 0 ; 23 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_1[4] ; B4 ; 8 ; 7 ; 34 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_1[5] ; L15 ; 5 ; 53 ; 11 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_1[6] ; D14 ; 7 ; 51 ; 34 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_1[7] ; N5 ; 3 ; 5 ; 0 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_1[8] ; F15 ; 6 ; 53 ; 22 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_1[9] ; R11 ; 4 ; 34 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_2[0] ; R4 ; 3 ; 5 ; 0 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_2[10] ; B12 ; 7 ; 43 ; 34 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_2[11] ; C8 ; 8 ; 23 ; 34 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_2[12] ; E8 ; 8 ; 20 ; 34 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_2[1] ; D12 ; 7 ; 51 ; 34 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_2[2] ; F2 ; 1 ; 0 ; 24 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_2[3] ; G5 ; 1 ; 0 ; 24 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_2[4] ; T4 ; 3 ; 5 ; 0 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_2[5] ; J2 ; 2 ; 0 ; 15 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_2[6] ; B3 ; 8 ; 3 ; 34 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_2[7] ; D3 ; 8 ; 1 ; 34 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_2[8] ; M7 ; 3 ; 11 ; 0 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-; GPIO_2[9] ; T2 ; 3 ; 3 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; Fitter ; 0 pF ; - ;
-+---------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+----------------------+----------------------+---------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------+
-; Dual Purpose and Dedicated Pins ;
-+----------+------------------------------------------+--------------------------+-------------------------+---------------------------+
-; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ;
-+----------+------------------------------------------+--------------------------+-------------------------+---------------------------+
-; C1 ; DIFFIO_L3n, DATA1, ASDO ; As input tri-stated ; ~ALTERA_ASDO_DATA1~ ; Dual Purpose Pin ;
-; D2 ; DIFFIO_L4p, FLASH_nCE, nCSO ; As input tri-stated ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin ;
-; F4 ; nSTATUS ; - ; - ; Dedicated Programming Pin ;
-; H1 ; DCLK ; As output driving ground ; ~ALTERA_DCLK~ ; Dual Purpose Pin ;
-; H2 ; DATA0 ; As input tri-stated ; ~ALTERA_DATA0~ ; Dual Purpose Pin ;
-; H5 ; nCONFIG ; - ; - ; Dedicated Programming Pin ;
-; J3 ; nCE ; - ; - ; Dedicated Programming Pin ;
-; J16 ; DIFFIO_R9n, DEV_OE ; Use as regular IO ; GPIO_1[29] ; Dual Purpose Pin ;
-; J15 ; DIFFIO_R9p, DEV_CLRn ; Use as regular IO ; KEY[0] ; Dual Purpose Pin ;
-; H14 ; CONF_DONE ; - ; - ; Dedicated Programming Pin ;
-; H13 ; MSEL0 ; - ; - ; Dedicated Programming Pin ;
-; H12 ; MSEL1 ; - ; - ; Dedicated Programming Pin ;
-; G12 ; MSEL2 ; - ; - ; Dedicated Programming Pin ;
-; G12 ; MSEL3 ; - ; - ; Dedicated Programming Pin ;
-; G16 ; DIFFIO_R5n, INIT_DONE ; Use as regular IO ; GPIO_1[2] ; Dual Purpose Pin ;
-; F16 ; DIFFIO_R4n, nCEO ; Use as programming pin ; ~ALTERA_nCEO~ ; Dual Purpose Pin ;
-; F15 ; DIFFIO_R4p, CLKUSR ; Use as regular IO ; GPIO_1[8] ; Dual Purpose Pin ;
-; D15 ; PADD23 ; Use as regular IO ; GPIO_1[12] ; Dual Purpose Pin ;
-; C16 ; DIFFIO_R1n, PADD20, DQS2R/CQ3R,CDPCLK5 ; Use as regular IO ; GPIO_1[19] ; Dual Purpose Pin ;
-; B11 ; DIFFIO_T20p, PADD0 ; Use as regular IO ; GPIO_0_PI[29] ; Dual Purpose Pin ;
-; A15 ; DIFFIO_T19n, PADD1 ; Use as regular IO ; LED[0] ; Dual Purpose Pin ;
-; F9 ; DIFFIO_T17p, PADD4, DQS2T/CQ3T,DPCLK8 ; Use as regular IO ; GPIO_0_PI[16] ; Dual Purpose Pin ;
-; A10 ; DIFFIO_T16n, PADD5 ; Use as regular IO ; GPIO_0_PI[0] ; Dual Purpose Pin ;
-; B10 ; DIFFIO_T16p, PADD6 ; Use as regular IO ; GPIO_0_PI[15] ; Dual Purpose Pin ;
-; C9 ; DIFFIO_T15n, PADD7 ; Use as regular IO ; GPIO_1[32] ; Dual Purpose Pin ;
-; C8 ; DIFFIO_T11p, PADD17, DQS5T/CQ5T#,DPCLK10 ; Use as regular IO ; GPIO_2[11] ; Dual Purpose Pin ;
-; E8 ; DIFFIO_T10n, DATA2 ; Use as regular IO ; GPIO_2[12] ; Dual Purpose Pin ;
-; A7 ; DIFFIO_T9n, PADD18 ; Use as regular IO ; GPIO_0_PI[23] ; Dual Purpose Pin ;
-; B7 ; DIFFIO_T9p, DATA4 ; Use as regular IO ; GPIO_0_PI[30] ; Dual Purpose Pin ;
-; A6 ; DIFFIO_T7n, DATA14, DQS3T/CQ3T#,DPCLK11 ; Use as regular IO ; GPIO_0_PI[11] ; Dual Purpose Pin ;
-; B6 ; DIFFIO_T7p, DATA13 ; Use as regular IO ; GPIO_0_PI[17] ; Dual Purpose Pin ;
-; E7 ; DATA5 ; Use as regular IO ; GPIO_0_PI[10] ; Dual Purpose Pin ;
-; E6 ; DIFFIO_T6p, DATA6 ; Use as regular IO ; GPIO_0_PI_IN[0] ; Dual Purpose Pin ;
-; A5 ; DIFFIO_T5n, DATA7 ; Use as regular IO ; GPIO_0_PI[5] ; Dual Purpose Pin ;
-; B5 ; DIFFIO_T5p, DATA8 ; Use as regular IO ; GPIO_1[22] ; Dual Purpose Pin ;
-; D6 ; DIFFIO_T4n, DATA9 ; Use as regular IO ; GPIO_2_IN[2] ; Dual Purpose Pin ;
-; B4 ; DIFFIO_T3p, DATA11 ; Use as regular IO ; GPIO_1[4] ; Dual Purpose Pin ;
-; B3 ; DATA12, DQS1T/CQ1T#,CDPCLK7 ; Use as regular IO ; GPIO_2[6] ; Dual Purpose Pin ;
-+----------+------------------------------------------+--------------------------+-------------------------+---------------------------+
-
-
-+-------------------------------------------------------------+
-; I/O Bank Usage ;
-+----------+-------------------+---------------+--------------+
-; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
-+----------+-------------------+---------------+--------------+
-; 1 ; 14 / 14 ( 100 % ) ; 2.5V ; -- ;
-; 2 ; 9 / 16 ( 56 % ) ; 2.5V ; -- ;
-; 3 ; 18 / 25 ( 72 % ) ; 2.5V ; -- ;
-; 4 ; 9 / 20 ( 45 % ) ; 2.5V ; -- ;
-; 5 ; 6 / 18 ( 33 % ) ; 2.5V ; -- ;
-; 6 ; 10 / 13 ( 77 % ) ; 2.5V ; -- ;
-; 7 ; 20 / 24 ( 83 % ) ; 2.5V ; -- ;
-; 8 ; 18 / 24 ( 75 % ) ; 2.5V ; -- ;
-+----------+-------------------+---------------+--------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; All Package Pins ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; A1 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A2 ; 238 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A3 ; 239 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A4 ; 236 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A5 ; 232 ; 8 ; GPIO_0_PI[5] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; A6 ; 225 ; 8 ; GPIO_0_PI[11] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; A7 ; 220 ; 8 ; GPIO_0_PI[23] ; bidir ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; A8 ; 211 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; A9 ; 209 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; A10 ; 198 ; 7 ; GPIO_0_PI[0] ; bidir ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; A11 ; 188 ; 7 ; LED[3] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; A12 ; 186 ; 7 ; GPIO_1_IN[0] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; A13 ; 179 ; 7 ; LED[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; A14 ; 181 ; 7 ; GPIO_0_PI[21] ; bidir ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; A15 ; 191 ; 7 ; LED[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; A16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; B1 ; 5 ; 1 ; LED[6] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B3 ; 242 ; 8 ; GPIO_2[6] ; bidir ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; B4 ; 237 ; 8 ; GPIO_1[4] ; bidir ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; B5 ; 233 ; 8 ; GPIO_1[22] ; bidir ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; B6 ; 226 ; 8 ; GPIO_0_PI[17] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; B7 ; 221 ; 8 ; GPIO_0_PI[30] ; bidir ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; B8 ; 212 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; B9 ; 210 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; B10 ; 199 ; 7 ; GPIO_0_PI[15] ; bidir ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; B11 ; 189 ; 7 ; GPIO_0_PI[29] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; B12 ; 187 ; 7 ; GPIO_2[10] ; bidir ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; B13 ; 180 ; 7 ; LED[2] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; B14 ; 182 ; 7 ; GPIO_0_PI[24] ; bidir ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; B15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B16 ; 164 ; 6 ; GPIO_0_PI[33] ; bidir ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; C1 ; 7 ; 1 ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; C2 ; 6 ; 1 ; GPIO_1[20] ; bidir ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; C3 ; 245 ; 8 ; GPIO_0_PI[14] ; bidir ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; C4 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; C5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; C6 ; 224 ; 8 ; GPIO_0_PI[3] ; bidir ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; C7 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; C8 ; 215 ; 8 ; GPIO_2[11] ; bidir ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; C9 ; 200 ; 7 ; GPIO_1[32] ; bidir ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; C10 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; C11 ; 190 ; 7 ; GPIO_0_PI[28] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; C12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; C13 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; C14 ; 175 ; 7 ; GPIO_0_PI_IN[1] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; C15 ; 174 ; 6 ; GPIO_1[15] ; bidir ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; C16 ; 173 ; 6 ; GPIO_1[19] ; bidir ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; D1 ; 10 ; 1 ; LED[4] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; D2 ; 9 ; 1 ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; D3 ; 246 ; 8 ; GPIO_2[7] ; bidir ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; D4 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; D5 ; 241 ; 8 ; GPIO_0_PI[9] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; D6 ; 234 ; 8 ; GPIO_2_IN[2] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; D7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; D8 ; 216 ; 8 ; GPIO_0_PI[32] ; bidir ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; D9 ; 201 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; D11 ; 177 ; 7 ; GPIO_0_PI[31] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; D12 ; 178 ; 7 ; GPIO_2[1] ; bidir ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; D13 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; D14 ; 176 ; 7 ; GPIO_1[6] ; bidir ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; D15 ; 170 ; 6 ; GPIO_1[12] ; bidir ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; D16 ; 169 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E1 ; 26 ; 1 ; KEY[1] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; E2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; E3 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; E5 ; ; ; GNDA3 ; gnd ; ; ; -- ; ; -- ; -- ;
-; E6 ; 231 ; 8 ; GPIO_0_PI_IN[0] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; E7 ; 227 ; 8 ; GPIO_0_PI[10] ; bidir ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; E8 ; 218 ; 8 ; GPIO_2[12] ; bidir ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; E9 ; 205 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E10 ; 184 ; 7 ; GPIO_0_PI[27] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; E11 ; 183 ; 7 ; GPIO_1[11] ; bidir ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; E12 ; ; ; GNDA2 ; gnd ; ; ; -- ; ; -- ; -- ;
-; E13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; E14 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E15 ; 151 ; 6 ; GPIO_2_IN[1] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; E16 ; 150 ; 6 ; GPIO_2_IN[0] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; F1 ; 14 ; 1 ; GPIO_1[3] ; bidir ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; F2 ; 13 ; 1 ; GPIO_2[2] ; bidir ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; F3 ; 8 ; 1 ; LED[5] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; F4 ; 11 ; 1 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
-; F5 ; ; -- ; VCCA3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; F6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F7 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; F8 ; 219 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F9 ; 197 ; 7 ; GPIO_0_PI[16] ; bidir ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; F10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; F12 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; F13 ; 161 ; 6 ; GPIO_1[25] ; bidir ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; F14 ; 167 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; F15 ; 163 ; 6 ; GPIO_1[8] ; bidir ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; F16 ; 162 ; 6 ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; G1 ; 16 ; 1 ; GPIO_1[28] ; bidir ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; G2 ; 15 ; 1 ; GPIO_0_PI[8] ; bidir ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; G3 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; G4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; G5 ; 12 ; 1 ; GPIO_2[3] ; bidir ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; G6 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; G7 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; G8 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; G9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; G10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; G11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; G12 ; 155 ; 6 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ;
-; G12 ; 156 ; 6 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ;
-; G13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; G14 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; G15 ; 160 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G16 ; 159 ; 6 ; GPIO_1[2] ; bidir ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; H1 ; 17 ; 1 ; ~ALTERA_DCLK~ ; output ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; H2 ; 18 ; 1 ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
-; H3 ; 21 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
-; H4 ; 20 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
-; H5 ; 19 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
-; H6 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; H7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; H12 ; 154 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
-; H13 ; 153 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
-; H14 ; 152 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
-; H15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J1 ; 30 ; 2 ; GPIO_0_PI[20] ; bidir ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; J2 ; 29 ; 2 ; GPIO_2[5] ; bidir ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; J3 ; 24 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
-; J4 ; 23 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
-; J5 ; 22 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
-; J6 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; J7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; J13 ; 146 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J14 ; 144 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J15 ; 143 ; 5 ; KEY[0] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; J16 ; 142 ; 5 ; GPIO_1[29] ; bidir ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; K1 ; 37 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K2 ; 36 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K3 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K5 ; 45 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K7 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K14 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K15 ; 141 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K16 ; 140 ; 5 ; GPIO_1[14] ; bidir ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; L1 ; 39 ; 2 ; GPIO_1[10] ; bidir ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; L2 ; 38 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L3 ; 40 ; 2 ; LED[7] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
-; L4 ; 46 ; 2 ; GPIO_1[33] ; bidir ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; L5 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; L6 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; L7 ; 75 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; L8 ; 79 ; 3 ; GPIO_0_PI[26] ; bidir ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; L9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L12 ; ; -- ; VCCA4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; L13 ; 136 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L14 ; 134 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; L15 ; 138 ; 5 ; GPIO_1[5] ; bidir ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; L16 ; 137 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M1 ; 28 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; M2 ; 27 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; M3 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; M4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M5 ; ; ; GNDA1 ; gnd ; ; ; -- ; ; -- ; -- ;
-; M6 ; 64 ; 3 ; GPIO_1[27] ; bidir ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; M7 ; 68 ; 3 ; GPIO_2[8] ; bidir ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; M8 ; 81 ; 3 ; GPIO_1[23] ; bidir ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; M9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M10 ; 111 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; M11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; M12 ; ; ; GNDA4 ; gnd ; ; ; -- ; ; -- ; -- ;
-; M13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M14 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; M15 ; 149 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; M16 ; 148 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; N1 ; 44 ; 2 ; GPIO_1[18] ; bidir ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; N2 ; 43 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N3 ; 52 ; 3 ; GPIO_1[1] ; bidir ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; N4 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N5 ; 62 ; 3 ; GPIO_1[7] ; bidir ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; N6 ; 63 ; 3 ; GPIO_1[24] ; bidir ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; N7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N8 ; 82 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; N9 ; 93 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; N10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N11 ; 112 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; N12 ; 117 ; 4 ; GPIO_1[21] ; bidir ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; N13 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; N14 ; 126 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N15 ; 133 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N16 ; 132 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P1 ; 51 ; 2 ; GPIO_0_PI[12] ; bidir ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; P2 ; 50 ; 2 ; GPIO_0_PI[1] ; bidir ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; P3 ; 53 ; 3 ; GPIO_1[26] ; bidir ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; P4 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; P5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P6 ; 67 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; P7 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; P8 ; 85 ; 3 ; GPIO_1[16] ; bidir ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; P9 ; 105 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; P10 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; P11 ; 106 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P13 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; P14 ; 119 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; P15 ; 127 ; 5 ; GPIO_0_PI[6] ; bidir ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; P16 ; 128 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R1 ; 49 ; 2 ; GPIO_0_PI[2] ; bidir ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; R2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R3 ; 54 ; 3 ; GPIO_0_PI[18] ; bidir ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; R4 ; 60 ; 3 ; GPIO_2[0] ; bidir ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; R5 ; 71 ; 3 ; GPIO_0_PI[7] ; bidir ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; R6 ; 73 ; 3 ; GPIO_0_PI[22] ; bidir ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; R7 ; 76 ; 3 ; CLOCK_50 ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
-; R8 ; 86 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; R9 ; 88 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; R10 ; 96 ; 4 ; GPIO_1[17] ; bidir ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; R11 ; 98 ; 4 ; GPIO_1[9] ; bidir ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; R12 ; 100 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; R13 ; 107 ; 4 ; GPIO_0_PI[25] ; bidir ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; R14 ; 120 ; 4 ; GPIO_1[31] ; bidir ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R16 ; 129 ; 5 ; GPIO_0_PI[13] ; bidir ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; T1 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T2 ; 59 ; 3 ; GPIO_2[9] ; bidir ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; T3 ; 55 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; T4 ; 61 ; 3 ; GPIO_2[4] ; bidir ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; T5 ; 72 ; 3 ; GPIO_0_PI[4] ; bidir ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; T6 ; 74 ; 3 ; GPIO_1[0] ; bidir ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; T7 ; 77 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; T8 ; 87 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; T9 ; 89 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
-; T10 ; 97 ; 4 ; GPIO_1_IN[1] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; T11 ; 99 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; T12 ; 101 ; 4 ; GPIO_0_PI[19] ; bidir ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; T13 ; 108 ; 4 ; GPIO_1[13] ; bidir ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; T14 ; 115 ; 4 ; GPIO_1[30] ; bidir ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; T15 ; 116 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; T16 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-Note: Pin directions (input, output or bidir) are based on device operating in user mode.
-
-
-+-------------------------------------------------+
-; I/O Assignment Warnings ;
-+-----------------+-------------------------------+
-; Pin Name ; Reason ;
-+-----------------+-------------------------------+
-; CLOCK_50 ; Incomplete set of assignments ;
-; LED[0] ; Incomplete set of assignments ;
-; LED[1] ; Incomplete set of assignments ;
-; LED[2] ; Incomplete set of assignments ;
-; LED[3] ; Incomplete set of assignments ;
-; LED[4] ; Incomplete set of assignments ;
-; LED[5] ; Incomplete set of assignments ;
-; LED[6] ; Incomplete set of assignments ;
-; LED[7] ; Incomplete set of assignments ;
-; KEY[0] ; Incomplete set of assignments ;
-; KEY[1] ; Incomplete set of assignments ;
-; GPIO_2_IN[0] ; Incomplete set of assignments ;
-; GPIO_2_IN[1] ; Incomplete set of assignments ;
-; GPIO_2_IN[2] ; Incomplete set of assignments ;
-; GPIO_0_PI_IN[0] ; Incomplete set of assignments ;
-; GPIO_0_PI_IN[1] ; Incomplete set of assignments ;
-; GPIO_1_IN[0] ; Incomplete set of assignments ;
-; GPIO_1_IN[1] ; Incomplete set of assignments ;
-; GPIO_2[0] ; Incomplete set of assignments ;
-; GPIO_2[1] ; Incomplete set of assignments ;
-; GPIO_2[2] ; Incomplete set of assignments ;
-; GPIO_2[3] ; Incomplete set of assignments ;
-; GPIO_2[4] ; Incomplete set of assignments ;
-; GPIO_2[5] ; Incomplete set of assignments ;
-; GPIO_2[6] ; Incomplete set of assignments ;
-; GPIO_2[7] ; Incomplete set of assignments ;
-; GPIO_2[8] ; Incomplete set of assignments ;
-; GPIO_2[9] ; Incomplete set of assignments ;
-; GPIO_2[10] ; Incomplete set of assignments ;
-; GPIO_2[11] ; Incomplete set of assignments ;
-; GPIO_2[12] ; Incomplete set of assignments ;
-; GPIO_0_PI[0] ; Incomplete set of assignments ;
-; GPIO_0_PI[1] ; Incomplete set of assignments ;
-; GPIO_0_PI[2] ; Incomplete set of assignments ;
-; GPIO_0_PI[3] ; Incomplete set of assignments ;
-; GPIO_0_PI[4] ; Incomplete set of assignments ;
-; GPIO_0_PI[5] ; Incomplete set of assignments ;
-; GPIO_0_PI[6] ; Incomplete set of assignments ;
-; GPIO_0_PI[7] ; Incomplete set of assignments ;
-; GPIO_0_PI[12] ; Incomplete set of assignments ;
-; GPIO_0_PI[13] ; Incomplete set of assignments ;
-; GPIO_0_PI[14] ; Incomplete set of assignments ;
-; GPIO_0_PI[15] ; Incomplete set of assignments ;
-; GPIO_0_PI[16] ; Incomplete set of assignments ;
-; GPIO_0_PI[17] ; Incomplete set of assignments ;
-; GPIO_0_PI[18] ; Incomplete set of assignments ;
-; GPIO_0_PI[19] ; Incomplete set of assignments ;
-; GPIO_0_PI[20] ; Incomplete set of assignments ;
-; GPIO_0_PI[21] ; Incomplete set of assignments ;
-; GPIO_0_PI[22] ; Incomplete set of assignments ;
-; GPIO_0_PI[23] ; Incomplete set of assignments ;
-; GPIO_0_PI[24] ; Incomplete set of assignments ;
-; GPIO_0_PI[25] ; Incomplete set of assignments ;
-; GPIO_0_PI[26] ; Incomplete set of assignments ;
-; GPIO_0_PI[27] ; Incomplete set of assignments ;
-; GPIO_0_PI[28] ; Incomplete set of assignments ;
-; GPIO_0_PI[29] ; Incomplete set of assignments ;
-; GPIO_0_PI[30] ; Incomplete set of assignments ;
-; GPIO_0_PI[32] ; Incomplete set of assignments ;
-; GPIO_0_PI[33] ; Incomplete set of assignments ;
-; GPIO_1[0] ; Incomplete set of assignments ;
-; GPIO_1[1] ; Incomplete set of assignments ;
-; GPIO_1[2] ; Incomplete set of assignments ;
-; GPIO_1[3] ; Incomplete set of assignments ;
-; GPIO_1[4] ; Incomplete set of assignments ;
-; GPIO_1[5] ; Incomplete set of assignments ;
-; GPIO_1[6] ; Incomplete set of assignments ;
-; GPIO_1[7] ; Incomplete set of assignments ;
-; GPIO_1[8] ; Incomplete set of assignments ;
-; GPIO_1[9] ; Incomplete set of assignments ;
-; GPIO_1[10] ; Incomplete set of assignments ;
-; GPIO_1[11] ; Incomplete set of assignments ;
-; GPIO_1[12] ; Incomplete set of assignments ;
-; GPIO_1[13] ; Incomplete set of assignments ;
-; GPIO_1[14] ; Incomplete set of assignments ;
-; GPIO_1[15] ; Incomplete set of assignments ;
-; GPIO_1[16] ; Incomplete set of assignments ;
-; GPIO_1[17] ; Incomplete set of assignments ;
-; GPIO_1[18] ; Incomplete set of assignments ;
-; GPIO_1[19] ; Incomplete set of assignments ;
-; GPIO_1[20] ; Incomplete set of assignments ;
-; GPIO_1[21] ; Incomplete set of assignments ;
-; GPIO_1[22] ; Incomplete set of assignments ;
-; GPIO_1[23] ; Incomplete set of assignments ;
-; GPIO_1[24] ; Incomplete set of assignments ;
-; GPIO_1[25] ; Incomplete set of assignments ;
-; GPIO_1[26] ; Incomplete set of assignments ;
-; GPIO_1[27] ; Incomplete set of assignments ;
-; GPIO_1[28] ; Incomplete set of assignments ;
-; GPIO_1[29] ; Incomplete set of assignments ;
-; GPIO_1[30] ; Incomplete set of assignments ;
-; GPIO_1[31] ; Incomplete set of assignments ;
-; GPIO_1[32] ; Incomplete set of assignments ;
-; GPIO_1[33] ; Incomplete set of assignments ;
-; GPIO_0_PI[8] ; Incomplete set of assignments ;
-; GPIO_0_PI[9] ; Incomplete set of assignments ;
-; GPIO_0_PI[10] ; Incomplete set of assignments ;
-; GPIO_0_PI[11] ; Incomplete set of assignments ;
-; GPIO_0_PI[31] ; Incomplete set of assignments ;
-; GPIO_2_IN[0] ; Missing location assignment ;
-; GPIO_2_IN[1] ; Missing location assignment ;
-; GPIO_2_IN[2] ; Missing location assignment ;
-; GPIO_0_PI_IN[0] ; Missing location assignment ;
-; GPIO_0_PI_IN[1] ; Missing location assignment ;
-; GPIO_1_IN[0] ; Missing location assignment ;
-; GPIO_1_IN[1] ; Missing location assignment ;
-; GPIO_2[0] ; Missing location assignment ;
-; GPIO_2[1] ; Missing location assignment ;
-; GPIO_2[2] ; Missing location assignment ;
-; GPIO_2[3] ; Missing location assignment ;
-; GPIO_2[4] ; Missing location assignment ;
-; GPIO_2[5] ; Missing location assignment ;
-; GPIO_2[6] ; Missing location assignment ;
-; GPIO_2[7] ; Missing location assignment ;
-; GPIO_2[8] ; Missing location assignment ;
-; GPIO_2[9] ; Missing location assignment ;
-; GPIO_2[10] ; Missing location assignment ;
-; GPIO_2[11] ; Missing location assignment ;
-; GPIO_2[12] ; Missing location assignment ;
-; GPIO_0_PI[0] ; Missing location assignment ;
-; GPIO_0_PI[1] ; Missing location assignment ;
-; GPIO_0_PI[2] ; Missing location assignment ;
-; GPIO_0_PI[3] ; Missing location assignment ;
-; GPIO_0_PI[4] ; Missing location assignment ;
-; GPIO_0_PI[6] ; Missing location assignment ;
-; GPIO_0_PI[7] ; Missing location assignment ;
-; GPIO_0_PI[12] ; Missing location assignment ;
-; GPIO_0_PI[13] ; Missing location assignment ;
-; GPIO_0_PI[14] ; Missing location assignment ;
-; GPIO_0_PI[15] ; Missing location assignment ;
-; GPIO_0_PI[16] ; Missing location assignment ;
-; GPIO_0_PI[18] ; Missing location assignment ;
-; GPIO_0_PI[19] ; Missing location assignment ;
-; GPIO_0_PI[20] ; Missing location assignment ;
-; GPIO_0_PI[21] ; Missing location assignment ;
-; GPIO_0_PI[22] ; Missing location assignment ;
-; GPIO_0_PI[23] ; Missing location assignment ;
-; GPIO_0_PI[24] ; Missing location assignment ;
-; GPIO_0_PI[25] ; Missing location assignment ;
-; GPIO_0_PI[26] ; Missing location assignment ;
-; GPIO_0_PI[30] ; Missing location assignment ;
-; GPIO_0_PI[32] ; Missing location assignment ;
-; GPIO_0_PI[33] ; Missing location assignment ;
-; GPIO_1[0] ; Missing location assignment ;
-; GPIO_1[1] ; Missing location assignment ;
-; GPIO_1[2] ; Missing location assignment ;
-; GPIO_1[3] ; Missing location assignment ;
-; GPIO_1[4] ; Missing location assignment ;
-; GPIO_1[5] ; Missing location assignment ;
-; GPIO_1[6] ; Missing location assignment ;
-; GPIO_1[7] ; Missing location assignment ;
-; GPIO_1[8] ; Missing location assignment ;
-; GPIO_1[9] ; Missing location assignment ;
-; GPIO_1[10] ; Missing location assignment ;
-; GPIO_1[11] ; Missing location assignment ;
-; GPIO_1[12] ; Missing location assignment ;
-; GPIO_1[13] ; Missing location assignment ;
-; GPIO_1[14] ; Missing location assignment ;
-; GPIO_1[15] ; Missing location assignment ;
-; GPIO_1[16] ; Missing location assignment ;
-; GPIO_1[17] ; Missing location assignment ;
-; GPIO_1[18] ; Missing location assignment ;
-; GPIO_1[19] ; Missing location assignment ;
-; GPIO_1[20] ; Missing location assignment ;
-; GPIO_1[21] ; Missing location assignment ;
-; GPIO_1[22] ; Missing location assignment ;
-; GPIO_1[23] ; Missing location assignment ;
-; GPIO_1[24] ; Missing location assignment ;
-; GPIO_1[25] ; Missing location assignment ;
-; GPIO_1[26] ; Missing location assignment ;
-; GPIO_1[27] ; Missing location assignment ;
-; GPIO_1[28] ; Missing location assignment ;
-; GPIO_1[29] ; Missing location assignment ;
-; GPIO_1[30] ; Missing location assignment ;
-; GPIO_1[31] ; Missing location assignment ;
-; GPIO_1[32] ; Missing location assignment ;
-; GPIO_1[33] ; Missing location assignment ;
-; GPIO_0_PI[8] ; Missing location assignment ;
-; GPIO_0_PI[10] ; Missing location assignment ;
-+-----------------+-------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Resource Utilization by Entity ;
-+-----------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------------------+-------------+--------------+
-; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
-+-----------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------------------+-------------+--------------+
-; |MyDE0_Nano ; 40 (0) ; 38 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 99 ; 0 ; 2 (0) ; 1 (0) ; 37 (0) ; |MyDE0_Nano ; MyDE0_Nano ; work ;
-; |spi_slave:spi_slave_instance| ; 40 (40) ; 38 (38) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 1 (1) ; 37 (37) ; |MyDE0_Nano|spi_slave:spi_slave_instance ; spi_slave ; work ;
-+-----------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------------------+-------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+-------------------------------------------------------------------------------------------------+
-; Delay Chain Summary ;
-+-----------------+----------+---------------+---------------+-----------------------+-----+------+
-; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
-+-----------------+----------+---------------+---------------+-----------------------+-----+------+
-; CLOCK_50 ; Input ; -- ; -- ; -- ; -- ; -- ;
-; LED[0] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LED[1] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LED[2] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LED[3] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LED[4] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LED[5] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LED[6] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; LED[7] ; Output ; -- ; -- ; -- ; -- ; -- ;
-; KEY[0] ; Input ; -- ; -- ; -- ; -- ; -- ;
-; KEY[1] ; Input ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_2_IN[0] ; Input ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_2_IN[1] ; Input ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_2_IN[2] ; Input ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_0_PI_IN[0] ; Input ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_0_PI_IN[1] ; Input ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_1_IN[0] ; Input ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_1_IN[1] ; Input ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_2[0] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_2[1] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_2[2] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_2[3] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_2[4] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_2[5] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_2[6] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_2[7] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_2[8] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_2[9] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_2[10] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_2[11] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_2[12] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_0_PI[0] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_0_PI[1] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_0_PI[2] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_0_PI[3] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_0_PI[4] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_0_PI[5] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_0_PI[6] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_0_PI[7] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_0_PI[12] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_0_PI[13] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_0_PI[14] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_0_PI[15] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_0_PI[16] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_0_PI[17] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_0_PI[18] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_0_PI[19] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_0_PI[20] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_0_PI[21] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_0_PI[22] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_0_PI[23] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_0_PI[24] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_0_PI[25] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_0_PI[26] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_0_PI[27] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_0_PI[28] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_0_PI[29] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_0_PI[30] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_0_PI[32] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_0_PI[33] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_1[0] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_1[1] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_1[2] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_1[3] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_1[4] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_1[5] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_1[6] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_1[7] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_1[8] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_1[9] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_1[10] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_1[11] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_1[12] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_1[13] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_1[14] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_1[15] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_1[16] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_1[17] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_1[18] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_1[19] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_1[20] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_1[21] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_1[22] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_1[23] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_1[24] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_1[25] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_1[26] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_1[27] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_1[28] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_1[29] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_1[30] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_1[31] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_1[32] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_1[33] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_0_PI[8] ; Bidir ; (0) 0 ps ; -- ; -- ; -- ; -- ;
-; GPIO_0_PI[9] ; Bidir ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-; GPIO_0_PI[10] ; Bidir ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
-; GPIO_0_PI[11] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
-; GPIO_0_PI[31] ; Bidir ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-+-----------------+----------+---------------+---------------+-----------------------+-----+------+
-
-
-+------------------------------------------------------------------------+
-; Pad To Core Delay Chain Fanout ;
-+------------------------------------------+-------------------+---------+
-; Source Pin / Fanout ; Pad To Core Index ; Setting ;
-+------------------------------------------+-------------------+---------+
-; CLOCK_50 ; ; ;
-; KEY[0] ; ; ;
-; KEY[1] ; ; ;
-; GPIO_2_IN[0] ; ; ;
-; GPIO_2_IN[1] ; ; ;
-; GPIO_2_IN[2] ; ; ;
-; GPIO_0_PI_IN[0] ; ; ;
-; GPIO_0_PI_IN[1] ; ; ;
-; GPIO_1_IN[0] ; ; ;
-; GPIO_1_IN[1] ; ; ;
-; GPIO_2[0] ; ; ;
-; GPIO_2[1] ; ; ;
-; GPIO_2[2] ; ; ;
-; GPIO_2[3] ; ; ;
-; GPIO_2[4] ; ; ;
-; GPIO_2[5] ; ; ;
-; GPIO_2[6] ; ; ;
-; GPIO_2[7] ; ; ;
-; GPIO_2[8] ; ; ;
-; GPIO_2[9] ; ; ;
-; GPIO_2[10] ; ; ;
-; GPIO_2[11] ; ; ;
-; GPIO_2[12] ; ; ;
-; GPIO_0_PI[0] ; ; ;
-; GPIO_0_PI[1] ; ; ;
-; GPIO_0_PI[2] ; ; ;
-; GPIO_0_PI[3] ; ; ;
-; GPIO_0_PI[4] ; ; ;
-; GPIO_0_PI[5] ; ; ;
-; GPIO_0_PI[6] ; ; ;
-; GPIO_0_PI[7] ; ; ;
-; GPIO_0_PI[12] ; ; ;
-; GPIO_0_PI[13] ; ; ;
-; GPIO_0_PI[14] ; ; ;
-; GPIO_0_PI[15] ; ; ;
-; GPIO_0_PI[16] ; ; ;
-; GPIO_0_PI[17] ; ; ;
-; GPIO_0_PI[18] ; ; ;
-; GPIO_0_PI[19] ; ; ;
-; GPIO_0_PI[20] ; ; ;
-; GPIO_0_PI[21] ; ; ;
-; GPIO_0_PI[22] ; ; ;
-; GPIO_0_PI[23] ; ; ;
-; GPIO_0_PI[24] ; ; ;
-; GPIO_0_PI[25] ; ; ;
-; GPIO_0_PI[26] ; ; ;
-; GPIO_0_PI[27] ; ; ;
-; GPIO_0_PI[28] ; ; ;
-; GPIO_0_PI[29] ; ; ;
-; GPIO_0_PI[30] ; ; ;
-; GPIO_0_PI[32] ; ; ;
-; GPIO_0_PI[33] ; ; ;
-; GPIO_1[0] ; ; ;
-; GPIO_1[1] ; ; ;
-; GPIO_1[2] ; ; ;
-; GPIO_1[3] ; ; ;
-; GPIO_1[4] ; ; ;
-; GPIO_1[5] ; ; ;
-; GPIO_1[6] ; ; ;
-; GPIO_1[7] ; ; ;
-; GPIO_1[8] ; ; ;
-; GPIO_1[9] ; ; ;
-; GPIO_1[10] ; ; ;
-; GPIO_1[11] ; ; ;
-; GPIO_1[12] ; ; ;
-; GPIO_1[13] ; ; ;
-; GPIO_1[14] ; ; ;
-; GPIO_1[15] ; ; ;
-; GPIO_1[16] ; ; ;
-; GPIO_1[17] ; ; ;
-; GPIO_1[18] ; ; ;
-; GPIO_1[19] ; ; ;
-; GPIO_1[20] ; ; ;
-; GPIO_1[21] ; ; ;
-; GPIO_1[22] ; ; ;
-; GPIO_1[23] ; ; ;
-; GPIO_1[24] ; ; ;
-; GPIO_1[25] ; ; ;
-; GPIO_1[26] ; ; ;
-; GPIO_1[27] ; ; ;
-; GPIO_1[28] ; ; ;
-; GPIO_1[29] ; ; ;
-; GPIO_1[30] ; ; ;
-; GPIO_1[31] ; ; ;
-; GPIO_1[32] ; ; ;
-; GPIO_1[33] ; ; ;
-; GPIO_0_PI[8] ; ; ;
-; GPIO_0_PI[9] ; ; ;
-; - spi_slave:spi_slave_instance|q[0] ; 0 ; 6 ;
-; GPIO_0_PI[10] ; ; ;
-; - GPIO_0_PI[11]~output ; 1 ; 6 ;
-; GPIO_0_PI[11] ; ; ;
-; GPIO_0_PI[31] ; ; ;
-; - spi_slave:spi_slave_instance|q~31 ; 0 ; 6 ;
-+------------------------------------------+-------------------+---------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------+
-; Control Signals ;
-+---------------+----------+---------+---------------+--------+----------------------+------------------+---------------------------+
-; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
-+---------------+----------+---------+---------------+--------+----------------------+------------------+---------------------------+
-; GPIO_0_PI[10] ; PIN_E7 ; 1 ; Output enable ; no ; -- ; -- ; -- ;
-; GPIO_0_PI[8] ; PIN_G2 ; 38 ; Clock ; yes ; Global Clock ; GCLK0 ; -- ;
-+---------------+----------+---------+---------------+--------+----------------------+------------------+---------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------+
-; Global & Other Fast Signals ;
-+--------------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+
-; Name ; Location ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
-+--------------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+
-; GPIO_0_PI[8] ; PIN_G2 ; 38 ; 0 ; Global Clock ; GCLK0 ; -- ;
-+--------------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+
-
-
-+-----------------------------------------------+
-; Routing Usage Summary ;
-+-----------------------+-----------------------+
-; Routing Resource Type ; Usage ;
-+-----------------------+-----------------------+
-; Block interconnects ; 18 / 71,559 ( < 1 % ) ;
-; C16 interconnects ; 3 / 2,597 ( < 1 % ) ;
-; C4 interconnects ; 3 / 46,848 ( < 1 % ) ;
-; Direct links ; 14 / 71,559 ( < 1 % ) ;
-; Global clocks ; 1 / 20 ( 5 % ) ;
-; Local interconnects ; 34 / 24,624 ( < 1 % ) ;
-; R24 interconnects ; 2 / 2,496 ( < 1 % ) ;
-; R4 interconnects ; 3 / 62,424 ( < 1 % ) ;
-+-----------------------+-----------------------+
-
-
-+---------------------------------------------------------------------------+
-; LAB Logic Elements ;
-+---------------------------------------------+-----------------------------+
-; Number of Logic Elements (Average = 13.33) ; Number of LABs (Total = 3) ;
-+---------------------------------------------+-----------------------------+
-; 1 ; 0 ;
-; 2 ; 0 ;
-; 3 ; 0 ;
-; 4 ; 0 ;
-; 5 ; 0 ;
-; 6 ; 0 ;
-; 7 ; 0 ;
-; 8 ; 0 ;
-; 9 ; 1 ;
-; 10 ; 0 ;
-; 11 ; 0 ;
-; 12 ; 0 ;
-; 13 ; 0 ;
-; 14 ; 0 ;
-; 15 ; 1 ;
-; 16 ; 1 ;
-+---------------------------------------------+-----------------------------+
-
-
-+------------------------------------------------------------------+
-; LAB-wide Signals ;
-+------------------------------------+-----------------------------+
-; LAB-wide Signals (Average = 1.00) ; Number of LABs (Total = 3) ;
-+------------------------------------+-----------------------------+
-; 1 Clock ; 3 ;
-+------------------------------------+-----------------------------+
-
-
-+----------------------------------------------------------------------------+
-; LAB Signals Sourced ;
-+----------------------------------------------+-----------------------------+
-; Number of Signals Sourced (Average = 25.67) ; Number of LABs (Total = 3) ;
-+----------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 0 ;
-; 2 ; 0 ;
-; 3 ; 0 ;
-; 4 ; 0 ;
-; 5 ; 0 ;
-; 6 ; 0 ;
-; 7 ; 0 ;
-; 8 ; 0 ;
-; 9 ; 0 ;
-; 10 ; 0 ;
-; 11 ; 0 ;
-; 12 ; 0 ;
-; 13 ; 0 ;
-; 14 ; 0 ;
-; 15 ; 0 ;
-; 16 ; 0 ;
-; 17 ; 1 ;
-; 18 ; 0 ;
-; 19 ; 0 ;
-; 20 ; 0 ;
-; 21 ; 0 ;
-; 22 ; 0 ;
-; 23 ; 0 ;
-; 24 ; 0 ;
-; 25 ; 0 ;
-; 26 ; 0 ;
-; 27 ; 0 ;
-; 28 ; 0 ;
-; 29 ; 1 ;
-; 30 ; 0 ;
-; 31 ; 1 ;
-+----------------------------------------------+-----------------------------+
-
-
-+-------------------------------------------------------------------------------+
-; LAB Signals Sourced Out ;
-+-------------------------------------------------+-----------------------------+
-; Number of Signals Sourced Out (Average = 3.67) ; Number of LABs (Total = 3) ;
-+-------------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 1 ;
-; 2 ; 1 ;
-; 3 ; 0 ;
-; 4 ; 0 ;
-; 5 ; 0 ;
-; 6 ; 0 ;
-; 7 ; 0 ;
-; 8 ; 1 ;
-+-------------------------------------------------+-----------------------------+
-
-
-+---------------------------------------------------------------------------+
-; LAB Distinct Inputs ;
-+---------------------------------------------+-----------------------------+
-; Number of Distinct Inputs (Average = 5.67) ; Number of LABs (Total = 3) ;
-+---------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 0 ;
-; 2 ; 0 ;
-; 3 ; 1 ;
-; 4 ; 0 ;
-; 5 ; 0 ;
-; 6 ; 1 ;
-; 7 ; 0 ;
-; 8 ; 1 ;
-+---------------------------------------------+-----------------------------+
-
-
-+------------------------------------------+
-; I/O Rules Summary ;
-+----------------------------------+-------+
-; I/O Rules Statistic ; Total ;
-+----------------------------------+-------+
-; Total I/O Rules ; 30 ;
-; Number of I/O Rules Passed ; 13 ;
-; Number of I/O Rules Failed ; 0 ;
-; Number of I/O Rules Unchecked ; 0 ;
-; Number of I/O Rules Inapplicable ; 17 ;
-+----------------------------------+-------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Details ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ;
-; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ;
-; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ;
-; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ;
-; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
-; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
-; Pass ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ;
-; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ;
-; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Matrix ;
-+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
-; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000033 ; IO_000034 ; IO_000042 ;
-+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
-; Total Pass ; 19 ; 0 ; 19 ; 0 ; 0 ; 99 ; 19 ; 0 ; 99 ; 99 ; 0 ; 89 ; 0 ; 0 ; 91 ; 0 ; 89 ; 91 ; 0 ; 0 ; 80 ; 89 ; 0 ; 0 ; 0 ; 0 ; 0 ; 99 ; 0 ; 0 ;
-; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; Total Inapplicable ; 80 ; 99 ; 80 ; 99 ; 99 ; 0 ; 80 ; 99 ; 0 ; 0 ; 99 ; 10 ; 99 ; 99 ; 8 ; 99 ; 10 ; 8 ; 99 ; 99 ; 19 ; 10 ; 99 ; 99 ; 99 ; 99 ; 99 ; 0 ; 99 ; 99 ;
-; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; CLOCK_50 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; LED[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; LED[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; LED[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; LED[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; LED[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; LED[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; LED[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; LED[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; KEY[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; KEY[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_2_IN[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_2_IN[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_2_IN[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_0_PI_IN[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_0_PI_IN[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_1_IN[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_1_IN[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_2[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_2[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_2[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_2[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_2[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_2[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_2[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_2[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_2[8] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_2[9] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_2[10] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_2[11] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_2[12] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_0_PI[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_0_PI[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_0_PI[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_0_PI[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_0_PI[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_0_PI[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_0_PI[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_0_PI[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_0_PI[12] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_0_PI[13] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_0_PI[14] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_0_PI[15] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_0_PI[16] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_0_PI[17] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_0_PI[18] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_0_PI[19] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_0_PI[20] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_0_PI[21] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_0_PI[22] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_0_PI[23] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_0_PI[24] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_0_PI[25] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_0_PI[26] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_0_PI[27] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_0_PI[28] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_0_PI[29] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_0_PI[30] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_0_PI[32] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_0_PI[33] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_1[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_1[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_1[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_1[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_1[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_1[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_1[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_1[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_1[8] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_1[9] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_1[10] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_1[11] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_1[12] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_1[13] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_1[14] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_1[15] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_1[16] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_1[17] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_1[18] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_1[19] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_1[20] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_1[21] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_1[22] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_1[23] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_1[24] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_1[25] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_1[26] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_1[27] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_1[28] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_1[29] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_1[30] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_1[31] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_1[32] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_1[33] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_0_PI[8] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_0_PI[9] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_0_PI[10] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_0_PI[11] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; GPIO_0_PI[31] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
-
-
-+---------------------------------------------------------------------------------------------+
-; Fitter Device Options ;
-+------------------------------------------------------------------+--------------------------+
-; Option ; Setting ;
-+------------------------------------------------------------------+--------------------------+
-; Enable user-supplied start-up clock (CLKUSR) ; Off ;
-; Enable device-wide reset (DEV_CLRn) ; Off ;
-; Enable device-wide output enable (DEV_OE) ; Off ;
-; Enable INIT_DONE output ; Off ;
-; Configuration scheme ; Active Serial ;
-; Error detection CRC ; Off ;
-; Enable open drain on CRC_ERROR pin ; Off ;
-; Enable input tri-state on active configuration pins in user mode ; Off ;
-; Configuration Voltage Level ; Auto ;
-; Force Configuration Voltage Level ; Off ;
-; nCEO ; As output driving ground ;
-; Data[0] ; As input tri-stated ;
-; Data[1]/ASDO ; As input tri-stated ;
-; Data[7..2] ; Unreserved ;
-; FLASH_nCE/nCSO ; As input tri-stated ;
-; Other Active Parallel pins ; Unreserved ;
-; DCLK ; As output driving ground ;
-+------------------------------------------------------------------+--------------------------+
-
-
-+------------------------------------+
-; Operating Settings and Conditions ;
-+---------------------------+--------+
-; Setting ; Value ;
-+---------------------------+--------+
-; Nominal Core Voltage ; 1.20 V ;
-; Low Junction Temperature ; 0 °C ;
-; High Junction Temperature ; 85 °C ;
-+---------------------------+--------+
-
-
-+-----------------+
-; Fitter Messages ;
-+-----------------+
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (119006): Selected device EP4CE22F17C6 for design "SPI_test"
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
-Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
-Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
- Info (176445): Device EP4CE10F17C6 is compatible
- Info (176445): Device EP4CE6F17C6 is compatible
- Info (176445): Device EP4CE15F17C6 is compatible
-Info (169124): Fitter converted 5 user pins into dedicated programming pins
- Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1
- Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2
- Info (169125): Pin ~ALTERA_DCLK~ is reserved at location H1
- Info (169125): Pin ~ALTERA_DATA0~ is reserved at location H2
- Info (169125): Pin ~ALTERA_nCEO~ is reserved at location F16
-Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
-Critical Warning (169085): No exact pin location assignment(s) for 80 pins of 99 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report.
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'SPI_test.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332144): No user constrained base clocks found in the design
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
-Info (176353): Automatically promoted node GPIO_0_PI[8]~input (placed in PIN G2 (DIFFIO_L6p, DQS0L/CQ1L,DPCLK0)) File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G0
-Info (176233): Starting register packing
-Info (176235): Finished register packing
- Extra Info (176219): No registers were packed into other blocks
-Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
- Info (176211): Number of I/O pins in group: 79 (unused VREF, 2.5V VCCIO, 7 input, 0 output, 72 bidirectional)
- Info (176212): I/O standards used: 2.5 V.
-Info (176215): I/O bank details before I/O pin placement
- Info (176214): Statistics of I/O banks
- Info (176213): I/O bank number 1 does not use VREF pins and has 2.5V VCCIO pins. 9 total pin(s) used -- 5 pins available
- Info (176213): I/O bank number 2 does not use VREF pins and has 2.5V VCCIO pins. 1 total pin(s) used -- 15 pins available
- Info (176213): I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 24 pins available
- Info (176213): I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 20 pins available
- Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 17 pins available
- Info (176213): I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 12 pins available
- Info (176213): I/O bank number 7 does not use VREF pins and has 2.5V VCCIO pins. 8 total pin(s) used -- 16 pins available
- Info (176213): I/O bank number 8 does not use VREF pins and has 2.5V VCCIO pins. 4 total pin(s) used -- 20 pins available
-Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
-Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
-Info (170189): Fitter placement preparation operations beginning
-Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
-Info (170191): Fitter placement operations beginning
-Info (170137): Fitter placement was successful
-Info (170192): Fitter placement operations ending: elapsed time is 00:00:02
-Info (170193): Fitter routing operations beginning
-Info (170195): Router estimated average interconnect usage is 0% of the available device resources
- Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X10_Y23 to location X20_Y34
-Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
- Info (170201): Optimizations that may affect the design's routability were skipped
-Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
-Info (11888): Total time spent on timing analysis during the Fitter is 0.11 seconds.
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01
-Warning (169064): Following 80 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
- Info (169065): Pin GPIO_2[0] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 13
- Info (169065): Pin GPIO_2[1] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 13
- Info (169065): Pin GPIO_2[2] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 13
- Info (169065): Pin GPIO_2[3] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 13
- Info (169065): Pin GPIO_2[4] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 13
- Info (169065): Pin GPIO_2[5] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 13
- Info (169065): Pin GPIO_2[6] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 13
- Info (169065): Pin GPIO_2[7] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 13
- Info (169065): Pin GPIO_2[8] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 13
- Info (169065): Pin GPIO_2[9] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 13
- Info (169065): Pin GPIO_2[10] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 13
- Info (169065): Pin GPIO_2[11] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 13
- Info (169065): Pin GPIO_2[12] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 13
- Info (169065): Pin GPIO_0_PI[0] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Info (169065): Pin GPIO_0_PI[1] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Info (169065): Pin GPIO_0_PI[2] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Info (169065): Pin GPIO_0_PI[3] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Info (169065): Pin GPIO_0_PI[4] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Info (169065): Pin GPIO_0_PI[5] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Info (169065): Pin GPIO_0_PI[6] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Info (169065): Pin GPIO_0_PI[7] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Info (169065): Pin GPIO_0_PI[12] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Info (169065): Pin GPIO_0_PI[13] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Info (169065): Pin GPIO_0_PI[14] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Info (169065): Pin GPIO_0_PI[15] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Info (169065): Pin GPIO_0_PI[16] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Info (169065): Pin GPIO_0_PI[17] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Info (169065): Pin GPIO_0_PI[18] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Info (169065): Pin GPIO_0_PI[19] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Info (169065): Pin GPIO_0_PI[20] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Info (169065): Pin GPIO_0_PI[21] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Info (169065): Pin GPIO_0_PI[22] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Info (169065): Pin GPIO_0_PI[23] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Info (169065): Pin GPIO_0_PI[24] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Info (169065): Pin GPIO_0_PI[25] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Info (169065): Pin GPIO_0_PI[26] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Info (169065): Pin GPIO_0_PI[27] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Info (169065): Pin GPIO_0_PI[28] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Info (169065): Pin GPIO_0_PI[29] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Info (169065): Pin GPIO_0_PI[30] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Info (169065): Pin GPIO_0_PI[32] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Info (169065): Pin GPIO_0_PI[33] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Info (169065): Pin GPIO_1[0] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Info (169065): Pin GPIO_1[1] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Info (169065): Pin GPIO_1[2] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Info (169065): Pin GPIO_1[3] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Info (169065): Pin GPIO_1[4] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Info (169065): Pin GPIO_1[5] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Info (169065): Pin GPIO_1[6] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Info (169065): Pin GPIO_1[7] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Info (169065): Pin GPIO_1[8] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Info (169065): Pin GPIO_1[9] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Info (169065): Pin GPIO_1[10] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Info (169065): Pin GPIO_1[11] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Info (169065): Pin GPIO_1[12] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Info (169065): Pin GPIO_1[13] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Info (169065): Pin GPIO_1[14] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Info (169065): Pin GPIO_1[15] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Info (169065): Pin GPIO_1[16] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Info (169065): Pin GPIO_1[17] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Info (169065): Pin GPIO_1[18] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Info (169065): Pin GPIO_1[19] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Info (169065): Pin GPIO_1[20] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Info (169065): Pin GPIO_1[21] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Info (169065): Pin GPIO_1[22] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Info (169065): Pin GPIO_1[23] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Info (169065): Pin GPIO_1[24] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Info (169065): Pin GPIO_1[25] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Info (169065): Pin GPIO_1[26] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Info (169065): Pin GPIO_1[27] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Info (169065): Pin GPIO_1[28] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Info (169065): Pin GPIO_1[29] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Info (169065): Pin GPIO_1[30] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Info (169065): Pin GPIO_1[31] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Info (169065): Pin GPIO_1[32] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Info (169065): Pin GPIO_1[33] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Info (169065): Pin GPIO_0_PI[8] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Info (169065): Pin GPIO_0_PI[9] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Info (169065): Pin GPIO_0_PI[10] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Info (169065): Pin GPIO_0_PI[31] has a permanently disabled output enable File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
-Info (144001): Generated suppressed messages file C:/Users/damie/Documents/Minibot/SPI/output_files/SPI_test.fit.smsg
-Info: Quartus Prime Fitter was successful. 0 errors, 6 warnings
- Info: Peak virtual memory: 5515 megabytes
- Info: Processing ended: Wed Nov 16 16:51:40 2022
- Info: Elapsed time: 00:00:07
- Info: Total CPU time (on all processors): 00:00:09
-
-
-+----------------------------+
-; Fitter Suppressed Messages ;
-+----------------------------+
-The suppressed messages can be found in C:/Users/damie/Documents/Minibot/SPI/output_files/SPI_test.fit.smsg.
-
-
diff --git a/SPI/output_files/SPI_test.fit.smsg b/SPI/output_files/SPI_test.fit.smsg
deleted file mode 100644
index 7121cbb1d5a671028e3f4ca4b9ee7c2046dfe1da..0000000000000000000000000000000000000000
--- a/SPI/output_files/SPI_test.fit.smsg
+++ /dev/null
@@ -1,8 +0,0 @@
-Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
-Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
-Extra Info (176236): Started Fast Input/Output/OE register processing
-Extra Info (176237): Finished Fast Input/Output/OE register processing
-Extra Info (176238): Start inferring scan chains for DSP blocks
-Extra Info (176239): Inferring scan chains for DSP blocks is complete
-Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
-Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/SPI/output_files/SPI_test.fit.summary b/SPI/output_files/SPI_test.fit.summary
deleted file mode 100644
index 6a030a526a8d04fb4370df19a07853e6bf0880e1..0000000000000000000000000000000000000000
--- a/SPI/output_files/SPI_test.fit.summary
+++ /dev/null
@@ -1,16 +0,0 @@
-Fitter Status : Successful - Wed Nov 16 16:51:40 2022
-Quartus Prime Version : 18.1.0 Build 625 09/12/2018 SJ Lite Edition
-Revision Name : SPI_test
-Top-level Entity Name : MyDE0_Nano
-Family : Cyclone IV E
-Device : EP4CE22F17C6
-Timing Models : Final
-Total logic elements : 40 / 22,320 ( < 1 % )
- Total combinational functions : 39 / 22,320 ( < 1 % )
- Dedicated logic registers : 38 / 22,320 ( < 1 % )
-Total registers : 38
-Total pins : 99 / 154 ( 64 % )
-Total virtual pins : 0
-Total memory bits : 0 / 608,256 ( 0 % )
-Embedded Multiplier 9-bit elements : 0 / 132 ( 0 % )
-Total PLLs : 0 / 4 ( 0 % )
diff --git a/SPI/output_files/SPI_test.flow.rpt b/SPI/output_files/SPI_test.flow.rpt
deleted file mode 100644
index 9d966d1b7793e96f60ea19e27c5ef3b05c095493..0000000000000000000000000000000000000000
--- a/SPI/output_files/SPI_test.flow.rpt
+++ /dev/null
@@ -1,132 +0,0 @@
-Flow report for SPI_test
-Wed Nov 16 16:51:48 2022
-Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Flow Summary
- 3. Flow Settings
- 4. Flow Non-Default Global Settings
- 5. Flow Elapsed Time
- 6. Flow OS Summary
- 7. Flow Log
- 8. Flow Messages
- 9. Flow Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2018 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details.
-
-
-
-+----------------------------------------------------------------------------------+
-; Flow Summary ;
-+------------------------------------+---------------------------------------------+
-; Flow Status ; Successful - Wed Nov 16 16:51:48 2022 ;
-; Quartus Prime Version ; 18.1.0 Build 625 09/12/2018 SJ Lite Edition ;
-; Revision Name ; SPI_test ;
-; Top-level Entity Name ; MyDE0_Nano ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE22F17C6 ;
-; Timing Models ; Final ;
-; Total logic elements ; 40 / 22,320 ( < 1 % ) ;
-; Total combinational functions ; 39 / 22,320 ( < 1 % ) ;
-; Dedicated logic registers ; 38 / 22,320 ( < 1 % ) ;
-; Total registers ; 38 ;
-; Total pins ; 99 / 154 ( 64 % ) ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 / 608,256 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ;
-; Total PLLs ; 0 / 4 ( 0 % ) ;
-+------------------------------------+---------------------------------------------+
-
-
-+-----------------------------------------+
-; Flow Settings ;
-+-------------------+---------------------+
-; Option ; Setting ;
-+-------------------+---------------------+
-; Start date & time ; 11/16/2022 16:51:22 ;
-; Main task ; Compilation ;
-; Revision Name ; SPI_test ;
-+-------------------+---------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings ;
-+-------------------------------------+----------------------------------------+---------------+-------------+----------------+
-; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
-+-------------------------------------+----------------------------------------+---------------+-------------+----------------+
-; COMPILER_SIGNATURE_ID ; 123519564958.166861388108744 ; -- ; -- ; -- ;
-; EDA_OUTPUT_DATA_FORMAT ; Systemverilog Hdl ; -- ; -- ; eda_simulation ;
-; EDA_SIMULATION_TOOL ; ModelSim-Altera (SystemVerilog) ; <None> ; -- ; -- ;
-; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
-; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
-; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
-; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ;
-; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; MyDE0_Nano ; Top ;
-; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; MyDE0_Nano ; Top ;
-; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; MyDE0_Nano ; Top ;
-; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
-; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
-; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
-; TOP_LEVEL_ENTITY ; MyDE0_Nano ; SPI_test ; -- ; -- ;
-+-------------------------------------+----------------------------------------+---------------+-------------+----------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------+
-; Flow Elapsed Time ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 4777 MB ; 00:00:23 ;
-; Fitter ; 00:00:07 ; 1.0 ; 5515 MB ; 00:00:08 ;
-; Assembler ; 00:00:01 ; 1.0 ; 4674 MB ; 00:00:01 ;
-; Timing Analyzer ; 00:00:02 ; 1.0 ; 4775 MB ; 00:00:02 ;
-; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 4635 MB ; 00:00:01 ;
-; Total ; 00:00:22 ; -- ; -- ; 00:00:35 ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-
-
-+------------------------------------------------------------------------------------+
-; Flow OS Summary ;
-+----------------------+------------------+------------+------------+----------------+
-; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
-+----------------------+------------------+------------+------------+----------------+
-; Analysis & Synthesis ; DESKTOP-5JFKADR ; Windows 10 ; 10.0 ; x86_64 ;
-; Fitter ; DESKTOP-5JFKADR ; Windows 10 ; 10.0 ; x86_64 ;
-; Assembler ; DESKTOP-5JFKADR ; Windows 10 ; 10.0 ; x86_64 ;
-; Timing Analyzer ; DESKTOP-5JFKADR ; Windows 10 ; 10.0 ; x86_64 ;
-; EDA Netlist Writer ; DESKTOP-5JFKADR ; Windows 10 ; 10.0 ; x86_64 ;
-+----------------------+------------------+------------+------------+----------------+
-
-
-------------
-; Flow Log ;
-------------
-quartus_map --read_settings_files=on --write_settings_files=off SPI_test -c SPI_test
-quartus_fit --read_settings_files=off --write_settings_files=off SPI_test -c SPI_test
-quartus_asm --read_settings_files=off --write_settings_files=off SPI_test -c SPI_test
-quartus_sta SPI_test -c SPI_test
-quartus_eda --read_settings_files=off --write_settings_files=off SPI_test -c SPI_test
-
-
-
diff --git a/SPI/output_files/SPI_test.jdi b/SPI/output_files/SPI_test.jdi
deleted file mode 100644
index 0999639c4e166a2933c938db5c9128b683891a4f..0000000000000000000000000000000000000000
--- a/SPI/output_files/SPI_test.jdi
+++ /dev/null
@@ -1,8 +0,0 @@
-<sld_project_info>
- <project>
- <hash md5_digest_80b="874873a42d5e601c8b01"/>
- </project>
- <file_info>
- <file device="EP4CE22F17C6" path="SPI_test.sof" usercode="0xFFFFFFFF"/>
- </file_info>
-</sld_project_info>
diff --git a/SPI/output_files/SPI_test.map.rpt b/SPI/output_files/SPI_test.map.rpt
deleted file mode 100644
index e907d8783734dd7381dc19bd360f26118fc4d496..0000000000000000000000000000000000000000
--- a/SPI/output_files/SPI_test.map.rpt
+++ /dev/null
@@ -1,416 +0,0 @@
-Analysis & Synthesis report for SPI_test
-Wed Nov 16 16:51:32 2022
-Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Analysis & Synthesis Summary
- 3. Analysis & Synthesis Settings
- 4. Parallel Compilation
- 5. Analysis & Synthesis Source Files Read
- 6. Analysis & Synthesis Resource Usage Summary
- 7. Analysis & Synthesis Resource Utilization by Entity
- 8. General Register Statistics
- 9. Port Connectivity Checks: "spi_slave:spi_slave_instance"
- 10. Post-Synthesis Netlist Statistics for Top Partition
- 11. Elapsed Time Per Partition
- 12. Analysis & Synthesis Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2018 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details.
-
-
-
-+----------------------------------------------------------------------------------+
-; Analysis & Synthesis Summary ;
-+------------------------------------+---------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Wed Nov 16 16:51:32 2022 ;
-; Quartus Prime Version ; 18.1.0 Build 625 09/12/2018 SJ Lite Edition ;
-; Revision Name ; SPI_test ;
-; Top-level Entity Name ; MyDE0_Nano ;
-; Family ; Cyclone IV E ;
-; Total logic elements ; 41 ;
-; Total combinational functions ; 39 ;
-; Dedicated logic registers ; 38 ;
-; Total registers ; 38 ;
-; Total pins ; 99 ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 ;
-; Embedded Multiplier 9-bit elements ; 0 ;
-; Total PLLs ; 0 ;
-+------------------------------------+---------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Settings ;
-+------------------------------------------------------------------+--------------------+--------------------+
-; Option ; Setting ; Default Value ;
-+------------------------------------------------------------------+--------------------+--------------------+
-; Device ; EP4CE22F17C6 ; ;
-; Top-level entity name ; MyDE0_Nano ; SPI_test ;
-; Family name ; Cyclone IV E ; Cyclone V ;
-; Use smart compilation ; Off ; Off ;
-; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
-; Enable compact report table ; Off ; Off ;
-; Restructure Multiplexers ; Auto ; Auto ;
-; Create Debugging Nodes for IP Cores ; Off ; Off ;
-; Preserve fewer node names ; On ; On ;
-; Intel FPGA IP Evaluation Mode ; Enable ; Enable ;
-; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
-; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
-; State Machine Processing ; Auto ; Auto ;
-; Safe State Machine ; Off ; Off ;
-; Extract Verilog State Machines ; On ; On ;
-; Extract VHDL State Machines ; On ; On ;
-; Ignore Verilog initial constructs ; Off ; Off ;
-; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
-; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
-; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
-; Infer RAMs from Raw Logic ; On ; On ;
-; Parallel Synthesis ; On ; On ;
-; DSP Block Balancing ; Auto ; Auto ;
-; NOT Gate Push-Back ; On ; On ;
-; Power-Up Don't Care ; On ; On ;
-; Remove Redundant Logic Cells ; Off ; Off ;
-; Remove Duplicate Registers ; On ; On ;
-; Ignore CARRY Buffers ; Off ; Off ;
-; Ignore CASCADE Buffers ; Off ; Off ;
-; Ignore GLOBAL Buffers ; Off ; Off ;
-; Ignore ROW GLOBAL Buffers ; Off ; Off ;
-; Ignore LCELL Buffers ; Off ; Off ;
-; Ignore SOFT Buffers ; On ; On ;
-; Limit AHDL Integers to 32 Bits ; Off ; Off ;
-; Optimization Technique ; Balanced ; Balanced ;
-; Carry Chain Length ; 70 ; 70 ;
-; Auto Carry Chains ; On ; On ;
-; Auto Open-Drain Pins ; On ; On ;
-; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
-; Auto ROM Replacement ; On ; On ;
-; Auto RAM Replacement ; On ; On ;
-; Auto DSP Block Replacement ; On ; On ;
-; Auto Shift Register Replacement ; Auto ; Auto ;
-; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
-; Auto Clock Enable Replacement ; On ; On ;
-; Strict RAM Replacement ; Off ; Off ;
-; Allow Synchronous Control Signals ; On ; On ;
-; Force Use of Synchronous Clear Signals ; Off ; Off ;
-; Auto RAM Block Balancing ; On ; On ;
-; Auto RAM to Logic Cell Conversion ; Off ; Off ;
-; Auto Resource Sharing ; Off ; Off ;
-; Allow Any RAM Size For Recognition ; Off ; Off ;
-; Allow Any ROM Size For Recognition ; Off ; Off ;
-; Allow Any Shift Register Size For Recognition ; Off ; Off ;
-; Use LogicLock Constraints during Resource Balancing ; On ; On ;
-; Ignore translate_off and synthesis_off directives ; Off ; Off ;
-; Timing-Driven Synthesis ; On ; On ;
-; Report Parameter Settings ; On ; On ;
-; Report Source Assignments ; On ; On ;
-; Report Connectivity Checks ; On ; On ;
-; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
-; Synchronization Register Chain Length ; 2 ; 2 ;
-; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
-; HDL message level ; Level2 ; Level2 ;
-; Suppress Register Optimization Related Messages ; Off ; Off ;
-; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
-; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
-; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
-; Clock MUX Protection ; On ; On ;
-; Auto Gated Clock Conversion ; Off ; Off ;
-; Block Design Naming ; Auto ; Auto ;
-; SDC constraint protection ; Off ; Off ;
-; Synthesis Effort ; Auto ; Auto ;
-; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
-; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
-; Analysis & Synthesis Message Level ; Medium ; Medium ;
-; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
-; Resource Aware Inference For Block RAM ; On ; On ;
-+------------------------------------------------------------------+--------------------+--------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.00 ;
-; Maximum used ; 4 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processor 2 ; 0.0% ;
-; Processors 3-4 ; 0.0% ;
-+----------------------------+-------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read ;
-+----------------------------------+-----------------+------------------------------+----------------------------------------------------+---------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
-+----------------------------------+-----------------+------------------------------+----------------------------------------------------+---------+
-; MySPI.sv ; yes ; User SystemVerilog HDL File ; C:/Users/damie/Documents/Minibot/SPI/MySPI.sv ; ;
-; MyDE0_Nano.sv ; yes ; User SystemVerilog HDL File ; C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv ; ;
-+----------------------------------+-----------------+------------------------------+----------------------------------------------------+---------+
-
-
-+------------------------------------------------------------------+
-; Analysis & Synthesis Resource Usage Summary ;
-+---------------------------------------------+--------------------+
-; Resource ; Usage ;
-+---------------------------------------------+--------------------+
-; Estimated Total logic elements ; 41 ;
-; ; ;
-; Total combinational functions ; 39 ;
-; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 3 ;
-; -- 3 input functions ; 32 ;
-; -- <=2 input functions ; 4 ;
-; ; ;
-; Logic elements by mode ; ;
-; -- normal mode ; 36 ;
-; -- arithmetic mode ; 3 ;
-; ; ;
-; Total registers ; 38 ;
-; -- Dedicated logic registers ; 38 ;
-; -- I/O registers ; 0 ;
-; ; ;
-; I/O pins ; 99 ;
-; ; ;
-; Embedded Multiplier 9-bit elements ; 0 ;
-; ; ;
-; Maximum fan-out node ; GPIO_0_PI[8]~input ;
-; Maximum fan-out ; 38 ;
-; Total fan-out ; 372 ;
-; Average fan-out ; 1.04 ;
-+---------------------------------------------+--------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Utilization by Entity ;
-+-----------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------+-------------+--------------+
-; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
-+-----------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------+-------------+--------------+
-; |MyDE0_Nano ; 39 (0) ; 38 (0) ; 0 ; 0 ; 0 ; 0 ; 99 ; 0 ; |MyDE0_Nano ; MyDE0_Nano ; work ;
-; |spi_slave:spi_slave_instance| ; 39 (39) ; 38 (38) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |MyDE0_Nano|spi_slave:spi_slave_instance ; spi_slave ; work ;
-+-----------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------+-------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+------------------------------------------------------+
-; General Register Statistics ;
-+----------------------------------------------+-------+
-; Statistic ; Value ;
-+----------------------------------------------+-------+
-; Total registers ; 38 ;
-; Number of registers using Synchronous Clear ; 0 ;
-; Number of registers using Synchronous Load ; 0 ;
-; Number of registers using Asynchronous Clear ; 0 ;
-; Number of registers using Asynchronous Load ; 0 ;
-; Number of registers using Clock Enable ; 0 ;
-; Number of registers using Preset ; 0 ;
-+----------------------------------------------+-------+
-
-
-+--------------------------------------------------------------------------------------------------------------------+
-; Port Connectivity Checks: "spi_slave:spi_slave_instance" ;
-+----------+--------+----------+-------------------------------------------------------------------------------------+
-; Port ; Type ; Severity ; Details ;
-+----------+--------+----------+-------------------------------------------------------------------------------------+
-; reset ; Input ; Info ; Explicitly unconnected ;
-; d[31..1] ; Input ; Info ; Stuck at GND ;
-; q ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-+----------+--------+----------+-------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------+
-; Post-Synthesis Netlist Statistics for Top Partition ;
-+-----------------------+-----------------------------+
-; Type ; Count ;
-+-----------------------+-----------------------------+
-; boundary_port ; 99 ;
-; cycloneiii_ff ; 38 ;
-; plain ; 38 ;
-; cycloneiii_io_obuf ; 81 ;
-; cycloneiii_lcell_comb ; 40 ;
-; arith ; 3 ;
-; 2 data inputs ; 2 ;
-; 3 data inputs ; 1 ;
-; normal ; 37 ;
-; 0 data inputs ; 1 ;
-; 1 data inputs ; 2 ;
-; 3 data inputs ; 31 ;
-; 4 data inputs ; 3 ;
-; ; ;
-; Max LUT depth ; 2.00 ;
-; Average LUT depth ; 0.73 ;
-+-----------------------+-----------------------------+
-
-
-+-------------------------------+
-; Elapsed Time Per Partition ;
-+----------------+--------------+
-; Partition Name ; Elapsed Time ;
-+----------------+--------------+
-; Top ; 00:00:00 ;
-+----------------+--------------+
-
-
-+-------------------------------+
-; Analysis & Synthesis Messages ;
-+-------------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Analysis & Synthesis
- Info: Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
- Info: Processing started: Wed Nov 16 16:51:21 2022
-Info: Command: quartus_map --read_settings_files=on --write_settings_files=off SPI_test -c SPI_test
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (12021): Found 1 design units, including 1 entities, in source file mytestbench.sv
- Info (12023): Found entity 1: MyTestbench File: C:/Users/damie/Documents/Minibot/SPI/MyTestbench.sv Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file myspi.sv
- Info (12023): Found entity 1: spi_slave File: C:/Users/damie/Documents/Minibot/SPI/MySPI.sv Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file myde0_nano.sv
- Info (12023): Found entity 1: MyDE0_Nano File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 1
-Info (12127): Elaborating entity "MyDE0_Nano" for the top level hierarchy
-Warning (10036): Verilog HDL or VHDL warning at MyDE0_Nano.sv(47): object "ENC_1B" assigned a value but never read File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 47
-Warning (10036): Verilog HDL or VHDL warning at MyDE0_Nano.sv(47): object "ENC_2A" assigned a value but never read File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 47
-Warning (10036): Verilog HDL or VHDL warning at MyDE0_Nano.sv(47): object "ENC_2B" assigned a value but never read File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 47
-Warning (10034): Output port "LED" at MyDE0_Nano.sv(7) has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 7
-Info (12128): Elaborating entity "spi_slave" for hierarchy "spi_slave:spi_slave_instance" File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 39
-Warning (13039): The following bidirectional pins have no drivers
- Warning (13040): bidirectional pin "GPIO_0_PI[8]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Warning (13040): bidirectional pin "GPIO_0_PI[9]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Warning (13040): bidirectional pin "GPIO_0_PI[10]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Warning (13040): bidirectional pin "GPIO_0_PI[31]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Warning (13040): bidirectional pin "GPIO_2[0]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 13
- Warning (13040): bidirectional pin "GPIO_2[1]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 13
- Warning (13040): bidirectional pin "GPIO_2[2]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 13
- Warning (13040): bidirectional pin "GPIO_2[3]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 13
- Warning (13040): bidirectional pin "GPIO_2[4]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 13
- Warning (13040): bidirectional pin "GPIO_2[5]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 13
- Warning (13040): bidirectional pin "GPIO_2[6]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 13
- Warning (13040): bidirectional pin "GPIO_2[7]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 13
- Warning (13040): bidirectional pin "GPIO_2[8]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 13
- Warning (13040): bidirectional pin "GPIO_2[9]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 13
- Warning (13040): bidirectional pin "GPIO_2[10]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 13
- Warning (13040): bidirectional pin "GPIO_2[11]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 13
- Warning (13040): bidirectional pin "GPIO_2[12]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 13
- Warning (13040): bidirectional pin "GPIO_0_PI[0]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Warning (13040): bidirectional pin "GPIO_0_PI[1]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Warning (13040): bidirectional pin "GPIO_0_PI[2]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Warning (13040): bidirectional pin "GPIO_0_PI[3]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Warning (13040): bidirectional pin "GPIO_0_PI[4]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Warning (13040): bidirectional pin "GPIO_0_PI[5]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Warning (13040): bidirectional pin "GPIO_0_PI[6]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Warning (13040): bidirectional pin "GPIO_0_PI[7]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Warning (13040): bidirectional pin "GPIO_0_PI[12]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Warning (13040): bidirectional pin "GPIO_0_PI[13]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Warning (13040): bidirectional pin "GPIO_0_PI[14]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Warning (13040): bidirectional pin "GPIO_0_PI[15]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Warning (13040): bidirectional pin "GPIO_0_PI[16]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Warning (13040): bidirectional pin "GPIO_0_PI[17]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Warning (13040): bidirectional pin "GPIO_0_PI[18]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Warning (13040): bidirectional pin "GPIO_0_PI[19]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Warning (13040): bidirectional pin "GPIO_0_PI[20]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Warning (13040): bidirectional pin "GPIO_0_PI[21]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Warning (13040): bidirectional pin "GPIO_0_PI[22]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Warning (13040): bidirectional pin "GPIO_0_PI[23]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Warning (13040): bidirectional pin "GPIO_0_PI[24]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Warning (13040): bidirectional pin "GPIO_0_PI[25]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Warning (13040): bidirectional pin "GPIO_0_PI[26]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Warning (13040): bidirectional pin "GPIO_0_PI[27]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Warning (13040): bidirectional pin "GPIO_0_PI[28]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Warning (13040): bidirectional pin "GPIO_0_PI[29]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Warning (13040): bidirectional pin "GPIO_0_PI[30]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Warning (13040): bidirectional pin "GPIO_0_PI[32]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Warning (13040): bidirectional pin "GPIO_0_PI[33]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 17
- Warning (13040): bidirectional pin "GPIO_1[0]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Warning (13040): bidirectional pin "GPIO_1[1]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Warning (13040): bidirectional pin "GPIO_1[2]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Warning (13040): bidirectional pin "GPIO_1[3]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Warning (13040): bidirectional pin "GPIO_1[4]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Warning (13040): bidirectional pin "GPIO_1[5]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Warning (13040): bidirectional pin "GPIO_1[6]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Warning (13040): bidirectional pin "GPIO_1[7]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Warning (13040): bidirectional pin "GPIO_1[8]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Warning (13040): bidirectional pin "GPIO_1[9]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Warning (13040): bidirectional pin "GPIO_1[10]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Warning (13040): bidirectional pin "GPIO_1[11]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Warning (13040): bidirectional pin "GPIO_1[12]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Warning (13040): bidirectional pin "GPIO_1[13]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Warning (13040): bidirectional pin "GPIO_1[14]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Warning (13040): bidirectional pin "GPIO_1[15]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Warning (13040): bidirectional pin "GPIO_1[16]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Warning (13040): bidirectional pin "GPIO_1[17]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Warning (13040): bidirectional pin "GPIO_1[18]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Warning (13040): bidirectional pin "GPIO_1[19]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Warning (13040): bidirectional pin "GPIO_1[20]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Warning (13040): bidirectional pin "GPIO_1[21]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Warning (13040): bidirectional pin "GPIO_1[22]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Warning (13040): bidirectional pin "GPIO_1[23]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Warning (13040): bidirectional pin "GPIO_1[24]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Warning (13040): bidirectional pin "GPIO_1[25]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Warning (13040): bidirectional pin "GPIO_1[26]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Warning (13040): bidirectional pin "GPIO_1[27]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Warning (13040): bidirectional pin "GPIO_1[28]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Warning (13040): bidirectional pin "GPIO_1[29]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Warning (13040): bidirectional pin "GPIO_1[30]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Warning (13040): bidirectional pin "GPIO_1[31]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Warning (13040): bidirectional pin "GPIO_1[32]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
- Warning (13040): bidirectional pin "GPIO_1[33]" has no driver File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 21
-Warning (13024): Output pins are stuck at VCC or GND
- Warning (13410): Pin "LED[0]" is stuck at GND File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 7
- Warning (13410): Pin "LED[1]" is stuck at GND File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 7
- Warning (13410): Pin "LED[2]" is stuck at GND File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 7
- Warning (13410): Pin "LED[3]" is stuck at GND File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 7
- Warning (13410): Pin "LED[4]" is stuck at GND File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 7
- Warning (13410): Pin "LED[5]" is stuck at GND File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 7
- Warning (13410): Pin "LED[6]" is stuck at GND File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 7
- Warning (13410): Pin "LED[7]" is stuck at GND File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 7
-Info (286030): Timing-Driven Synthesis is running
-Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
- Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
-Warning (21074): Design contains 10 input pin(s) that do not drive logic
- Warning (15610): No output dependent on input pin "CLOCK_50" File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 4
- Warning (15610): No output dependent on input pin "KEY[0]" File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 10
- Warning (15610): No output dependent on input pin "KEY[1]" File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 10
- Warning (15610): No output dependent on input pin "GPIO_2_IN[0]" File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 14
- Warning (15610): No output dependent on input pin "GPIO_2_IN[1]" File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 14
- Warning (15610): No output dependent on input pin "GPIO_2_IN[2]" File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 14
- Warning (15610): No output dependent on input pin "GPIO_0_PI_IN[0]" File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 18
- Warning (15610): No output dependent on input pin "GPIO_0_PI_IN[1]" File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 18
- Warning (15610): No output dependent on input pin "GPIO_1_IN[0]" File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 23
- Warning (15610): No output dependent on input pin "GPIO_1_IN[1]" File: C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv Line: 23
-Info (21057): Implemented 140 device resources after synthesis - the final resource count might be different
- Info (21058): Implemented 10 input pins
- Info (21059): Implemented 8 output pins
- Info (21060): Implemented 81 bidirectional pins
- Info (21061): Implemented 41 logic cells
-Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 106 warnings
- Info: Peak virtual memory: 4777 megabytes
- Info: Processing ended: Wed Nov 16 16:51:32 2022
- Info: Elapsed time: 00:00:11
- Info: Total CPU time (on all processors): 00:00:23
-
-
diff --git a/SPI/output_files/SPI_test.map.summary b/SPI/output_files/SPI_test.map.summary
deleted file mode 100644
index fc7cf2d023892e4d2fc8977f2daeadfa130ce6ce..0000000000000000000000000000000000000000
--- a/SPI/output_files/SPI_test.map.summary
+++ /dev/null
@@ -1,14 +0,0 @@
-Analysis & Synthesis Status : Successful - Wed Nov 16 16:51:32 2022
-Quartus Prime Version : 18.1.0 Build 625 09/12/2018 SJ Lite Edition
-Revision Name : SPI_test
-Top-level Entity Name : MyDE0_Nano
-Family : Cyclone IV E
-Total logic elements : 41
- Total combinational functions : 39
- Dedicated logic registers : 38
-Total registers : 38
-Total pins : 99
-Total virtual pins : 0
-Total memory bits : 0
-Embedded Multiplier 9-bit elements : 0
-Total PLLs : 0
diff --git a/SPI/output_files/SPI_test.pin b/SPI/output_files/SPI_test.pin
deleted file mode 100644
index 1c69754b9a3ac2b65f8d8ace4925c1bd892cf0a9..0000000000000000000000000000000000000000
--- a/SPI/output_files/SPI_test.pin
+++ /dev/null
@@ -1,326 +0,0 @@
- -- Copyright (C) 2018 Intel Corporation. All rights reserved.
- -- Your use of Intel Corporation's design tools, logic functions
- -- and other software and tools, and its AMPP partner logic
- -- functions, and any output files from any of the foregoing
- -- (including device programming or simulation files), and any
- -- associated documentation or information are expressly subject
- -- to the terms and conditions of the Intel Program License
- -- Subscription Agreement, the Intel Quartus Prime License Agreement,
- -- the Intel FPGA IP License Agreement, or other applicable license
- -- agreement, including, without limitation, that your use is for
- -- the sole purpose of programming logic devices manufactured by
- -- Intel and sold by Intel or its authorized distributors. Please
- -- refer to the applicable agreement for further details.
- --
- -- This is a Quartus Prime output file. It is for reporting purposes only, and is
- -- not intended for use as a Quartus Prime input file. This file cannot be used
- -- to make Quartus Prime pin assignments - for instructions on how to make pin
- -- assignments, please see Quartus Prime help.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- NC : No Connect. This pin has no internal connection to the device.
- -- DNU : Do Not Use. This pin MUST NOT be connected.
- -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
- -- VCCIO : Dedicated power pin, which MUST be connected to VCC
- -- of its bank.
- -- Bank 1: 2.5V
- -- Bank 2: 2.5V
- -- Bank 3: 2.5V
- -- Bank 4: 2.5V
- -- Bank 5: 2.5V
- -- Bank 6: 2.5V
- -- Bank 7: 2.5V
- -- Bank 8: 2.5V
- -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
- -- It can also be used to report unused dedicated pins. The connection
- -- on the board for unused dedicated pins depends on whether this will
- -- be used in a future design. One example is device migration. When
- -- using device migration, refer to the device pin-tables. If it is a
- -- GND pin in the pin table or if it will not be used in a future design
- -- for another purpose the it MUST be connected to GND. If it is an unused
- -- dedicated pin, then it can be connected to a valid signal on the board
- -- (low, high, or toggling) if that signal is required for a different
- -- revision of the design.
- -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
- -- This pin should be connected to GND. It may also be connected to a
- -- valid signal on the board (low, high, or toggling) if that signal
- -- is required for a different revision of the design.
- -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
- -- or leave it unconnected.
- -- RESERVED : Unused I/O pin, which MUST be left unconnected.
- -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
- -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
- -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
- -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- Pin directions (input, output or bidir) are based on device operating in user mode.
- ---------------------------------------------------------------------------------
-
-Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
-CHIP "SPI_test" ASSIGNED TO AN: EP4CE22F17C6
-
-Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
--------------------------------------------------------------------------------------------------------------
-VCCIO8 : A1 : power : : 2.5V : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A2 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 :
-GPIO_0_PI[5] : A5 : bidir : 2.5 V : : 8 : Y
-GPIO_0_PI[11] : A6 : bidir : 2.5 V : : 8 : Y
-GPIO_0_PI[23] : A7 : bidir : 2.5 V : : 8 : N
-GND+ : A8 : : : : 8 :
-GND+ : A9 : : : : 7 :
-GPIO_0_PI[0] : A10 : bidir : 2.5 V : : 7 : N
-LED[3] : A11 : output : 2.5 V : : 7 : Y
-GPIO_1_IN[0] : A12 : input : 2.5 V : : 7 : N
-LED[1] : A13 : output : 2.5 V : : 7 : Y
-GPIO_0_PI[21] : A14 : bidir : 2.5 V : : 7 : N
-LED[0] : A15 : output : 2.5 V : : 7 : Y
-VCCIO7 : A16 : power : : 2.5V : 7 :
-LED[6] : B1 : output : 2.5 V : : 1 : Y
-GND : B2 : gnd : : : :
-GPIO_2[6] : B3 : bidir : 2.5 V : : 8 : N
-GPIO_1[4] : B4 : bidir : 2.5 V : : 8 : N
-GPIO_1[22] : B5 : bidir : 2.5 V : : 8 : N
-GPIO_0_PI[17] : B6 : bidir : 2.5 V : : 8 : Y
-GPIO_0_PI[30] : B7 : bidir : 2.5 V : : 8 : N
-GND+ : B8 : : : : 8 :
-GND+ : B9 : : : : 7 :
-GPIO_0_PI[15] : B10 : bidir : 2.5 V : : 7 : N
-GPIO_0_PI[29] : B11 : bidir : 2.5 V : : 7 : Y
-GPIO_2[10] : B12 : bidir : 2.5 V : : 7 : N
-LED[2] : B13 : output : 2.5 V : : 7 : Y
-GPIO_0_PI[24] : B14 : bidir : 2.5 V : : 7 : N
-GND : B15 : gnd : : : :
-GPIO_0_PI[33] : B16 : bidir : 2.5 V : : 6 : N
-~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C1 : input : 2.5 V : : 1 : N
-GPIO_1[20] : C2 : bidir : 2.5 V : : 1 : N
-GPIO_0_PI[14] : C3 : bidir : 2.5 V : : 8 : N
-VCCIO8 : C4 : power : : 2.5V : 8 :
-GND : C5 : gnd : : : :
-GPIO_0_PI[3] : C6 : bidir : 2.5 V : : 8 : N
-VCCIO8 : C7 : power : : 2.5V : 8 :
-GPIO_2[11] : C8 : bidir : 2.5 V : : 8 : N
-GPIO_1[32] : C9 : bidir : 2.5 V : : 7 : N
-VCCIO7 : C10 : power : : 2.5V : 7 :
-GPIO_0_PI[28] : C11 : bidir : 2.5 V : : 7 : Y
-GND : C12 : gnd : : : :
-VCCIO7 : C13 : power : : 2.5V : 7 :
-GPIO_0_PI_IN[1] : C14 : input : 2.5 V : : 7 : N
-GPIO_1[15] : C15 : bidir : 2.5 V : : 6 : N
-GPIO_1[19] : C16 : bidir : 2.5 V : : 6 : N
-LED[4] : D1 : output : 2.5 V : : 1 : Y
-~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : input : 2.5 V : : 1 : N
-GPIO_2[7] : D3 : bidir : 2.5 V : : 8 : N
-VCCD_PLL3 : D4 : power : : 1.2V : :
-GPIO_0_PI[9] : D5 : bidir : 2.5 V : : 8 : Y
-GPIO_2_IN[2] : D6 : input : 2.5 V : : 8 : N
-GND : D7 : gnd : : : :
-GPIO_0_PI[32] : D8 : bidir : 2.5 V : : 8 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 7 :
-GND : D10 : gnd : : : :
-GPIO_0_PI[31] : D11 : bidir : 2.5 V : : 7 : Y
-GPIO_2[1] : D12 : bidir : 2.5 V : : 7 : N
-VCCD_PLL2 : D13 : power : : 1.2V : :
-GPIO_1[6] : D14 : bidir : 2.5 V : : 7 : N
-GPIO_1[12] : D15 : bidir : 2.5 V : : 6 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : D16 : : : : 6 :
-KEY[1] : E1 : input : 2.5 V : : 1 : Y
-GND : E2 : gnd : : : :
-VCCIO1 : E3 : power : : 2.5V : 1 :
-GND : E4 : gnd : : : :
-GNDA3 : E5 : gnd : : : :
-GPIO_0_PI_IN[0] : E6 : input : 2.5 V : : 8 : N
-GPIO_0_PI[10] : E7 : bidir : 2.5 V : : 8 : N
-GPIO_2[12] : E8 : bidir : 2.5 V : : 8 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 7 :
-GPIO_0_PI[27] : E10 : bidir : 2.5 V : : 7 : Y
-GPIO_1[11] : E11 : bidir : 2.5 V : : 7 : N
-GNDA2 : E12 : gnd : : : :
-GND : E13 : gnd : : : :
-VCCIO6 : E14 : power : : 2.5V : 6 :
-GPIO_2_IN[1] : E15 : input : 2.5 V : : 6 : N
-GPIO_2_IN[0] : E16 : input : 2.5 V : : 6 : N
-GPIO_1[3] : F1 : bidir : 2.5 V : : 1 : N
-GPIO_2[2] : F2 : bidir : 2.5 V : : 1 : N
-LED[5] : F3 : output : 2.5 V : : 1 : Y
-nSTATUS : F4 : : : : 1 :
-VCCA3 : F5 : power : : 2.5V : :
-GND : F6 : gnd : : : :
-VCCINT : F7 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F8 : : : : 8 :
-GPIO_0_PI[16] : F9 : bidir : 2.5 V : : 7 : N
-GND : F10 : gnd : : : :
-VCCINT : F11 : power : : 1.2V : :
-VCCA2 : F12 : power : : 2.5V : :
-GPIO_1[25] : F13 : bidir : 2.5 V : : 6 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 6 :
-GPIO_1[8] : F15 : bidir : 2.5 V : : 6 : N
-~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : F16 : output : 2.5 V : : 6 : N
-GPIO_1[28] : G1 : bidir : 2.5 V : : 1 : N
-GPIO_0_PI[8] : G2 : bidir : 2.5 V : : 1 : N
-VCCIO1 : G3 : power : : 2.5V : 1 :
-GND : G4 : gnd : : : :
-GPIO_2[3] : G5 : bidir : 2.5 V : : 1 : N
-VCCINT : G6 : power : : 1.2V : :
-VCCINT : G7 : power : : 1.2V : :
-VCCINT : G8 : power : : 1.2V : :
-VCCINT : G9 : power : : 1.2V : :
-VCCINT : G10 : power : : 1.2V : :
-GND : G11 : gnd : : : :
-MSEL2 : G12 : : : : 6 :
-GND : G13 : gnd : : : :
-VCCIO6 : G14 : power : : 2.5V : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 6 :
-GPIO_1[2] : G16 : bidir : 2.5 V : : 6 : N
-~ALTERA_DCLK~ : H1 : output : 2.5 V : : 1 : N
-~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : H2 : input : 2.5 V : : 1 : N
-TCK : H3 : input : : : 1 :
-TDI : H4 : input : : : 1 :
-nCONFIG : H5 : : : : 1 :
-VCCINT : H6 : power : : 1.2V : :
-GND : H7 : gnd : : : :
-GND : H8 : gnd : : : :
-GND : H9 : gnd : : : :
-GND : H10 : gnd : : : :
-VCCINT : H11 : power : : 1.2V : :
-MSEL1 : H12 : : : : 6 :
-MSEL0 : H13 : : : : 6 :
-CONF_DONE : H14 : : : : 6 :
-GND : H15 : gnd : : : :
-GND : H16 : gnd : : : :
-GPIO_0_PI[20] : J1 : bidir : 2.5 V : : 2 : N
-GPIO_2[5] : J2 : bidir : 2.5 V : : 2 : N
-nCE : J3 : : : : 1 :
-TDO : J4 : output : : : 1 :
-TMS : J5 : input : : : 1 :
-VCCINT : J6 : power : : 1.2V : :
-GND : J7 : gnd : : : :
-GND : J8 : gnd : : : :
-GND : J9 : gnd : : : :
-GND : J10 : gnd : : : :
-GND : J11 : gnd : : : :
-VCCINT : J12 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J13 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 5 :
-KEY[0] : J15 : input : 2.5 V : : 5 : Y
-GPIO_1[29] : J16 : bidir : 2.5 V : : 5 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : : : : 2 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 2 :
-VCCIO2 : K3 : power : : 2.5V : 2 :
-GND : K4 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K5 : : : : 2 :
-GND : K6 : gnd : : : :
-VCCINT : K7 : power : : 1.2V : :
-GND : K8 : gnd : : : :
-VCCINT : K9 : power : : 1.2V : :
-VCCINT : K10 : power : : 1.2V : :
-VCCINT : K11 : power : : 1.2V : :
-GND : K12 : gnd : : : :
-GND : K13 : gnd : : : :
-VCCIO5 : K14 : power : : 2.5V : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K15 : : : : 5 :
-GPIO_1[14] : K16 : bidir : 2.5 V : : 5 : N
-GPIO_1[10] : L1 : bidir : 2.5 V : : 2 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : L2 : : : : 2 :
-LED[7] : L3 : output : 2.5 V : : 2 : Y
-GPIO_1[33] : L4 : bidir : 2.5 V : : 2 : N
-VCCA1 : L5 : power : : 2.5V : :
-VCCINT : L6 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L7 : : : : 3 :
-GPIO_0_PI[26] : L8 : bidir : 2.5 V : : 3 : N
-GND : L9 : gnd : : : :
-GND : L10 : gnd : : : :
-GND : L11 : gnd : : : :
-VCCA4 : L12 : power : : 2.5V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L13 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L14 : : : : 5 :
-GPIO_1[5] : L15 : bidir : 2.5 V : : 5 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : L16 : : : : 5 :
-GND+ : M1 : : : : 2 :
-GND+ : M2 : : : : 2 :
-VCCIO2 : M3 : power : : 2.5V : 2 :
-GND : M4 : gnd : : : :
-GNDA1 : M5 : gnd : : : :
-GPIO_1[27] : M6 : bidir : 2.5 V : : 3 : N
-GPIO_2[8] : M7 : bidir : 2.5 V : : 3 : N
-GPIO_1[23] : M8 : bidir : 2.5 V : : 3 : N
-VCCINT : M9 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M10 : : : : 4 :
-VCCINT : M11 : power : : 1.2V : :
-GNDA4 : M12 : gnd : : : :
-GND : M13 : gnd : : : :
-VCCIO5 : M14 : power : : 2.5V : 5 :
-GND+ : M15 : : : : 5 :
-GND+ : M16 : : : : 5 :
-GPIO_1[18] : N1 : bidir : 2.5 V : : 2 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : N2 : : : : 2 :
-GPIO_1[1] : N3 : bidir : 2.5 V : : 3 : N
-VCCD_PLL1 : N4 : power : : 1.2V : :
-GPIO_1[7] : N5 : bidir : 2.5 V : : 3 : N
-GPIO_1[24] : N6 : bidir : 2.5 V : : 3 : N
-GND : N7 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N9 : : : : 4 :
-GND : N10 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N11 : : : : 4 :
-GPIO_1[21] : N12 : bidir : 2.5 V : : 4 : N
-VCCD_PLL4 : N13 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N14 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N15 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N16 : : : : 5 :
-GPIO_0_PI[12] : P1 : bidir : 2.5 V : : 2 : N
-GPIO_0_PI[1] : P2 : bidir : 2.5 V : : 2 : N
-GPIO_1[26] : P3 : bidir : 2.5 V : : 3 : N
-VCCIO3 : P4 : power : : 2.5V : 3 :
-GND : P5 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P6 : : : : 3 :
-VCCIO3 : P7 : power : : 2.5V : 3 :
-GPIO_1[16] : P8 : bidir : 2.5 V : : 3 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : P9 : : : : 4 :
-VCCIO4 : P10 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P11 : : : : 4 :
-GND : P12 : gnd : : : :
-VCCIO4 : P13 : power : : 2.5V : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P14 : : : : 4 :
-GPIO_0_PI[6] : P15 : bidir : 2.5 V : : 5 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : P16 : : : : 5 :
-GPIO_0_PI[2] : R1 : bidir : 2.5 V : : 2 : N
-GND : R2 : gnd : : : :
-GPIO_0_PI[18] : R3 : bidir : 2.5 V : : 3 : N
-GPIO_2[0] : R4 : bidir : 2.5 V : : 3 : N
-GPIO_0_PI[7] : R5 : bidir : 2.5 V : : 3 : N
-GPIO_0_PI[22] : R6 : bidir : 2.5 V : : 3 : N
-CLOCK_50 : R7 : input : 2.5 V : : 3 : Y
-GND+ : R8 : : : : 3 :
-GND+ : R9 : : : : 4 :
-GPIO_1[17] : R10 : bidir : 2.5 V : : 4 : N
-GPIO_1[9] : R11 : bidir : 2.5 V : : 4 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : R12 : : : : 4 :
-GPIO_0_PI[25] : R13 : bidir : 2.5 V : : 4 : N
-GPIO_1[31] : R14 : bidir : 2.5 V : : 4 : N
-GND : R15 : gnd : : : :
-GPIO_0_PI[13] : R16 : bidir : 2.5 V : : 5 : N
-VCCIO3 : T1 : power : : 2.5V : 3 :
-GPIO_2[9] : T2 : bidir : 2.5 V : : 3 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 3 :
-GPIO_2[4] : T4 : bidir : 2.5 V : : 3 : N
-GPIO_0_PI[4] : T5 : bidir : 2.5 V : : 3 : N
-GPIO_1[0] : T6 : bidir : 2.5 V : : 3 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : T7 : : : : 3 :
-GND+ : T8 : : : : 3 :
-GND+ : T9 : : : : 4 :
-GPIO_1_IN[1] : T10 : input : 2.5 V : : 4 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : T11 : : : : 4 :
-GPIO_0_PI[19] : T12 : bidir : 2.5 V : : 4 : N
-GPIO_1[13] : T13 : bidir : 2.5 V : : 4 : N
-GPIO_1[30] : T14 : bidir : 2.5 V : : 4 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : T15 : : : : 4 :
-VCCIO4 : T16 : power : : 2.5V : 4 :
diff --git a/SPI/output_files/SPI_test.sld b/SPI/output_files/SPI_test.sld
deleted file mode 100644
index f7d3ed7cc6abd95c50005b31855c0eec845cbeed..0000000000000000000000000000000000000000
--- a/SPI/output_files/SPI_test.sld
+++ /dev/null
@@ -1 +0,0 @@
-<sld_project_info/>
diff --git a/SPI/output_files/SPI_test.sof b/SPI/output_files/SPI_test.sof
deleted file mode 100644
index b05e24c65fa7ede42a70f9111692f0d31cbd60a8..0000000000000000000000000000000000000000
Binary files a/SPI/output_files/SPI_test.sof and /dev/null differ
diff --git a/SPI/output_files/SPI_test.sta.rpt b/SPI/output_files/SPI_test.sta.rpt
deleted file mode 100644
index d4dc82ebfbe88afc420ef7acac6897b77dc265ca..0000000000000000000000000000000000000000
--- a/SPI/output_files/SPI_test.sta.rpt
+++ /dev/null
@@ -1,1617 +0,0 @@
-Timing Analyzer report for SPI_test
-Wed Nov 16 16:51:46 2022
-Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Timing Analyzer Summary
- 3. Parallel Compilation
- 4. Clocks
- 5. Slow 1200mV 85C Model Fmax Summary
- 6. Timing Closure Recommendations
- 7. Slow 1200mV 85C Model Setup Summary
- 8. Slow 1200mV 85C Model Hold Summary
- 9. Slow 1200mV 85C Model Recovery Summary
- 10. Slow 1200mV 85C Model Removal Summary
- 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
- 12. Slow 1200mV 85C Model Setup: 'GPIO_0_PI[8]'
- 13. Slow 1200mV 85C Model Hold: 'GPIO_0_PI[8]'
- 14. Slow 1200mV 85C Model Metastability Summary
- 15. Slow 1200mV 0C Model Fmax Summary
- 16. Slow 1200mV 0C Model Setup Summary
- 17. Slow 1200mV 0C Model Hold Summary
- 18. Slow 1200mV 0C Model Recovery Summary
- 19. Slow 1200mV 0C Model Removal Summary
- 20. Slow 1200mV 0C Model Minimum Pulse Width Summary
- 21. Slow 1200mV 0C Model Setup: 'GPIO_0_PI[8]'
- 22. Slow 1200mV 0C Model Hold: 'GPIO_0_PI[8]'
- 23. Slow 1200mV 0C Model Metastability Summary
- 24. Fast 1200mV 0C Model Setup Summary
- 25. Fast 1200mV 0C Model Hold Summary
- 26. Fast 1200mV 0C Model Recovery Summary
- 27. Fast 1200mV 0C Model Removal Summary
- 28. Fast 1200mV 0C Model Minimum Pulse Width Summary
- 29. Fast 1200mV 0C Model Setup: 'GPIO_0_PI[8]'
- 30. Fast 1200mV 0C Model Hold: 'GPIO_0_PI[8]'
- 31. Fast 1200mV 0C Model Metastability Summary
- 32. Multicorner Timing Analysis Summary
- 33. Board Trace Model Assignments
- 34. Input Transition Times
- 35. Signal Integrity Metrics (Slow 1200mv 0c Model)
- 36. Signal Integrity Metrics (Slow 1200mv 85c Model)
- 37. Signal Integrity Metrics (Fast 1200mv 0c Model)
- 38. Setup Transfers
- 39. Hold Transfers
- 40. Report TCCS
- 41. Report RSKM
- 42. Unconstrained Paths Summary
- 43. Clock Status Summary
- 44. Unconstrained Input Ports
- 45. Unconstrained Output Ports
- 46. Unconstrained Input Ports
- 47. Unconstrained Output Ports
- 48. Timing Analyzer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2018 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors. Please
-refer to the applicable agreement for further details.
-
-
-
-+-----------------------------------------------------------------------------+
-; Timing Analyzer Summary ;
-+-----------------------+-----------------------------------------------------+
-; Quartus Prime Version ; Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition ;
-; Timing Analyzer ; Legacy Timing Analyzer ;
-; Revision Name ; SPI_test ;
-; Device Family ; Cyclone IV E ;
-; Device Name ; EP4CE22F17C6 ;
-; Timing Models ; Final ;
-; Delay Model ; Combined ;
-; Rise/Fall Delays ; Enabled ;
-+-----------------------+-----------------------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.01 ;
-; Maximum used ; 4 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processor 2 ; 0.4% ;
-; Processors 3-4 ; 0.3% ;
-+----------------------------+-------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clocks ;
-+--------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+------------------+
-; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
-+--------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+------------------+
-; GPIO_0_PI[8] ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { GPIO_0_PI[8] } ;
-+--------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------+
-; Slow 1200mV 85C Model Fmax Summary ;
-+------------+-----------------+--------------+---------------------------------------------------------------+
-; Fmax ; Restricted Fmax ; Clock Name ; Note ;
-+------------+-----------------+--------------+---------------------------------------------------------------+
-; 273.67 MHz ; 250.0 MHz ; GPIO_0_PI[8] ; limit due to minimum period restriction (max I/O toggle rate) ;
-+------------+-----------------+--------------+---------------------------------------------------------------+
-This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
-
-
-----------------------------------
-; Timing Closure Recommendations ;
-----------------------------------
-HTML report is unavailable in plain text report export.
-
-
-+---------------------------------------+
-; Slow 1200mV 85C Model Setup Summary ;
-+--------------+--------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+--------------+--------+---------------+
-; GPIO_0_PI[8] ; -1.327 ; -40.855 ;
-+--------------+--------+---------------+
-
-
-+--------------------------------------+
-; Slow 1200mV 85C Model Hold Summary ;
-+--------------+-------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+--------------+-------+---------------+
-; GPIO_0_PI[8] ; 0.360 ; 0.000 ;
-+--------------+-------+---------------+
-
-
-------------------------------------------
-; Slow 1200mV 85C Model Recovery Summary ;
-------------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Slow 1200mV 85C Model Removal Summary ;
------------------------------------------
-No paths to report.
-
-
-+---------------------------------------------------+
-; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
-+--------------+--------+---------------------------+
-; Clock ; Slack ; End Point TNS ;
-+--------------+--------+---------------------------+
-; GPIO_0_PI[8] ; -3.000 ; -41.000 ;
-+--------------+--------+---------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Slow 1200mV 85C Model Setup: 'GPIO_0_PI[8]' ;
-+--------+-------------------------------------+------------------------------------+--------------+--------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+--------+-------------------------------------+------------------------------------+--------------+--------------+--------------+------------+------------+
-; -1.327 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[24] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.591 ;
-; -1.325 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[20] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.589 ;
-; -1.325 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[23] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.589 ;
-; -1.325 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[25] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.589 ;
-; -1.324 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[19] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.588 ;
-; -1.324 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[22] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.588 ;
-; -1.324 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[27] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.588 ;
-; -1.322 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[28] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.586 ;
-; -1.322 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[30] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.586 ;
-; -1.321 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[31] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.585 ;
-; -1.320 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[26] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.584 ;
-; -1.320 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[24] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.584 ;
-; -1.319 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[29] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.583 ;
-; -1.318 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[20] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.582 ;
-; -1.318 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[23] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.582 ;
-; -1.318 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[25] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.582 ;
-; -1.317 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[19] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.581 ;
-; -1.317 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[22] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.581 ;
-; -1.317 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[27] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.581 ;
-; -1.315 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[28] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.579 ;
-; -1.315 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[30] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.579 ;
-; -1.314 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[31] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.578 ;
-; -1.313 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[26] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.577 ;
-; -1.312 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[29] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.576 ;
-; -1.269 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[7] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.230 ; 1.534 ;
-; -1.269 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[4] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.230 ; 1.534 ;
-; -1.269 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[3] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.230 ; 1.534 ;
-; -1.268 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[6] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.230 ; 1.533 ;
-; -1.266 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[2] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.230 ; 1.531 ;
-; -1.265 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[1] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.230 ; 1.530 ;
-; -1.264 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[13] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.230 ; 1.529 ;
-; -1.264 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[5] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.230 ; 1.529 ;
-; -1.262 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[7] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.230 ; 1.527 ;
-; -1.262 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[4] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.230 ; 1.527 ;
-; -1.262 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[3] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.230 ; 1.527 ;
-; -1.261 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[6] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.230 ; 1.526 ;
-; -1.259 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[2] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.230 ; 1.524 ;
-; -1.258 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[1] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.230 ; 1.523 ;
-; -1.257 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[13] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.230 ; 1.522 ;
-; -1.257 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[5] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.230 ; 1.522 ;
-; -1.206 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[21] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.470 ;
-; -1.196 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[21] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.460 ;
-; -1.148 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[24] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.412 ;
-; -1.146 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[20] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.410 ;
-; -1.146 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[23] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.410 ;
-; -1.146 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[25] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.410 ;
-; -1.145 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[19] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.409 ;
-; -1.145 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[22] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.409 ;
-; -1.145 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[27] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.409 ;
-; -1.143 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[28] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.407 ;
-; -1.143 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[30] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.407 ;
-; -1.142 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[31] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.406 ;
-; -1.141 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[26] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.405 ;
-; -1.140 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[16] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.230 ; 1.405 ;
-; -1.140 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[14] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.230 ; 1.405 ;
-; -1.140 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[8] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.230 ; 1.405 ;
-; -1.140 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[15] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.230 ; 1.405 ;
-; -1.140 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[17] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.230 ; 1.405 ;
-; -1.140 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[29] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.404 ;
-; -1.139 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[18] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.230 ; 1.404 ;
-; -1.139 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[11] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.230 ; 1.404 ;
-; -1.139 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[10] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.230 ; 1.404 ;
-; -1.138 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[9] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.230 ; 1.403 ;
-; -1.138 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[12] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.230 ; 1.403 ;
-; -1.133 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[16] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.230 ; 1.398 ;
-; -1.133 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[14] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.230 ; 1.398 ;
-; -1.133 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[8] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.230 ; 1.398 ;
-; -1.133 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[15] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.230 ; 1.398 ;
-; -1.133 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[17] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.230 ; 1.398 ;
-; -1.132 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[18] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.230 ; 1.397 ;
-; -1.132 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[11] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.230 ; 1.397 ;
-; -1.132 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[10] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.230 ; 1.397 ;
-; -1.131 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[9] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.230 ; 1.396 ;
-; -1.131 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[12] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.230 ; 1.396 ;
-; -1.090 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[7] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.230 ; 1.355 ;
-; -1.090 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[4] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.230 ; 1.355 ;
-; -1.090 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[3] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.230 ; 1.355 ;
-; -1.089 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[6] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.230 ; 1.354 ;
-; -1.087 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[2] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.230 ; 1.352 ;
-; -1.086 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[1] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.230 ; 1.351 ;
-; -1.085 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[13] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.230 ; 1.350 ;
-; -1.085 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[5] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.230 ; 1.350 ;
-; -1.061 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[24] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.325 ;
-; -1.059 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[20] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.323 ;
-; -1.059 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[23] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.323 ;
-; -1.059 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[25] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.323 ;
-; -1.058 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[19] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.322 ;
-; -1.058 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[22] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.322 ;
-; -1.058 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[27] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.322 ;
-; -1.056 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[28] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.320 ;
-; -1.056 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[30] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.320 ;
-; -1.055 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[31] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.319 ;
-; -1.054 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[26] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.318 ;
-; -1.053 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[29] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.317 ;
-; -1.003 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[7] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.230 ; 1.268 ;
-; -1.003 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[4] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.230 ; 1.268 ;
-; -1.003 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[3] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.230 ; 1.268 ;
-; -1.002 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[6] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.230 ; 1.267 ;
-; -1.000 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[2] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.230 ; 1.265 ;
-; -0.999 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[19] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.231 ; 1.263 ;
-+--------+-------------------------------------+------------------------------------+--------------+--------------+--------------+------------+------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Slow 1200mV 85C Model Hold: 'GPIO_0_PI[8]' ;
-+-------+-------------------------------------+---------------------------------------+--------------+--------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+-------+-------------------------------------+---------------------------------------+--------------+--------------+--------------+------------+------------+
-; 0.360 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|cnt[0] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.063 ; 0.580 ;
-; 0.478 ; spi_slave:spi_slave_instance|q[1] ; spi_slave:spi_slave_instance|q[2] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.062 ; 0.697 ;
-; 0.479 ; spi_slave:spi_slave_instance|q[10] ; spi_slave:spi_slave_instance|q[11] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.061 ; 0.697 ;
-; 0.479 ; spi_slave:spi_slave_instance|q[4] ; spi_slave:spi_slave_instance|q[5] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.062 ; 0.698 ;
-; 0.480 ; spi_slave:spi_slave_instance|q[3] ; spi_slave:spi_slave_instance|q[4] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.062 ; 0.699 ;
-; 0.480 ; spi_slave:spi_slave_instance|q[0] ; spi_slave:spi_slave_instance|q[1] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.062 ; 0.699 ;
-; 0.481 ; spi_slave:spi_slave_instance|q[17] ; spi_slave:spi_slave_instance|q[18] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.061 ; 0.699 ;
-; 0.553 ; spi_slave:spi_slave_instance|q[25] ; spi_slave:spi_slave_instance|q[26] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.061 ; 0.771 ;
-; 0.553 ; spi_slave:spi_slave_instance|q[23] ; spi_slave:spi_slave_instance|q[24] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.061 ; 0.771 ;
-; 0.553 ; spi_slave:spi_slave_instance|q[22] ; spi_slave:spi_slave_instance|q[23] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.061 ; 0.771 ;
-; 0.553 ; spi_slave:spi_slave_instance|q[2] ; spi_slave:spi_slave_instance|q[3] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.062 ; 0.772 ;
-; 0.554 ; spi_slave:spi_slave_instance|q[5] ; spi_slave:spi_slave_instance|q[6] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.062 ; 0.773 ;
-; 0.555 ; spi_slave:spi_slave_instance|q[21] ; spi_slave:spi_slave_instance|q[22] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.061 ; 0.773 ;
-; 0.556 ; spi_slave:spi_slave_instance|q[20] ; spi_slave:spi_slave_instance|q[21] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.061 ; 0.774 ;
-; 0.556 ; spi_slave:spi_slave_instance|q[11] ; spi_slave:spi_slave_instance|q[12] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.061 ; 0.774 ;
-; 0.556 ; spi_slave:spi_slave_instance|q[9] ; spi_slave:spi_slave_instance|q[10] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.061 ; 0.774 ;
-; 0.556 ; spi_slave:spi_slave_instance|q[6] ; spi_slave:spi_slave_instance|q[7] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.062 ; 0.775 ;
-; 0.557 ; spi_slave:spi_slave_instance|q[30] ; spi_slave:spi_slave_instance|q[31] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.061 ; 0.775 ;
-; 0.557 ; spi_slave:spi_slave_instance|q[29] ; spi_slave:spi_slave_instance|q[30] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.061 ; 0.775 ;
-; 0.557 ; spi_slave:spi_slave_instance|q[28] ; spi_slave:spi_slave_instance|q[29] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.061 ; 0.775 ;
-; 0.557 ; spi_slave:spi_slave_instance|q[27] ; spi_slave:spi_slave_instance|q[28] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.061 ; 0.775 ;
-; 0.557 ; spi_slave:spi_slave_instance|q[26] ; spi_slave:spi_slave_instance|q[27] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.061 ; 0.775 ;
-; 0.557 ; spi_slave:spi_slave_instance|q[16] ; spi_slave:spi_slave_instance|q[17] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.061 ; 0.775 ;
-; 0.558 ; spi_slave:spi_slave_instance|q[19] ; spi_slave:spi_slave_instance|q[20] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.061 ; 0.776 ;
-; 0.558 ; spi_slave:spi_slave_instance|q[14] ; spi_slave:spi_slave_instance|q[15] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.061 ; 0.776 ;
-; 0.558 ; spi_slave:spi_slave_instance|q[8] ; spi_slave:spi_slave_instance|q[9] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.061 ; 0.776 ;
-; 0.559 ; spi_slave:spi_slave_instance|q[24] ; spi_slave:spi_slave_instance|q[25] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.061 ; 0.777 ;
-; 0.576 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|cnt[3] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.063 ; 0.796 ;
-; 0.588 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|cnt[1] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.063 ; 0.808 ;
-; 0.592 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|cnt[1] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.063 ; 0.812 ;
-; 0.617 ; spi_slave:spi_slave_instance|q[13] ; spi_slave:spi_slave_instance|q[14] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.061 ; 0.835 ;
-; 0.618 ; spi_slave:spi_slave_instance|q[7] ; spi_slave:spi_slave_instance|q[8] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.061 ; 0.836 ;
-; 0.620 ; spi_slave:spi_slave_instance|q[15] ; spi_slave:spi_slave_instance|q[16] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.061 ; 0.838 ;
-; 0.636 ; spi_slave:spi_slave_instance|q[12] ; spi_slave:spi_slave_instance|q[13] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.062 ; 0.855 ;
-; 0.653 ; spi_slave:spi_slave_instance|q[18] ; spi_slave:spi_slave_instance|q[19] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.060 ; 0.870 ;
-; 0.670 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|cnt[4] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.063 ; 0.890 ;
-; 0.711 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|cnt[2] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.063 ; 0.931 ;
-; 0.830 ; spi_slave:spi_slave_instance|q[31] ; spi_slave:spi_slave_instance|qdelayed ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; 0.230 ; 0.737 ;
-; 0.864 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|cnt[4] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.063 ; 1.084 ;
-; 0.866 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|cnt[2] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.063 ; 1.086 ;
-; 0.866 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|cnt[2] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.063 ; 1.086 ;
-; 0.868 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|cnt[3] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.063 ; 1.088 ;
-; 0.868 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|cnt[3] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.063 ; 1.088 ;
-; 0.978 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|cnt[4] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.063 ; 1.198 ;
-; 0.978 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|cnt[4] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.063 ; 1.198 ;
-; 0.985 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|cnt[3] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.063 ; 1.205 ;
-; 1.095 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|cnt[4] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.063 ; 1.315 ;
-; 1.234 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[15] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.104 ; 0.807 ;
-; 1.238 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[17] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.104 ; 0.811 ;
-; 1.240 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[9] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.104 ; 0.813 ;
-; 1.240 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[12] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.104 ; 0.813 ;
-; 1.241 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[10] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.104 ; 0.814 ;
-; 1.312 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[18] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.104 ; 0.885 ;
-; 1.314 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[21] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.105 ; 0.886 ;
-; 1.318 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[14] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.104 ; 0.891 ;
-; 1.320 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[11] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.104 ; 0.893 ;
-; 1.321 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[8] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.104 ; 0.894 ;
-; 1.325 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[16] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.104 ; 0.898 ;
-; 1.413 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[20] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.105 ; 0.985 ;
-; 1.415 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[23] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.105 ; 0.987 ;
-; 1.416 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[24] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.105 ; 0.988 ;
-; 1.418 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[22] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.105 ; 0.990 ;
-; 1.420 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[27] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.105 ; 0.992 ;
-; 1.423 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[4] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.103 ; 0.997 ;
-; 1.424 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[7] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.103 ; 0.998 ;
-; 1.424 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[31] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.105 ; 0.996 ;
-; 1.425 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[30] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.105 ; 0.997 ;
-; 1.427 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[25] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.105 ; 0.999 ;
-; 1.427 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[28] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.105 ; 0.999 ;
-; 1.427 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[29] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.105 ; 0.999 ;
-; 1.428 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[26] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.105 ; 1.000 ;
-; 1.433 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[5] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.103 ; 1.007 ;
-; 1.433 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[2] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.103 ; 1.007 ;
-; 1.434 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[13] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.103 ; 1.008 ;
-; 1.434 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[6] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.103 ; 1.008 ;
-; 1.435 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[3] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.103 ; 1.009 ;
-; 1.446 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[1] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.103 ; 1.020 ;
-; 1.452 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[21] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.105 ; 1.024 ;
-; 1.472 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[12] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.104 ; 1.045 ;
-; 1.472 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[11] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.104 ; 1.045 ;
-; 1.473 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[17] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.104 ; 1.046 ;
-; 1.473 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[9] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.104 ; 1.046 ;
-; 1.473 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[10] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.104 ; 1.046 ;
-; 1.473 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[21] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.105 ; 1.045 ;
-; 1.475 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[18] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.104 ; 1.048 ;
-; 1.475 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[8] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.104 ; 1.048 ;
-; 1.475 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[16] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.104 ; 1.048 ;
-; 1.477 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[15] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.104 ; 1.050 ;
-; 1.478 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[14] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.104 ; 1.051 ;
-; 1.515 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[19] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.105 ; 1.087 ;
-; 1.560 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[1] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.103 ; 1.134 ;
-; 1.567 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[12] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.104 ; 1.140 ;
-; 1.567 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[11] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.104 ; 1.140 ;
-; 1.568 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[17] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.104 ; 1.141 ;
-; 1.568 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[9] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.104 ; 1.141 ;
-; 1.568 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[10] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.104 ; 1.141 ;
-; 1.570 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[5] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.103 ; 1.144 ;
-; 1.570 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[2] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.103 ; 1.144 ;
-; 1.570 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[6] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.103 ; 1.144 ;
-; 1.570 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[18] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.104 ; 1.143 ;
-+-------+-------------------------------------+---------------------------------------+--------------+--------------+--------------+------------+------------+
-
-
------------------------------------------------
-; Slow 1200mV 85C Model Metastability Summary ;
------------------------------------------------
-No synchronizer chains to report.
-
-
-+-------------------------------------------------------------------------------------------------------------+
-; Slow 1200mV 0C Model Fmax Summary ;
-+------------+-----------------+--------------+---------------------------------------------------------------+
-; Fmax ; Restricted Fmax ; Clock Name ; Note ;
-+------------+-----------------+--------------+---------------------------------------------------------------+
-; 304.69 MHz ; 250.0 MHz ; GPIO_0_PI[8] ; limit due to minimum period restriction (max I/O toggle rate) ;
-+------------+-----------------+--------------+---------------------------------------------------------------+
-This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
-
-
-+---------------------------------------+
-; Slow 1200mV 0C Model Setup Summary ;
-+--------------+--------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+--------------+--------+---------------+
-; GPIO_0_PI[8] ; -1.141 ; -34.310 ;
-+--------------+--------+---------------+
-
-
-+--------------------------------------+
-; Slow 1200mV 0C Model Hold Summary ;
-+--------------+-------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+--------------+-------+---------------+
-; GPIO_0_PI[8] ; 0.320 ; 0.000 ;
-+--------------+-------+---------------+
-
-
------------------------------------------
-; Slow 1200mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Slow 1200mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-+--------------------------------------------------+
-; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
-+--------------+--------+--------------------------+
-; Clock ; Slack ; End Point TNS ;
-+--------------+--------+--------------------------+
-; GPIO_0_PI[8] ; -3.000 ; -41.000 ;
-+--------------+--------+--------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Slow 1200mV 0C Model Setup: 'GPIO_0_PI[8]' ;
-+--------+-------------------------------------+------------------------------------+--------------+--------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+--------+-------------------------------------+------------------------------------+--------------+--------------+--------------+------------+------------+
-; -1.141 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[20] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.441 ;
-; -1.141 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[23] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.441 ;
-; -1.139 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[22] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.439 ;
-; -1.139 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[24] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.439 ;
-; -1.138 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[27] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.438 ;
-; -1.136 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[19] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.436 ;
-; -1.136 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[25] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.436 ;
-; -1.134 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[30] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.434 ;
-; -1.134 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[20] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.434 ;
-; -1.134 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[23] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.434 ;
-; -1.133 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[28] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.433 ;
-; -1.133 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[31] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.433 ;
-; -1.132 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[26] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.432 ;
-; -1.132 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[29] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.432 ;
-; -1.132 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[22] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.432 ;
-; -1.132 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[24] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.432 ;
-; -1.131 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[27] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.431 ;
-; -1.129 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[19] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.429 ;
-; -1.129 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[25] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.429 ;
-; -1.127 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[30] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.427 ;
-; -1.126 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[28] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.426 ;
-; -1.126 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[31] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.426 ;
-; -1.125 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[26] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.425 ;
-; -1.125 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[29] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.425 ;
-; -1.078 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[7] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.193 ; 1.380 ;
-; -1.078 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[4] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.193 ; 1.380 ;
-; -1.078 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[3] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.193 ; 1.380 ;
-; -1.077 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[6] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.193 ; 1.379 ;
-; -1.077 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[1] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.193 ; 1.379 ;
-; -1.076 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[2] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.193 ; 1.378 ;
-; -1.074 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[13] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.193 ; 1.376 ;
-; -1.074 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[5] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.193 ; 1.376 ;
-; -1.071 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[7] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.193 ; 1.373 ;
-; -1.071 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[4] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.193 ; 1.373 ;
-; -1.071 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[3] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.193 ; 1.373 ;
-; -1.070 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[6] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.193 ; 1.372 ;
-; -1.070 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[1] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.193 ; 1.372 ;
-; -1.069 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[2] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.193 ; 1.371 ;
-; -1.067 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[13] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.193 ; 1.369 ;
-; -1.067 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[5] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.193 ; 1.369 ;
-; -0.998 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[21] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.298 ;
-; -0.991 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[21] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.291 ;
-; -0.989 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[20] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.289 ;
-; -0.989 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[23] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.289 ;
-; -0.987 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[22] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.287 ;
-; -0.987 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[24] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.287 ;
-; -0.986 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[27] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.286 ;
-; -0.984 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[19] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.284 ;
-; -0.984 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[25] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.284 ;
-; -0.982 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[30] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.282 ;
-; -0.981 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[28] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.281 ;
-; -0.981 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[31] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.281 ;
-; -0.980 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[26] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.280 ;
-; -0.980 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[29] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.280 ;
-; -0.956 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[16] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.194 ; 1.257 ;
-; -0.955 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[14] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.194 ; 1.256 ;
-; -0.955 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[8] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.194 ; 1.256 ;
-; -0.955 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[15] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.194 ; 1.256 ;
-; -0.955 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[17] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.194 ; 1.256 ;
-; -0.954 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[18] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.194 ; 1.255 ;
-; -0.954 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[11] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.194 ; 1.255 ;
-; -0.954 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[9] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.194 ; 1.255 ;
-; -0.954 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[10] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.194 ; 1.255 ;
-; -0.953 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[12] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.194 ; 1.254 ;
-; -0.949 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[16] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.194 ; 1.250 ;
-; -0.948 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[14] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.194 ; 1.249 ;
-; -0.948 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[8] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.194 ; 1.249 ;
-; -0.948 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[15] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.194 ; 1.249 ;
-; -0.948 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[17] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.194 ; 1.249 ;
-; -0.947 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[18] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.194 ; 1.248 ;
-; -0.947 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[11] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.194 ; 1.248 ;
-; -0.947 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[9] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.194 ; 1.248 ;
-; -0.947 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[10] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.194 ; 1.248 ;
-; -0.946 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[12] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.194 ; 1.247 ;
-; -0.926 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[7] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.193 ; 1.228 ;
-; -0.926 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[4] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.193 ; 1.228 ;
-; -0.926 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[3] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.193 ; 1.228 ;
-; -0.925 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[6] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.193 ; 1.227 ;
-; -0.925 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[1] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.193 ; 1.227 ;
-; -0.924 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[2] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.193 ; 1.226 ;
-; -0.922 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[13] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.193 ; 1.224 ;
-; -0.922 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[5] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.193 ; 1.224 ;
-; -0.908 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[20] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.208 ;
-; -0.908 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[23] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.208 ;
-; -0.906 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[22] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.206 ;
-; -0.906 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[24] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.206 ;
-; -0.905 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[27] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.205 ;
-; -0.903 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[19] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.203 ;
-; -0.903 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[25] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.203 ;
-; -0.901 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[30] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.201 ;
-; -0.900 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[28] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.200 ;
-; -0.900 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[31] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.200 ;
-; -0.899 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[26] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.199 ;
-; -0.899 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[29] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.195 ; 1.199 ;
-; -0.845 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[7] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.193 ; 1.147 ;
-; -0.845 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[4] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.193 ; 1.147 ;
-; -0.845 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[3] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.193 ; 1.147 ;
-; -0.844 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[6] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.193 ; 1.146 ;
-; -0.844 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[1] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.193 ; 1.146 ;
-; -0.843 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[2] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.193 ; 1.145 ;
-+--------+-------------------------------------+------------------------------------+--------------+--------------+--------------+------------+------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Slow 1200mV 0C Model Hold: 'GPIO_0_PI[8]' ;
-+-------+-------------------------------------+---------------------------------------+--------------+--------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+-------+-------------------------------------+---------------------------------------+--------------+--------------+--------------+------------+------------+
-; 0.320 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|cnt[0] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.055 ; 0.519 ;
-; 0.431 ; spi_slave:spi_slave_instance|q[10] ; spi_slave:spi_slave_instance|q[11] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.055 ; 0.630 ;
-; 0.432 ; spi_slave:spi_slave_instance|q[1] ; spi_slave:spi_slave_instance|q[2] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.054 ; 0.630 ;
-; 0.433 ; spi_slave:spi_slave_instance|q[17] ; spi_slave:spi_slave_instance|q[18] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.055 ; 0.632 ;
-; 0.434 ; spi_slave:spi_slave_instance|q[4] ; spi_slave:spi_slave_instance|q[5] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.054 ; 0.632 ;
-; 0.434 ; spi_slave:spi_slave_instance|q[3] ; spi_slave:spi_slave_instance|q[4] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.054 ; 0.632 ;
-; 0.434 ; spi_slave:spi_slave_instance|q[0] ; spi_slave:spi_slave_instance|q[1] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.054 ; 0.632 ;
-; 0.496 ; spi_slave:spi_slave_instance|q[23] ; spi_slave:spi_slave_instance|q[24] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.054 ; 0.694 ;
-; 0.497 ; spi_slave:spi_slave_instance|q[25] ; spi_slave:spi_slave_instance|q[26] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.054 ; 0.695 ;
-; 0.497 ; spi_slave:spi_slave_instance|q[22] ; spi_slave:spi_slave_instance|q[23] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.054 ; 0.695 ;
-; 0.498 ; spi_slave:spi_slave_instance|q[2] ; spi_slave:spi_slave_instance|q[3] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.054 ; 0.696 ;
-; 0.499 ; spi_slave:spi_slave_instance|q[21] ; spi_slave:spi_slave_instance|q[22] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.054 ; 0.697 ;
-; 0.499 ; spi_slave:spi_slave_instance|q[11] ; spi_slave:spi_slave_instance|q[12] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.055 ; 0.698 ;
-; 0.499 ; spi_slave:spi_slave_instance|q[9] ; spi_slave:spi_slave_instance|q[10] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.055 ; 0.698 ;
-; 0.499 ; spi_slave:spi_slave_instance|q[5] ; spi_slave:spi_slave_instance|q[6] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.054 ; 0.697 ;
-; 0.500 ; spi_slave:spi_slave_instance|q[16] ; spi_slave:spi_slave_instance|q[17] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.055 ; 0.699 ;
-; 0.501 ; spi_slave:spi_slave_instance|q[30] ; spi_slave:spi_slave_instance|q[31] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.054 ; 0.699 ;
-; 0.501 ; spi_slave:spi_slave_instance|q[29] ; spi_slave:spi_slave_instance|q[30] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.054 ; 0.699 ;
-; 0.501 ; spi_slave:spi_slave_instance|q[20] ; spi_slave:spi_slave_instance|q[21] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.054 ; 0.699 ;
-; 0.501 ; spi_slave:spi_slave_instance|q[14] ; spi_slave:spi_slave_instance|q[15] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.055 ; 0.700 ;
-; 0.501 ; spi_slave:spi_slave_instance|q[8] ; spi_slave:spi_slave_instance|q[9] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.055 ; 0.700 ;
-; 0.501 ; spi_slave:spi_slave_instance|q[6] ; spi_slave:spi_slave_instance|q[7] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.054 ; 0.699 ;
-; 0.502 ; spi_slave:spi_slave_instance|q[28] ; spi_slave:spi_slave_instance|q[29] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.054 ; 0.700 ;
-; 0.502 ; spi_slave:spi_slave_instance|q[27] ; spi_slave:spi_slave_instance|q[28] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.054 ; 0.700 ;
-; 0.502 ; spi_slave:spi_slave_instance|q[26] ; spi_slave:spi_slave_instance|q[27] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.054 ; 0.700 ;
-; 0.503 ; spi_slave:spi_slave_instance|q[24] ; spi_slave:spi_slave_instance|q[25] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.054 ; 0.701 ;
-; 0.503 ; spi_slave:spi_slave_instance|q[19] ; spi_slave:spi_slave_instance|q[20] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.054 ; 0.701 ;
-; 0.519 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|cnt[3] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.055 ; 0.718 ;
-; 0.530 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|cnt[1] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.055 ; 0.729 ;
-; 0.534 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|cnt[1] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.055 ; 0.733 ;
-; 0.566 ; spi_slave:spi_slave_instance|q[15] ; spi_slave:spi_slave_instance|q[16] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.055 ; 0.765 ;
-; 0.566 ; spi_slave:spi_slave_instance|q[13] ; spi_slave:spi_slave_instance|q[14] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.054 ; 0.764 ;
-; 0.566 ; spi_slave:spi_slave_instance|q[7] ; spi_slave:spi_slave_instance|q[8] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.054 ; 0.764 ;
-; 0.583 ; spi_slave:spi_slave_instance|q[12] ; spi_slave:spi_slave_instance|q[13] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.055 ; 0.782 ;
-; 0.592 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|cnt[4] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.055 ; 0.791 ;
-; 0.600 ; spi_slave:spi_slave_instance|q[18] ; spi_slave:spi_slave_instance|q[19] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.053 ; 0.797 ;
-; 0.647 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|cnt[2] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.055 ; 0.846 ;
-; 0.768 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|cnt[4] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.055 ; 0.967 ;
-; 0.769 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|cnt[2] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.055 ; 0.968 ;
-; 0.769 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|cnt[2] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.055 ; 0.968 ;
-; 0.776 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|cnt[3] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.055 ; 0.975 ;
-; 0.776 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|cnt[3] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.055 ; 0.975 ;
-; 0.808 ; spi_slave:spi_slave_instance|q[31] ; spi_slave:spi_slave_instance|qdelayed ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; 0.194 ; 0.666 ;
-; 0.865 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|cnt[4] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.055 ; 1.064 ;
-; 0.865 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|cnt[4] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.055 ; 1.064 ;
-; 0.892 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|cnt[3] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.055 ; 1.091 ;
-; 0.981 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|cnt[4] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.055 ; 1.180 ;
-; 1.137 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[15] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.084 ; 0.717 ;
-; 1.141 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[17] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.084 ; 0.721 ;
-; 1.144 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[9] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.084 ; 0.724 ;
-; 1.144 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[10] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.084 ; 0.724 ;
-; 1.144 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[12] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.084 ; 0.724 ;
-; 1.208 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[18] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.084 ; 0.788 ;
-; 1.215 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[14] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.084 ; 0.795 ;
-; 1.215 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[8] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.084 ; 0.795 ;
-; 1.216 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[11] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.084 ; 0.796 ;
-; 1.217 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[16] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.084 ; 0.797 ;
-; 1.237 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[21] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.086 ; 0.815 ;
-; 1.308 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[20] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.086 ; 0.886 ;
-; 1.309 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[23] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.086 ; 0.887 ;
-; 1.310 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[24] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.086 ; 0.888 ;
-; 1.312 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[22] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.086 ; 0.890 ;
-; 1.314 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[27] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.086 ; 0.892 ;
-; 1.317 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[31] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.086 ; 0.895 ;
-; 1.318 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[30] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.086 ; 0.896 ;
-; 1.319 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[28] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.086 ; 0.897 ;
-; 1.320 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[25] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.086 ; 0.898 ;
-; 1.320 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[29] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.086 ; 0.898 ;
-; 1.321 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[26] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.086 ; 0.899 ;
-; 1.328 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[7] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.084 ; 0.908 ;
-; 1.328 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[4] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.084 ; 0.908 ;
-; 1.335 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[5] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.084 ; 0.915 ;
-; 1.336 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[13] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.084 ; 0.916 ;
-; 1.336 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[2] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.084 ; 0.916 ;
-; 1.337 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[6] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.084 ; 0.917 ;
-; 1.338 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[3] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.084 ; 0.918 ;
-; 1.350 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[1] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.084 ; 0.930 ;
-; 1.358 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[21] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.086 ; 0.936 ;
-; 1.361 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[9] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.084 ; 0.941 ;
-; 1.361 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[12] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.084 ; 0.941 ;
-; 1.361 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[11] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.084 ; 0.941 ;
-; 1.362 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[17] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.084 ; 0.942 ;
-; 1.362 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[10] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.084 ; 0.942 ;
-; 1.363 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[18] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.084 ; 0.943 ;
-; 1.363 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[8] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.084 ; 0.943 ;
-; 1.363 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[16] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.084 ; 0.943 ;
-; 1.366 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[15] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.084 ; 0.946 ;
-; 1.366 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[14] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.084 ; 0.946 ;
-; 1.383 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[21] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.086 ; 0.961 ;
-; 1.395 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[19] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.086 ; 0.973 ;
-; 1.438 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[1] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.084 ; 1.018 ;
-; 1.445 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[9] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.084 ; 1.025 ;
-; 1.445 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[12] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.084 ; 1.025 ;
-; 1.445 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[11] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.084 ; 1.025 ;
-; 1.446 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[17] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.084 ; 1.026 ;
-; 1.446 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[10] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.084 ; 1.026 ;
-; 1.447 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[18] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.084 ; 1.027 ;
-; 1.447 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[8] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.084 ; 1.027 ;
-; 1.447 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[16] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.084 ; 1.027 ;
-; 1.450 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[15] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.084 ; 1.030 ;
-+-------+-------------------------------------+---------------------------------------+--------------+--------------+--------------+------------+------------+
-
-
-----------------------------------------------
-; Slow 1200mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
-+---------------------------------------+
-; Fast 1200mV 0C Model Setup Summary ;
-+--------------+--------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+--------------+--------+---------------+
-; GPIO_0_PI[8] ; -0.818 ; -23.965 ;
-+--------------+--------+---------------+
-
-
-+--------------------------------------+
-; Fast 1200mV 0C Model Hold Summary ;
-+--------------+-------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+--------------+-------+---------------+
-; GPIO_0_PI[8] ; 0.192 ; 0.000 ;
-+--------------+-------+---------------+
-
-
------------------------------------------
-; Fast 1200mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Fast 1200mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-+--------------------------------------------------+
-; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
-+--------------+--------+--------------------------+
-; Clock ; Slack ; End Point TNS ;
-+--------------+--------+--------------------------+
-; GPIO_0_PI[8] ; -3.000 ; -43.505 ;
-+--------------+--------+--------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fast 1200mV 0C Model Setup: 'GPIO_0_PI[8]' ;
-+--------+-------------------------------------+------------------------------------+--------------+--------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+--------+-------------------------------------+------------------------------------+--------------+--------------+--------------+------------+------------+
-; -0.818 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[20] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.874 ;
-; -0.818 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[23] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.874 ;
-; -0.818 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[24] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.874 ;
-; -0.817 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[22] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.873 ;
-; -0.817 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[27] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.873 ;
-; -0.817 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[28] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.873 ;
-; -0.816 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[26] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.872 ;
-; -0.816 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[29] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.872 ;
-; -0.816 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[30] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.872 ;
-; -0.816 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[31] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.872 ;
-; -0.815 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[19] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.871 ;
-; -0.815 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[25] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.871 ;
-; -0.813 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[20] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.869 ;
-; -0.813 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[23] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.869 ;
-; -0.813 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[24] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.869 ;
-; -0.812 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[22] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.868 ;
-; -0.812 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[27] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.868 ;
-; -0.812 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[28] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.868 ;
-; -0.811 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[26] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.867 ;
-; -0.811 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[29] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.867 ;
-; -0.811 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[30] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.867 ;
-; -0.811 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[31] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.867 ;
-; -0.810 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[19] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.866 ;
-; -0.810 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[25] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.866 ;
-; -0.779 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[13] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.430 ; 0.836 ;
-; -0.779 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[7] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.430 ; 0.836 ;
-; -0.779 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[5] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.430 ; 0.836 ;
-; -0.779 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[4] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.430 ; 0.836 ;
-; -0.779 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[2] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.430 ; 0.836 ;
-; -0.779 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[1] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.430 ; 0.836 ;
-; -0.778 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[6] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.430 ; 0.835 ;
-; -0.778 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[3] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.430 ; 0.835 ;
-; -0.775 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[21] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.831 ;
-; -0.774 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[13] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.430 ; 0.831 ;
-; -0.774 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[7] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.430 ; 0.831 ;
-; -0.774 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[5] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.430 ; 0.831 ;
-; -0.774 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[4] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.430 ; 0.831 ;
-; -0.774 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[2] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.430 ; 0.831 ;
-; -0.774 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[1] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.430 ; 0.831 ;
-; -0.773 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[6] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.430 ; 0.830 ;
-; -0.773 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[3] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.430 ; 0.830 ;
-; -0.751 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[21] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.807 ;
-; -0.718 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[18] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.430 ; 0.775 ;
-; -0.717 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[10] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.430 ; 0.774 ;
-; -0.716 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[16] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.430 ; 0.773 ;
-; -0.716 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[11] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.430 ; 0.773 ;
-; -0.716 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[9] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.430 ; 0.773 ;
-; -0.716 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[12] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.430 ; 0.773 ;
-; -0.716 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[15] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.430 ; 0.773 ;
-; -0.716 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[17] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.430 ; 0.773 ;
-; -0.716 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[24] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.772 ;
-; -0.715 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[14] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.430 ; 0.772 ;
-; -0.715 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[8] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.430 ; 0.772 ;
-; -0.715 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[20] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.771 ;
-; -0.715 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[23] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.771 ;
-; -0.714 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[22] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.770 ;
-; -0.714 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[27] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.770 ;
-; -0.713 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[26] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.769 ;
-; -0.713 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[28] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.769 ;
-; -0.713 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[29] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.769 ;
-; -0.713 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[31] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.769 ;
-; -0.713 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[18] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.430 ; 0.770 ;
-; -0.712 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[19] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.768 ;
-; -0.712 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[25] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.768 ;
-; -0.712 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[30] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.768 ;
-; -0.712 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[10] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.430 ; 0.769 ;
-; -0.711 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[16] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.430 ; 0.768 ;
-; -0.711 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[11] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.430 ; 0.768 ;
-; -0.711 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[9] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.430 ; 0.768 ;
-; -0.711 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[12] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.430 ; 0.768 ;
-; -0.711 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[15] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.430 ; 0.768 ;
-; -0.711 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[17] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.430 ; 0.768 ;
-; -0.710 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[14] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.430 ; 0.767 ;
-; -0.710 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|q[8] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.430 ; 0.767 ;
-; -0.673 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[19] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.729 ;
-; -0.670 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[13] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.430 ; 0.727 ;
-; -0.670 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[7] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.430 ; 0.727 ;
-; -0.670 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[5] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.430 ; 0.727 ;
-; -0.670 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[4] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.430 ; 0.727 ;
-; -0.670 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[2] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.430 ; 0.727 ;
-; -0.670 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[1] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.430 ; 0.727 ;
-; -0.669 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[6] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.430 ; 0.726 ;
-; -0.669 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[3] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.430 ; 0.726 ;
-; -0.665 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[20] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.721 ;
-; -0.665 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[23] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.721 ;
-; -0.665 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[24] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.721 ;
-; -0.664 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[22] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.720 ;
-; -0.664 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[27] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.720 ;
-; -0.664 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[28] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.720 ;
-; -0.663 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[26] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.719 ;
-; -0.663 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[29] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.719 ;
-; -0.663 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[30] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.719 ;
-; -0.663 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[31] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.719 ;
-; -0.662 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[19] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.718 ;
-; -0.662 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[25] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.431 ; 0.718 ;
-; -0.626 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[13] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.430 ; 0.683 ;
-; -0.626 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[7] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.430 ; 0.683 ;
-; -0.626 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[5] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.430 ; 0.683 ;
-; -0.626 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[4] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.430 ; 0.683 ;
-; -0.626 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[2] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.500 ; -0.430 ; 0.683 ;
-+--------+-------------------------------------+------------------------------------+--------------+--------------+--------------+------------+------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fast 1200mV 0C Model Hold: 'GPIO_0_PI[8]' ;
-+-------+-------------------------------------+---------------------------------------+--------------+--------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+-------+-------------------------------------+---------------------------------------+--------------+--------------+--------------+------------+------------+
-; 0.192 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|cnt[0] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.038 ; 0.314 ;
-; 0.252 ; spi_slave:spi_slave_instance|q[1] ; spi_slave:spi_slave_instance|q[2] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.037 ; 0.373 ;
-; 0.253 ; spi_slave:spi_slave_instance|q[10] ; spi_slave:spi_slave_instance|q[11] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.036 ; 0.373 ;
-; 0.253 ; spi_slave:spi_slave_instance|q[4] ; spi_slave:spi_slave_instance|q[5] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.037 ; 0.374 ;
-; 0.254 ; spi_slave:spi_slave_instance|q[3] ; spi_slave:spi_slave_instance|q[4] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.037 ; 0.375 ;
-; 0.254 ; spi_slave:spi_slave_instance|q[0] ; spi_slave:spi_slave_instance|q[1] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.037 ; 0.375 ;
-; 0.255 ; spi_slave:spi_slave_instance|q[17] ; spi_slave:spi_slave_instance|q[18] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.036 ; 0.375 ;
-; 0.294 ; spi_slave:spi_slave_instance|q[25] ; spi_slave:spi_slave_instance|q[26] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.037 ; 0.415 ;
-; 0.294 ; spi_slave:spi_slave_instance|q[23] ; spi_slave:spi_slave_instance|q[24] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.037 ; 0.415 ;
-; 0.294 ; spi_slave:spi_slave_instance|q[22] ; spi_slave:spi_slave_instance|q[23] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.037 ; 0.415 ;
-; 0.294 ; spi_slave:spi_slave_instance|q[2] ; spi_slave:spi_slave_instance|q[3] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.037 ; 0.415 ;
-; 0.295 ; spi_slave:spi_slave_instance|q[30] ; spi_slave:spi_slave_instance|q[31] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.037 ; 0.416 ;
-; 0.295 ; spi_slave:spi_slave_instance|q[28] ; spi_slave:spi_slave_instance|q[29] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.037 ; 0.416 ;
-; 0.295 ; spi_slave:spi_slave_instance|q[27] ; spi_slave:spi_slave_instance|q[28] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.037 ; 0.416 ;
-; 0.295 ; spi_slave:spi_slave_instance|q[21] ; spi_slave:spi_slave_instance|q[22] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.037 ; 0.416 ;
-; 0.295 ; spi_slave:spi_slave_instance|q[9] ; spi_slave:spi_slave_instance|q[10] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.036 ; 0.415 ;
-; 0.295 ; spi_slave:spi_slave_instance|q[5] ; spi_slave:spi_slave_instance|q[6] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.037 ; 0.416 ;
-; 0.296 ; spi_slave:spi_slave_instance|q[29] ; spi_slave:spi_slave_instance|q[30] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.037 ; 0.417 ;
-; 0.296 ; spi_slave:spi_slave_instance|q[26] ; spi_slave:spi_slave_instance|q[27] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.037 ; 0.417 ;
-; 0.296 ; spi_slave:spi_slave_instance|q[20] ; spi_slave:spi_slave_instance|q[21] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.037 ; 0.417 ;
-; 0.296 ; spi_slave:spi_slave_instance|q[16] ; spi_slave:spi_slave_instance|q[17] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.036 ; 0.416 ;
-; 0.296 ; spi_slave:spi_slave_instance|q[11] ; spi_slave:spi_slave_instance|q[12] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.036 ; 0.416 ;
-; 0.296 ; spi_slave:spi_slave_instance|q[6] ; spi_slave:spi_slave_instance|q[7] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.037 ; 0.417 ;
-; 0.297 ; spi_slave:spi_slave_instance|q[19] ; spi_slave:spi_slave_instance|q[20] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.037 ; 0.418 ;
-; 0.297 ; spi_slave:spi_slave_instance|q[14] ; spi_slave:spi_slave_instance|q[15] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.036 ; 0.417 ;
-; 0.298 ; spi_slave:spi_slave_instance|q[24] ; spi_slave:spi_slave_instance|q[25] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.037 ; 0.419 ;
-; 0.298 ; spi_slave:spi_slave_instance|q[8] ; spi_slave:spi_slave_instance|q[9] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.036 ; 0.418 ;
-; 0.308 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|cnt[3] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.038 ; 0.430 ;
-; 0.314 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|cnt[1] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.038 ; 0.436 ;
-; 0.315 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|cnt[1] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.038 ; 0.437 ;
-; 0.321 ; spi_slave:spi_slave_instance|q[13] ; spi_slave:spi_slave_instance|q[14] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.036 ; 0.441 ;
-; 0.322 ; spi_slave:spi_slave_instance|q[15] ; spi_slave:spi_slave_instance|q[16] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.036 ; 0.442 ;
-; 0.322 ; spi_slave:spi_slave_instance|q[7] ; spi_slave:spi_slave_instance|q[8] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.036 ; 0.442 ;
-; 0.328 ; spi_slave:spi_slave_instance|q[12] ; spi_slave:spi_slave_instance|q[13] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.037 ; 0.449 ;
-; 0.338 ; spi_slave:spi_slave_instance|q[18] ; spi_slave:spi_slave_instance|q[19] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.036 ; 0.458 ;
-; 0.355 ; spi_slave:spi_slave_instance|q[31] ; spi_slave:spi_slave_instance|qdelayed ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; 0.430 ; 0.389 ;
-; 0.362 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|cnt[4] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.038 ; 0.484 ;
-; 0.375 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|cnt[2] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.038 ; 0.497 ;
-; 0.466 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|cnt[4] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.038 ; 0.588 ;
-; 0.467 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|cnt[2] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.038 ; 0.589 ;
-; 0.467 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|cnt[2] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.038 ; 0.589 ;
-; 0.470 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|cnt[3] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.038 ; 0.592 ;
-; 0.470 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|cnt[3] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.038 ; 0.592 ;
-; 0.524 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|cnt[3] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.038 ; 0.646 ;
-; 0.533 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|cnt[4] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.038 ; 0.655 ;
-; 0.533 ; spi_slave:spi_slave_instance|cnt[1] ; spi_slave:spi_slave_instance|cnt[4] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.038 ; 0.655 ;
-; 0.587 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|cnt[4] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 0.000 ; 0.038 ; 0.709 ;
-; 1.189 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[15] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.355 ; 0.438 ;
-; 1.194 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[17] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.355 ; 0.443 ;
-; 1.195 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[12] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.355 ; 0.444 ;
-; 1.196 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[9] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.355 ; 0.445 ;
-; 1.196 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[10] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.355 ; 0.445 ;
-; 1.218 ; spi_slave:spi_slave_instance|cnt[0] ; spi_slave:spi_slave_instance|q[21] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.355 ; 0.467 ;
-; 1.234 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[18] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.355 ; 0.483 ;
-; 1.237 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[8] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.355 ; 0.486 ;
-; 1.239 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[14] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.355 ; 0.488 ;
-; 1.240 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[16] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.355 ; 0.489 ;
-; 1.242 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[11] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.355 ; 0.491 ;
-; 1.290 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[23] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.355 ; 0.539 ;
-; 1.290 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[24] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.355 ; 0.539 ;
-; 1.291 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[7] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.354 ; 0.541 ;
-; 1.291 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[20] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.355 ; 0.540 ;
-; 1.292 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[4] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.354 ; 0.542 ;
-; 1.292 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[22] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.355 ; 0.541 ;
-; 1.293 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[27] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.355 ; 0.542 ;
-; 1.294 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[28] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.355 ; 0.543 ;
-; 1.295 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[5] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.354 ; 0.545 ;
-; 1.295 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[26] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.355 ; 0.544 ;
-; 1.295 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[29] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.355 ; 0.544 ;
-; 1.296 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[13] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.354 ; 0.546 ;
-; 1.296 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[30] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.355 ; 0.545 ;
-; 1.296 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[31] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.355 ; 0.545 ;
-; 1.297 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[6] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.354 ; 0.547 ;
-; 1.297 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[2] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.354 ; 0.547 ;
-; 1.298 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[3] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.354 ; 0.548 ;
-; 1.298 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[25] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.355 ; 0.547 ;
-; 1.298 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[21] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.355 ; 0.547 ;
-; 1.299 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[21] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.355 ; 0.548 ;
-; 1.303 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[1] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.354 ; 0.553 ;
-; 1.325 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[17] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.355 ; 0.574 ;
-; 1.325 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[16] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.355 ; 0.574 ;
-; 1.325 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[11] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.355 ; 0.574 ;
-; 1.326 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[12] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.355 ; 0.575 ;
-; 1.326 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[9] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.355 ; 0.575 ;
-; 1.326 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[8] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.355 ; 0.575 ;
-; 1.326 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[14] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.355 ; 0.575 ;
-; 1.327 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[15] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.355 ; 0.576 ;
-; 1.327 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[10] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.355 ; 0.576 ;
-; 1.328 ; spi_slave:spi_slave_instance|cnt[3] ; spi_slave:spi_slave_instance|q[18] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.355 ; 0.577 ;
-; 1.349 ; spi_slave:spi_slave_instance|cnt[4] ; spi_slave:spi_slave_instance|q[19] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.355 ; 0.598 ;
-; 1.375 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[17] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.355 ; 0.624 ;
-; 1.375 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[16] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.355 ; 0.624 ;
-; 1.375 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[11] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.355 ; 0.624 ;
-; 1.376 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[12] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.355 ; 0.625 ;
-; 1.376 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[9] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.355 ; 0.625 ;
-; 1.376 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[8] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.355 ; 0.625 ;
-; 1.376 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[14] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.355 ; 0.625 ;
-; 1.377 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[15] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.355 ; 0.626 ;
-; 1.377 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[10] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.355 ; 0.626 ;
-; 1.378 ; spi_slave:spi_slave_instance|cnt[2] ; spi_slave:spi_slave_instance|q[18] ; GPIO_0_PI[8] ; GPIO_0_PI[8] ; -0.500 ; -0.355 ; 0.627 ;
-+-------+-------------------------------------+---------------------------------------+--------------+--------------+--------------+------------+------------+
-
-
-----------------------------------------------
-; Fast 1200mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
-+-------------------------------------------------------------------------------+
-; Multicorner Timing Analysis Summary ;
-+------------------+---------+-------+----------+---------+---------------------+
-; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
-+------------------+---------+-------+----------+---------+---------------------+
-; Worst-case Slack ; -1.327 ; 0.192 ; N/A ; N/A ; -3.000 ;
-; GPIO_0_PI[8] ; -1.327 ; 0.192 ; N/A ; N/A ; -3.000 ;
-; Design-wide TNS ; -40.855 ; 0.0 ; 0.0 ; 0.0 ; -43.505 ;
-; GPIO_0_PI[8] ; -40.855 ; 0.000 ; N/A ; N/A ; -43.505 ;
-+------------------+---------+-------+----------+---------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Board Trace Model Assignments ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; LED[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LED[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LED[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LED[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LED[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LED[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LED[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LED[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_2[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_2[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_2[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_2[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_2[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_2[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_2[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_2[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_2[8] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_2[9] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_2[10] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_2[11] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_2[12] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_0_PI[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_0_PI[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_0_PI[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_0_PI[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_0_PI[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_0_PI[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_0_PI[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_0_PI[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_0_PI[12] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_0_PI[13] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_0_PI[14] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_0_PI[15] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_0_PI[16] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_0_PI[17] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_0_PI[18] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_0_PI[19] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_0_PI[20] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_0_PI[21] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_0_PI[22] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_0_PI[23] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_0_PI[24] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_0_PI[25] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_0_PI[26] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_0_PI[27] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_0_PI[28] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_0_PI[29] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_0_PI[30] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_0_PI[32] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_0_PI[33] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_1[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_1[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_1[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_1[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_1[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_1[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_1[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_1[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_1[8] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_1[9] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_1[10] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_1[11] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_1[12] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_1[13] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_1[14] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_1[15] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_1[16] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_1[17] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_1[18] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_1[19] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_1[20] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_1[21] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_1[22] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_1[23] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_1[24] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_1[25] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_1[26] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_1[27] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_1[28] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_1[29] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_1[30] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_1[31] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_1[32] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_1[33] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_0_PI[8] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_0_PI[9] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_0_PI[10] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_0_PI[11] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; GPIO_0_PI[31] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-
-
-+----------------------------------------------------------------------------+
-; Input Transition Times ;
-+-------------------------+--------------+-----------------+-----------------+
-; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
-+-------------------------+--------------+-----------------+-----------------+
-; CLOCK_50 ; 2.5 V ; 2000 ps ; 2000 ps ;
-; KEY[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; KEY[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_2_IN[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_2_IN[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_2_IN[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_0_PI_IN[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_0_PI_IN[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_1_IN[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_1_IN[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_2[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_2[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_2[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_2[3] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_2[4] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_2[5] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_2[6] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_2[7] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_2[8] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_2[9] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_2[10] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_2[11] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_2[12] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_0_PI[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_0_PI[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_0_PI[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_0_PI[3] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_0_PI[4] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_0_PI[5] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_0_PI[6] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_0_PI[7] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_0_PI[12] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_0_PI[13] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_0_PI[14] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_0_PI[15] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_0_PI[16] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_0_PI[17] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_0_PI[18] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_0_PI[19] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_0_PI[20] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_0_PI[21] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_0_PI[22] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_0_PI[23] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_0_PI[24] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_0_PI[25] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_0_PI[26] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_0_PI[27] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_0_PI[28] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_0_PI[29] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_0_PI[30] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_0_PI[32] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_0_PI[33] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_1[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_1[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_1[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_1[3] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_1[4] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_1[5] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_1[6] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_1[7] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_1[8] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_1[9] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_1[10] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_1[11] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_1[12] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_1[13] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_1[14] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_1[15] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_1[16] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_1[17] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_1[18] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_1[19] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_1[20] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_1[21] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_1[22] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_1[23] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_1[24] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_1[25] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_1[26] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_1[27] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_1[28] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_1[29] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_1[30] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_1[31] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_1[32] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_1[33] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_0_PI[8] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_0_PI[9] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_0_PI[10] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_0_PI[11] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; GPIO_0_PI[31] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ~ALTERA_ASDO_DATA1~ ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V ; 2000 ps ; 2000 ps ;
-; ~ALTERA_DATA0~ ; 2.5 V ; 2000 ps ; 2000 ps ;
-+-------------------------+--------------+-----------------+-----------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1200mv 0c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; LED[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; LED[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; LED[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; LED[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; LED[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ;
-; LED[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.33 V ; -0.00624 V ; 0.185 V ; 0.097 V ; 2.82e-09 s ; 2.56e-09 s ; No ; Yes ; 2.32 V ; 4.44e-09 V ; 2.33 V ; -0.00624 V ; 0.185 V ; 0.097 V ; 2.82e-09 s ; 2.56e-09 s ; No ; Yes ;
-; LED[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.39 V ; -0.0265 V ; 0.2 V ; 0.033 V ; 2.94e-10 s ; 3.12e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.39 V ; -0.0265 V ; 0.2 V ; 0.033 V ; 2.94e-10 s ; 3.12e-10 s ; Yes ; Yes ;
-; LED[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.33 V ; -0.00624 V ; 0.185 V ; 0.097 V ; 2.82e-09 s ; 2.56e-09 s ; No ; Yes ; 2.32 V ; 4.44e-09 V ; 2.33 V ; -0.00624 V ; 0.185 V ; 0.097 V ; 2.82e-09 s ; 2.56e-09 s ; No ; Yes ;
-; GPIO_2[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_2[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_2[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ;
-; GPIO_2[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.39 V ; -0.0265 V ; 0.2 V ; 0.033 V ; 2.94e-10 s ; 3.12e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.39 V ; -0.0265 V ; 0.2 V ; 0.033 V ; 2.94e-10 s ; 3.12e-10 s ; Yes ; Yes ;
-; GPIO_2[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_2[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ;
-; GPIO_2[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_2[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_2[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_2[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_2[10] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_2[11] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_2[12] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.39 V ; -0.0265 V ; 0.2 V ; 0.033 V ; 2.94e-10 s ; 3.12e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.39 V ; -0.0265 V ; 0.2 V ; 0.033 V ; 2.94e-10 s ; 3.12e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.33 V ; -0.00616 V ; 0.191 V ; 0.099 V ; 2.83e-09 s ; 2.56e-09 s ; No ; Yes ; 2.32 V ; 5.95e-09 V ; 2.33 V ; -0.00616 V ; 0.191 V ; 0.099 V ; 2.83e-09 s ; 2.56e-09 s ; No ; Yes ;
-; GPIO_0_PI[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.39 V ; -0.0265 V ; 0.2 V ; 0.033 V ; 2.94e-10 s ; 3.12e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.39 V ; -0.0265 V ; 0.2 V ; 0.033 V ; 2.94e-10 s ; 3.12e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[12] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[13] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[14] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[15] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[16] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[17] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[18] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[19] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[20] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[21] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[22] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[23] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[24] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[25] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[26] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[27] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[28] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.33 V ; -0.00616 V ; 0.191 V ; 0.099 V ; 2.83e-09 s ; 2.56e-09 s ; No ; Yes ; 2.32 V ; 5.95e-09 V ; 2.33 V ; -0.00616 V ; 0.191 V ; 0.099 V ; 2.83e-09 s ; 2.56e-09 s ; No ; Yes ;
-; GPIO_0_PI[29] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[30] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[32] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[33] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.39 V ; -0.0265 V ; 0.2 V ; 0.033 V ; 2.94e-10 s ; 3.12e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.39 V ; -0.0265 V ; 0.2 V ; 0.033 V ; 2.94e-10 s ; 3.12e-10 s ; Yes ; Yes ;
-; GPIO_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ;
-; GPIO_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ;
-; GPIO_1[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_1[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ;
-; GPIO_1[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_1[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_1[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ;
-; GPIO_1[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_1[10] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ;
-; GPIO_1[11] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_1[12] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.39 V ; -0.0265 V ; 0.2 V ; 0.033 V ; 2.94e-10 s ; 3.12e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.39 V ; -0.0265 V ; 0.2 V ; 0.033 V ; 2.94e-10 s ; 3.12e-10 s ; Yes ; Yes ;
-; GPIO_1[13] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_1[14] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ;
-; GPIO_1[15] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ;
-; GPIO_1[16] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_1[17] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_1[18] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ;
-; GPIO_1[19] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ;
-; GPIO_1[20] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ;
-; GPIO_1[21] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_1[22] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_1[23] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_1[24] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_1[25] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.39 V ; -0.0265 V ; 0.2 V ; 0.033 V ; 2.94e-10 s ; 3.12e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.39 V ; -0.0265 V ; 0.2 V ; 0.033 V ; 2.94e-10 s ; 3.12e-10 s ; Yes ; Yes ;
-; GPIO_1[26] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_1[27] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_1[28] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ;
-; GPIO_1[29] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ;
-; GPIO_1[30] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_1[31] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_1[32] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_1[33] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.39 V ; -0.0265 V ; 0.2 V ; 0.033 V ; 2.94e-10 s ; 3.12e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.39 V ; -0.0265 V ; 0.2 V ; 0.033 V ; 2.94e-10 s ; 3.12e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[10] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[11] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[31] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.45e-09 V ; 2.38 V ; -0.0609 V ; 0.148 V ; 0.095 V ; 2.82e-10 s ; 2.59e-10 s ; Yes ; Yes ; 2.32 V ; 3.45e-09 V ; 2.38 V ; -0.0609 V ; 0.148 V ; 0.095 V ; 2.82e-10 s ; 2.59e-10 s ; Yes ; Yes ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.61e-09 V ; 2.38 V ; -0.00274 V ; 0.141 V ; 0.006 V ; 4.7e-10 s ; 6.02e-10 s ; Yes ; Yes ; 2.32 V ; 5.61e-09 V ; 2.38 V ; -0.00274 V ; 0.141 V ; 0.006 V ; 4.7e-10 s ; 6.02e-10 s ; Yes ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1200mv 85c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; LED[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; LED[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; LED[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; LED[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; LED[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ;
-; LED[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.33 V ; -0.00349 V ; 0.163 V ; 0.074 V ; 3.33e-09 s ; 3.14e-09 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.33 V ; -0.00349 V ; 0.163 V ; 0.074 V ; 3.33e-09 s ; 3.14e-09 s ; Yes ; Yes ;
-; LED[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.36 V ; -0.00476 V ; 0.096 V ; 0.013 V ; 4.39e-10 s ; 4.15e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.36 V ; -0.00476 V ; 0.096 V ; 0.013 V ; 4.39e-10 s ; 4.15e-10 s ; Yes ; Yes ;
-; LED[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.33 V ; -0.00349 V ; 0.163 V ; 0.074 V ; 3.33e-09 s ; 3.14e-09 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.33 V ; -0.00349 V ; 0.163 V ; 0.074 V ; 3.33e-09 s ; 3.14e-09 s ; Yes ; Yes ;
-; GPIO_2[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_2[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_2[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ;
-; GPIO_2[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.36 V ; -0.00476 V ; 0.096 V ; 0.013 V ; 4.39e-10 s ; 4.15e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.36 V ; -0.00476 V ; 0.096 V ; 0.013 V ; 4.39e-10 s ; 4.15e-10 s ; Yes ; Yes ;
-; GPIO_2[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_2[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ;
-; GPIO_2[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_2[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_2[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_2[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_2[10] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_2[11] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_2[12] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.36 V ; -0.00476 V ; 0.096 V ; 0.013 V ; 4.39e-10 s ; 4.15e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.36 V ; -0.00476 V ; 0.096 V ; 0.013 V ; 4.39e-10 s ; 4.15e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.33 V ; -0.00344 V ; 0.134 V ; 0.075 V ; 3.33e-09 s ; 3.16e-09 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.33 V ; -0.00344 V ; 0.134 V ; 0.075 V ; 3.33e-09 s ; 3.16e-09 s ; Yes ; Yes ;
-; GPIO_0_PI[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.36 V ; -0.00476 V ; 0.096 V ; 0.013 V ; 4.39e-10 s ; 4.15e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.36 V ; -0.00476 V ; 0.096 V ; 0.013 V ; 4.39e-10 s ; 4.15e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[12] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[13] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[14] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[15] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[16] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[17] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[18] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[19] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[20] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[21] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[22] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[23] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[24] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[25] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[26] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[27] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[28] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.33 V ; -0.00344 V ; 0.134 V ; 0.075 V ; 3.33e-09 s ; 3.16e-09 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.33 V ; -0.00344 V ; 0.134 V ; 0.075 V ; 3.33e-09 s ; 3.16e-09 s ; Yes ; Yes ;
-; GPIO_0_PI[29] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[30] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[32] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[33] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.36 V ; -0.00476 V ; 0.096 V ; 0.013 V ; 4.39e-10 s ; 4.15e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.36 V ; -0.00476 V ; 0.096 V ; 0.013 V ; 4.39e-10 s ; 4.15e-10 s ; Yes ; Yes ;
-; GPIO_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ;
-; GPIO_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ;
-; GPIO_1[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_1[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ;
-; GPIO_1[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_1[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_1[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ;
-; GPIO_1[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_1[10] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ;
-; GPIO_1[11] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_1[12] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.36 V ; -0.00476 V ; 0.096 V ; 0.013 V ; 4.39e-10 s ; 4.15e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.36 V ; -0.00476 V ; 0.096 V ; 0.013 V ; 4.39e-10 s ; 4.15e-10 s ; Yes ; Yes ;
-; GPIO_1[13] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_1[14] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ;
-; GPIO_1[15] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ;
-; GPIO_1[16] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_1[17] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_1[18] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ;
-; GPIO_1[19] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ;
-; GPIO_1[20] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ;
-; GPIO_1[21] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_1[22] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_1[23] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_1[24] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_1[25] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.36 V ; -0.00476 V ; 0.096 V ; 0.013 V ; 4.39e-10 s ; 4.15e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.36 V ; -0.00476 V ; 0.096 V ; 0.013 V ; 4.39e-10 s ; 4.15e-10 s ; Yes ; Yes ;
-; GPIO_1[26] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_1[27] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_1[28] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ;
-; GPIO_1[29] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ;
-; GPIO_1[30] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_1[31] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_1[32] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_1[33] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.36 V ; -0.00476 V ; 0.096 V ; 0.013 V ; 4.39e-10 s ; 4.15e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.36 V ; -0.00476 V ; 0.096 V ; 0.013 V ; 4.39e-10 s ; 4.15e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[10] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[11] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[31] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.74e-07 V ; 2.36 V ; -0.0201 V ; 0.072 V ; 0.033 V ; 4.04e-10 s ; 3.29e-10 s ; Yes ; Yes ; 2.32 V ; 5.74e-07 V ; 2.36 V ; -0.0201 V ; 0.072 V ; 0.033 V ; 4.04e-10 s ; 3.29e-10 s ; Yes ; Yes ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.45e-07 V ; 2.35 V ; -0.00643 V ; 0.081 V ; 0.031 V ; 5.31e-10 s ; 7.59e-10 s ; Yes ; Yes ; 2.32 V ; 9.45e-07 V ; 2.35 V ; -0.00643 V ; 0.081 V ; 0.031 V ; 5.31e-10 s ; 7.59e-10 s ; Yes ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Fast 1200mv 0c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; LED[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LED[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LED[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LED[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; LED[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ;
-; LED[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.64 V ; -0.0117 V ; 0.202 V ; 0.176 V ; 2.38e-09 s ; 2.22e-09 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.64 V ; -0.0117 V ; 0.202 V ; 0.176 V ; 2.38e-09 s ; 2.22e-09 s ; No ; Yes ;
-; LED[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ;
-; LED[7] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.64 V ; -0.0117 V ; 0.202 V ; 0.176 V ; 2.38e-09 s ; 2.22e-09 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.64 V ; -0.0117 V ; 0.202 V ; 0.176 V ; 2.38e-09 s ; 2.22e-09 s ; No ; Yes ;
-; GPIO_2[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_2[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_2[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ;
-; GPIO_2[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ;
-; GPIO_2[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_2[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ;
-; GPIO_2[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_2[7] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_2[8] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_2[9] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_2[10] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_2[11] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_2[12] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ;
-; GPIO_0_PI[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ;
-; GPIO_0_PI[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[7] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[12] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ;
-; GPIO_0_PI[13] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ;
-; GPIO_0_PI[14] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[15] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[16] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[17] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[18] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[19] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[20] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ;
-; GPIO_0_PI[21] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[22] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[23] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[24] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[25] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[26] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[27] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[28] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ;
-; GPIO_0_PI[29] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[30] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[32] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[33] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ;
-; GPIO_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ;
-; GPIO_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ;
-; GPIO_1[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_1[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ;
-; GPIO_1[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_1[7] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_1[8] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ;
-; GPIO_1[9] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_1[10] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ;
-; GPIO_1[11] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_1[12] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ;
-; GPIO_1[13] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_1[14] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ;
-; GPIO_1[15] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ;
-; GPIO_1[16] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_1[17] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_1[18] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ;
-; GPIO_1[19] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ;
-; GPIO_1[20] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ;
-; GPIO_1[21] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_1[22] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_1[23] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_1[24] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_1[25] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ;
-; GPIO_1[26] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_1[27] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_1[28] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ;
-; GPIO_1[29] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ;
-; GPIO_1[30] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_1[31] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_1[32] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_1[33] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[8] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ;
-; GPIO_0_PI[9] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[10] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[11] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; GPIO_0_PI[31] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
-; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ;
-; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+-------------------------------------------------------------------------+
-; Setup Transfers ;
-+--------------+--------------+----------+----------+----------+----------+
-; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
-+--------------+--------------+----------+----------+----------+----------+
-; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 31 ; 155 ; 1 ; 15 ;
-+--------------+--------------+----------+----------+----------+----------+
-Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
-
-
-+-------------------------------------------------------------------------+
-; Hold Transfers ;
-+--------------+--------------+----------+----------+----------+----------+
-; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
-+--------------+--------------+----------+----------+----------+----------+
-; GPIO_0_PI[8] ; GPIO_0_PI[8] ; 31 ; 155 ; 1 ; 15 ;
-+--------------+--------------+----------+----------+----------+----------+
-Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
-
-
----------------
-; Report TCCS ;
----------------
-No dedicated SERDES Transmitter circuitry present in device or used in design
-
-
----------------
-; Report RSKM ;
----------------
-No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
-
-
-+------------------------------------------------+
-; Unconstrained Paths Summary ;
-+---------------------------------+-------+------+
-; Property ; Setup ; Hold ;
-+---------------------------------+-------+------+
-; Illegal Clocks ; 0 ; 0 ;
-; Unconstrained Clocks ; 0 ; 0 ;
-; Unconstrained Input Ports ; 3 ; 3 ;
-; Unconstrained Input Port Paths ; 3 ; 3 ;
-; Unconstrained Output Ports ; 1 ; 1 ;
-; Unconstrained Output Port Paths ; 7 ; 7 ;
-+---------------------------------+-------+------+
-
-
-+--------------------------------------------------+
-; Clock Status Summary ;
-+--------------+--------------+------+-------------+
-; Target ; Clock ; Type ; Status ;
-+--------------+--------------+------+-------------+
-; GPIO_0_PI[8] ; GPIO_0_PI[8] ; Base ; Constrained ;
-+--------------+--------------+------+-------------+
-
-
-+------------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports ;
-+---------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment ;
-+---------------+--------------------------------------------------------------------------------------+
-; GPIO_0_PI[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; GPIO_0_PI[10] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; GPIO_0_PI[31] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+---------------+--------------------------------------------------------------------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports ;
-+---------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment ;
-+---------------+---------------------------------------------------------------------------------------+
-; GPIO_0_PI[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+---------------+---------------------------------------------------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports ;
-+---------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment ;
-+---------------+--------------------------------------------------------------------------------------+
-; GPIO_0_PI[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; GPIO_0_PI[10] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; GPIO_0_PI[31] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+---------------+--------------------------------------------------------------------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports ;
-+---------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment ;
-+---------------+---------------------------------------------------------------------------------------+
-; GPIO_0_PI[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+---------------+---------------------------------------------------------------------------------------+
-
-
-+--------------------------+
-; Timing Analyzer Messages ;
-+--------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Timing Analyzer
- Info: Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
- Info: Processing started: Wed Nov 16 16:51:44 2022
-Info: Command: quartus_sta SPI_test -c SPI_test
-Info: qsta_default_script.tcl version: #1
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'SPI_test.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332105): Deriving Clocks
- Info (332105): create_clock -period 1.000 -name GPIO_0_PI[8] GPIO_0_PI[8]
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
-Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
-Info: Analyzing Slow 1200mV 85C Model
-Critical Warning (332148): Timing requirements not met
- Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
-Info (332146): Worst-case setup slack is -1.327
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -1.327 -40.855 GPIO_0_PI[8]
-Info (332146): Worst-case hold slack is 0.360
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): 0.360 0.000 GPIO_0_PI[8]
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is -3.000
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -3.000 -41.000 GPIO_0_PI[8]
-Info: Analyzing Slow 1200mV 0C Model
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
-Critical Warning (332148): Timing requirements not met
- Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
-Info (332146): Worst-case setup slack is -1.141
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -1.141 -34.310 GPIO_0_PI[8]
-Info (332146): Worst-case hold slack is 0.320
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): 0.320 0.000 GPIO_0_PI[8]
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is -3.000
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -3.000 -41.000 GPIO_0_PI[8]
-Info: Analyzing Fast 1200mV 0C Model
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
-Critical Warning (332148): Timing requirements not met
- Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
-Info (332146): Worst-case setup slack is -0.818
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -0.818 -23.965 GPIO_0_PI[8]
-Info (332146): Worst-case hold slack is 0.192
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): 0.192 0.000 GPIO_0_PI[8]
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is -3.000
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -3.000 -43.505 GPIO_0_PI[8]
-Info (332102): Design is not fully constrained for setup requirements
-Info (332102): Design is not fully constrained for hold requirements
-Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings
- Info: Peak virtual memory: 4775 megabytes
- Info: Processing ended: Wed Nov 16 16:51:46 2022
- Info: Elapsed time: 00:00:02
- Info: Total CPU time (on all processors): 00:00:02
-
-
diff --git a/SPI/output_files/SPI_test.sta.summary b/SPI/output_files/SPI_test.sta.summary
deleted file mode 100644
index 478ffeb78d4970d60d27db3865e1215ad8cfffa8..0000000000000000000000000000000000000000
--- a/SPI/output_files/SPI_test.sta.summary
+++ /dev/null
@@ -1,41 +0,0 @@
-------------------------------------------------------------
-Timing Analyzer Summary
-------------------------------------------------------------
-
-Type : Slow 1200mV 85C Model Setup 'GPIO_0_PI[8]'
-Slack : -1.327
-TNS : -40.855
-
-Type : Slow 1200mV 85C Model Hold 'GPIO_0_PI[8]'
-Slack : 0.360
-TNS : 0.000
-
-Type : Slow 1200mV 85C Model Minimum Pulse Width 'GPIO_0_PI[8]'
-Slack : -3.000
-TNS : -41.000
-
-Type : Slow 1200mV 0C Model Setup 'GPIO_0_PI[8]'
-Slack : -1.141
-TNS : -34.310
-
-Type : Slow 1200mV 0C Model Hold 'GPIO_0_PI[8]'
-Slack : 0.320
-TNS : 0.000
-
-Type : Slow 1200mV 0C Model Minimum Pulse Width 'GPIO_0_PI[8]'
-Slack : -3.000
-TNS : -41.000
-
-Type : Fast 1200mV 0C Model Setup 'GPIO_0_PI[8]'
-Slack : -0.818
-TNS : -23.965
-
-Type : Fast 1200mV 0C Model Hold 'GPIO_0_PI[8]'
-Slack : 0.192
-TNS : 0.000
-
-Type : Fast 1200mV 0C Model Minimum Pulse Width 'GPIO_0_PI[8]'
-Slack : -3.000
-TNS : -43.505
-
-------------------------------------------------------------
diff --git a/SPI/output_files/output_file.jic b/SPI/output_files/output_file.jic
deleted file mode 100644
index 2a7835f3b03fc2f75eedbc40cab4d0d7f85af4b7..0000000000000000000000000000000000000000
Binary files a/SPI/output_files/output_file.jic and /dev/null differ
diff --git a/SPI/output_files/output_file.map b/SPI/output_files/output_file.map
deleted file mode 100644
index d3126bd7feb3973152c89d1be0ec5eb3de85348d..0000000000000000000000000000000000000000
--- a/SPI/output_files/output_file.map
+++ /dev/null
@@ -1,15 +0,0 @@
-BLOCK START ADDRESS END ADDRESS
-
-Page_0 0x00000000 0x000AF6E8
-
-
-Configuration device: EP4CE22
-Configuration mode: Active Serial
-Quad-Serial configuration device dummy clock cycle: 8
-
-
-Notes:
-
-- Data checksum for this conversion is 0x74B52A0B
-
-- All the addresses in this file are byte addresses
\ No newline at end of file
diff --git a/SPI/simulation/modelsim/SPI_test.sft b/SPI/simulation/modelsim/SPI_test.sft
deleted file mode 100644
index 88525759c0343c404f7563cc0a1cfa4072177f22..0000000000000000000000000000000000000000
--- a/SPI/simulation/modelsim/SPI_test.sft
+++ /dev/null
@@ -1,6 +0,0 @@
-set tool_name "ModelSim-Altera (SystemVerilog)"
-set corner_file_list {
- {{"Slow -6 1.2V 85 Model"} {SPI_test_6_1200mv_85c_slow.svo SPI_test_6_1200mv_85c_v_slow.sdo}}
- {{"Slow -6 1.2V 0 Model"} {SPI_test_6_1200mv_0c_slow.svo SPI_test_6_1200mv_0c_v_slow.sdo}}
- {{"Fast -M 1.2V 0 Model"} {SPI_test_min_1200mv_0c_fast.svo SPI_test_min_1200mv_0c_v_fast.sdo}}
-}
diff --git a/SPI/simulation/modelsim/SPI_test.svo b/SPI/simulation/modelsim/SPI_test.svo
deleted file mode 100644
index 400cf1f543fba8594cee2f0c097129b888c161f7..0000000000000000000000000000000000000000
--- a/SPI/simulation/modelsim/SPI_test.svo
+++ /dev/null
@@ -1,4083 +0,0 @@
-// Copyright (C) 2018 Intel Corporation. All rights reserved.
-// Your use of Intel Corporation's design tools, logic functions
-// and other software and tools, and its AMPP partner logic
-// functions, and any output files from any of the foregoing
-// (including device programming or simulation files), and any
-// associated documentation or information are expressly subject
-// to the terms and conditions of the Intel Program License
-// Subscription Agreement, the Intel Quartus Prime License Agreement,
-// the Intel FPGA IP License Agreement, or other applicable license
-// agreement, including, without limitation, that your use is for
-// the sole purpose of programming logic devices manufactured by
-// Intel and sold by Intel or its authorized distributors. Please
-// refer to the applicable agreement for further details.
-
-// VENDOR "Altera"
-// PROGRAM "Quartus Prime"
-// VERSION "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition"
-
-// DATE "11/16/2022 16:51:48"
-
-//
-// Device: Altera EP4CE22F17C6 Package FBGA256
-//
-
-//
-// This Verilog file should be used for ModelSim-Altera (SystemVerilog) only
-//
-
-`timescale 1 ps/ 1 ps
-
-module MyDE0_Nano (
- CLOCK_50,
- LED,
- KEY,
- GPIO_2,
- GPIO_2_IN,
- GPIO_0_PI,
- GPIO_0_PI_IN,
- GPIO_1,
- GPIO_1_IN);
-input CLOCK_50;
-output [7:0] LED;
-input [1:0] KEY;
-output [12:0] GPIO_2;
-input [2:0] GPIO_2_IN;
-output [33:0] GPIO_0_PI;
-input [1:0] GPIO_0_PI_IN;
-output [33:0] GPIO_1;
-input [1:0] GPIO_1_IN;
-
-// Design Ports Information
-// CLOCK_50 => Location: PIN_R7, I/O Standard: 2.5 V, Current Strength: Default
-// LED[0] => Location: PIN_A15, I/O Standard: 2.5 V, Current Strength: Default
-// LED[1] => Location: PIN_A13, I/O Standard: 2.5 V, Current Strength: Default
-// LED[2] => Location: PIN_B13, I/O Standard: 2.5 V, Current Strength: Default
-// LED[3] => Location: PIN_A11, I/O Standard: 2.5 V, Current Strength: Default
-// LED[4] => Location: PIN_D1, I/O Standard: 2.5 V, Current Strength: Default
-// LED[5] => Location: PIN_F3, I/O Standard: 2.5 V, Current Strength: Default
-// LED[6] => Location: PIN_B1, I/O Standard: 2.5 V, Current Strength: Default
-// LED[7] => Location: PIN_L3, I/O Standard: 2.5 V, Current Strength: Default
-// KEY[0] => Location: PIN_J15, I/O Standard: 2.5 V, Current Strength: Default
-// KEY[1] => Location: PIN_E1, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2_IN[0] => Location: PIN_E16, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2_IN[1] => Location: PIN_E15, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2_IN[2] => Location: PIN_D6, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI_IN[0] => Location: PIN_E6, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI_IN[1] => Location: PIN_C14, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1_IN[0] => Location: PIN_A12, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1_IN[1] => Location: PIN_T10, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[0] => Location: PIN_R4, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[1] => Location: PIN_D12, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[2] => Location: PIN_F2, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[3] => Location: PIN_G5, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[4] => Location: PIN_T4, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[5] => Location: PIN_J2, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[6] => Location: PIN_B3, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[7] => Location: PIN_D3, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[8] => Location: PIN_M7, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[9] => Location: PIN_T2, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[10] => Location: PIN_B12, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[11] => Location: PIN_C8, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[12] => Location: PIN_E8, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[0] => Location: PIN_A10, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[1] => Location: PIN_P2, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[2] => Location: PIN_R1, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[3] => Location: PIN_C6, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[4] => Location: PIN_T5, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[5] => Location: PIN_A5, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[6] => Location: PIN_P15, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[7] => Location: PIN_R5, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[12] => Location: PIN_P1, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[13] => Location: PIN_R16, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[14] => Location: PIN_C3, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[15] => Location: PIN_B10, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[16] => Location: PIN_F9, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[17] => Location: PIN_B6, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[18] => Location: PIN_R3, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[19] => Location: PIN_T12, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[20] => Location: PIN_J1, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[21] => Location: PIN_A14, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[22] => Location: PIN_R6, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[23] => Location: PIN_A7, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[24] => Location: PIN_B14, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[25] => Location: PIN_R13, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[26] => Location: PIN_L8, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[27] => Location: PIN_E10, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[28] => Location: PIN_C11, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[29] => Location: PIN_B11, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[30] => Location: PIN_B7, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[32] => Location: PIN_D8, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[33] => Location: PIN_B16, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[0] => Location: PIN_T6, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[1] => Location: PIN_N3, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[2] => Location: PIN_G16, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[3] => Location: PIN_F1, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[4] => Location: PIN_B4, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[5] => Location: PIN_L15, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[6] => Location: PIN_D14, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[7] => Location: PIN_N5, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[8] => Location: PIN_F15, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[9] => Location: PIN_R11, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[10] => Location: PIN_L1, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[11] => Location: PIN_E11, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[12] => Location: PIN_D15, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[13] => Location: PIN_T13, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[14] => Location: PIN_K16, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[15] => Location: PIN_C15, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[16] => Location: PIN_P8, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[17] => Location: PIN_R10, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[18] => Location: PIN_N1, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[19] => Location: PIN_C16, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[20] => Location: PIN_C2, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[21] => Location: PIN_N12, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[22] => Location: PIN_B5, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[23] => Location: PIN_M8, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[24] => Location: PIN_N6, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[25] => Location: PIN_F13, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[26] => Location: PIN_P3, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[27] => Location: PIN_M6, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[28] => Location: PIN_G1, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[29] => Location: PIN_J16, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[30] => Location: PIN_T14, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[31] => Location: PIN_R14, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[32] => Location: PIN_C9, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[33] => Location: PIN_L4, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[8] => Location: PIN_G2, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[9] => Location: PIN_D5, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[10] => Location: PIN_E7, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[11] => Location: PIN_A6, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[31] => Location: PIN_D11, I/O Standard: 2.5 V, Current Strength: Default
-
-
-wire gnd;
-wire vcc;
-wire unknown;
-
-assign gnd = 1'b0;
-assign vcc = 1'b1;
-assign unknown = 1'bx;
-
-tri1 devclrn;
-tri1 devpor;
-tri1 devoe;
-// synopsys translate_off
-initial $sdf_annotate("SPI_test_v.sdo");
-// synopsys translate_on
-
-wire \CLOCK_50~input_o ;
-wire \KEY[0]~input_o ;
-wire \KEY[1]~input_o ;
-wire \GPIO_2_IN[0]~input_o ;
-wire \GPIO_2_IN[1]~input_o ;
-wire \GPIO_2_IN[2]~input_o ;
-wire \GPIO_0_PI_IN[0]~input_o ;
-wire \GPIO_0_PI_IN[1]~input_o ;
-wire \GPIO_1_IN[0]~input_o ;
-wire \GPIO_1_IN[1]~input_o ;
-wire \GPIO_2[0]~input_o ;
-wire \GPIO_2[1]~input_o ;
-wire \GPIO_2[2]~input_o ;
-wire \GPIO_2[3]~input_o ;
-wire \GPIO_2[4]~input_o ;
-wire \GPIO_2[5]~input_o ;
-wire \GPIO_2[6]~input_o ;
-wire \GPIO_2[7]~input_o ;
-wire \GPIO_2[8]~input_o ;
-wire \GPIO_2[9]~input_o ;
-wire \GPIO_2[10]~input_o ;
-wire \GPIO_2[11]~input_o ;
-wire \GPIO_2[12]~input_o ;
-wire \GPIO_0_PI[0]~input_o ;
-wire \GPIO_0_PI[1]~input_o ;
-wire \GPIO_0_PI[2]~input_o ;
-wire \GPIO_0_PI[3]~input_o ;
-wire \GPIO_0_PI[4]~input_o ;
-wire \GPIO_0_PI[5]~input_o ;
-wire \GPIO_0_PI[6]~input_o ;
-wire \GPIO_0_PI[7]~input_o ;
-wire \GPIO_0_PI[12]~input_o ;
-wire \GPIO_0_PI[13]~input_o ;
-wire \GPIO_0_PI[14]~input_o ;
-wire \GPIO_0_PI[15]~input_o ;
-wire \GPIO_0_PI[16]~input_o ;
-wire \GPIO_0_PI[17]~input_o ;
-wire \GPIO_0_PI[18]~input_o ;
-wire \GPIO_0_PI[19]~input_o ;
-wire \GPIO_0_PI[20]~input_o ;
-wire \GPIO_0_PI[21]~input_o ;
-wire \GPIO_0_PI[22]~input_o ;
-wire \GPIO_0_PI[23]~input_o ;
-wire \GPIO_0_PI[24]~input_o ;
-wire \GPIO_0_PI[25]~input_o ;
-wire \GPIO_0_PI[26]~input_o ;
-wire \GPIO_0_PI[27]~input_o ;
-wire \GPIO_0_PI[28]~input_o ;
-wire \GPIO_0_PI[29]~input_o ;
-wire \GPIO_0_PI[30]~input_o ;
-wire \GPIO_0_PI[32]~input_o ;
-wire \GPIO_0_PI[33]~input_o ;
-wire \GPIO_1[0]~input_o ;
-wire \GPIO_1[1]~input_o ;
-wire \GPIO_1[2]~input_o ;
-wire \GPIO_1[3]~input_o ;
-wire \GPIO_1[4]~input_o ;
-wire \GPIO_1[5]~input_o ;
-wire \GPIO_1[6]~input_o ;
-wire \GPIO_1[7]~input_o ;
-wire \GPIO_1[8]~input_o ;
-wire \GPIO_1[9]~input_o ;
-wire \GPIO_1[10]~input_o ;
-wire \GPIO_1[11]~input_o ;
-wire \GPIO_1[12]~input_o ;
-wire \GPIO_1[13]~input_o ;
-wire \GPIO_1[14]~input_o ;
-wire \GPIO_1[15]~input_o ;
-wire \GPIO_1[16]~input_o ;
-wire \GPIO_1[17]~input_o ;
-wire \GPIO_1[18]~input_o ;
-wire \GPIO_1[19]~input_o ;
-wire \GPIO_1[20]~input_o ;
-wire \GPIO_1[21]~input_o ;
-wire \GPIO_1[22]~input_o ;
-wire \GPIO_1[23]~input_o ;
-wire \GPIO_1[24]~input_o ;
-wire \GPIO_1[25]~input_o ;
-wire \GPIO_1[26]~input_o ;
-wire \GPIO_1[27]~input_o ;
-wire \GPIO_1[28]~input_o ;
-wire \GPIO_1[29]~input_o ;
-wire \GPIO_1[30]~input_o ;
-wire \GPIO_1[31]~input_o ;
-wire \GPIO_1[32]~input_o ;
-wire \GPIO_1[33]~input_o ;
-wire \GPIO_0_PI[11]~input_o ;
-wire \GPIO_2[0]~output_o ;
-wire \GPIO_2[1]~output_o ;
-wire \GPIO_2[2]~output_o ;
-wire \GPIO_2[3]~output_o ;
-wire \GPIO_2[4]~output_o ;
-wire \GPIO_2[5]~output_o ;
-wire \GPIO_2[6]~output_o ;
-wire \GPIO_2[7]~output_o ;
-wire \GPIO_2[8]~output_o ;
-wire \GPIO_2[9]~output_o ;
-wire \GPIO_2[10]~output_o ;
-wire \GPIO_2[11]~output_o ;
-wire \GPIO_2[12]~output_o ;
-wire \GPIO_0_PI[0]~output_o ;
-wire \GPIO_0_PI[1]~output_o ;
-wire \GPIO_0_PI[2]~output_o ;
-wire \GPIO_0_PI[3]~output_o ;
-wire \GPIO_0_PI[4]~output_o ;
-wire \GPIO_0_PI[5]~output_o ;
-wire \GPIO_0_PI[6]~output_o ;
-wire \GPIO_0_PI[7]~output_o ;
-wire \GPIO_0_PI[12]~output_o ;
-wire \GPIO_0_PI[13]~output_o ;
-wire \GPIO_0_PI[14]~output_o ;
-wire \GPIO_0_PI[15]~output_o ;
-wire \GPIO_0_PI[16]~output_o ;
-wire \GPIO_0_PI[17]~output_o ;
-wire \GPIO_0_PI[18]~output_o ;
-wire \GPIO_0_PI[19]~output_o ;
-wire \GPIO_0_PI[20]~output_o ;
-wire \GPIO_0_PI[21]~output_o ;
-wire \GPIO_0_PI[22]~output_o ;
-wire \GPIO_0_PI[23]~output_o ;
-wire \GPIO_0_PI[24]~output_o ;
-wire \GPIO_0_PI[25]~output_o ;
-wire \GPIO_0_PI[26]~output_o ;
-wire \GPIO_0_PI[27]~output_o ;
-wire \GPIO_0_PI[28]~output_o ;
-wire \GPIO_0_PI[29]~output_o ;
-wire \GPIO_0_PI[30]~output_o ;
-wire \GPIO_0_PI[32]~output_o ;
-wire \GPIO_0_PI[33]~output_o ;
-wire \GPIO_1[0]~output_o ;
-wire \GPIO_1[1]~output_o ;
-wire \GPIO_1[2]~output_o ;
-wire \GPIO_1[3]~output_o ;
-wire \GPIO_1[4]~output_o ;
-wire \GPIO_1[5]~output_o ;
-wire \GPIO_1[6]~output_o ;
-wire \GPIO_1[7]~output_o ;
-wire \GPIO_1[8]~output_o ;
-wire \GPIO_1[9]~output_o ;
-wire \GPIO_1[10]~output_o ;
-wire \GPIO_1[11]~output_o ;
-wire \GPIO_1[12]~output_o ;
-wire \GPIO_1[13]~output_o ;
-wire \GPIO_1[14]~output_o ;
-wire \GPIO_1[15]~output_o ;
-wire \GPIO_1[16]~output_o ;
-wire \GPIO_1[17]~output_o ;
-wire \GPIO_1[18]~output_o ;
-wire \GPIO_1[19]~output_o ;
-wire \GPIO_1[20]~output_o ;
-wire \GPIO_1[21]~output_o ;
-wire \GPIO_1[22]~output_o ;
-wire \GPIO_1[23]~output_o ;
-wire \GPIO_1[24]~output_o ;
-wire \GPIO_1[25]~output_o ;
-wire \GPIO_1[26]~output_o ;
-wire \GPIO_1[27]~output_o ;
-wire \GPIO_1[28]~output_o ;
-wire \GPIO_1[29]~output_o ;
-wire \GPIO_1[30]~output_o ;
-wire \GPIO_1[31]~output_o ;
-wire \GPIO_1[32]~output_o ;
-wire \GPIO_1[33]~output_o ;
-wire \GPIO_0_PI[8]~output_o ;
-wire \GPIO_0_PI[9]~output_o ;
-wire \GPIO_0_PI[10]~output_o ;
-wire \GPIO_0_PI[11]~output_o ;
-wire \GPIO_0_PI[31]~output_o ;
-wire \LED[0]~output_o ;
-wire \LED[1]~output_o ;
-wire \LED[2]~output_o ;
-wire \LED[3]~output_o ;
-wire \LED[4]~output_o ;
-wire \LED[5]~output_o ;
-wire \LED[6]~output_o ;
-wire \LED[7]~output_o ;
-wire \GPIO_0_PI[8]~input_o ;
-wire \GPIO_0_PI[8]~inputclkctrl_outclk ;
-wire \spi_slave_instance|cnt[0]~12_combout ;
-wire \spi_slave_instance|cnt[1]~4_combout ;
-wire \spi_slave_instance|cnt[1]~5 ;
-wire \spi_slave_instance|cnt[2]~6_combout ;
-wire \spi_slave_instance|cnt[2]~7 ;
-wire \spi_slave_instance|cnt[3]~8_combout ;
-wire \spi_slave_instance|cnt[3]~9 ;
-wire \spi_slave_instance|cnt[4]~10_combout ;
-wire \GPIO_0_PI[31]~input_o ;
-wire \GPIO_0_PI[9]~input_o ;
-wire \spi_slave_instance|Equal0~0_combout ;
-wire \spi_slave_instance|q~31_combout ;
-wire \spi_slave_instance|q~30_combout ;
-wire \spi_slave_instance|q~29_combout ;
-wire \spi_slave_instance|q~28_combout ;
-wire \spi_slave_instance|q~27_combout ;
-wire \spi_slave_instance|q~26_combout ;
-wire \spi_slave_instance|q~25_combout ;
-wire \spi_slave_instance|q~24_combout ;
-wire \spi_slave_instance|q~23_combout ;
-wire \spi_slave_instance|q~22_combout ;
-wire \spi_slave_instance|q~21_combout ;
-wire \spi_slave_instance|q~20_combout ;
-wire \spi_slave_instance|q~19_combout ;
-wire \spi_slave_instance|q~18_combout ;
-wire \spi_slave_instance|q~17_combout ;
-wire \spi_slave_instance|q~16_combout ;
-wire \spi_slave_instance|q~15_combout ;
-wire \spi_slave_instance|q~14_combout ;
-wire \spi_slave_instance|q~13_combout ;
-wire \spi_slave_instance|q~12_combout ;
-wire \spi_slave_instance|q~10_combout ;
-wire \spi_slave_instance|q~11_combout ;
-wire \spi_slave_instance|q~9_combout ;
-wire \spi_slave_instance|q~8_combout ;
-wire \spi_slave_instance|q~7_combout ;
-wire \spi_slave_instance|q~6_combout ;
-wire \spi_slave_instance|q~5_combout ;
-wire \spi_slave_instance|q~4_combout ;
-wire \spi_slave_instance|q~3_combout ;
-wire \spi_slave_instance|q~2_combout ;
-wire \spi_slave_instance|q~1_combout ;
-wire \spi_slave_instance|q~0_combout ;
-wire \spi_slave_instance|qdelayed~q ;
-wire \spi_slave_instance|miso~0_combout ;
-wire \GPIO_0_PI[10]~input_o ;
-wire [4:0] \spi_slave_instance|cnt ;
-wire [31:0] \spi_slave_instance|q ;
-
-
-hard_block auto_generated_inst(
- .devpor(devpor),
- .devclrn(devclrn),
- .devoe(devoe));
-
-// Location: IOOBUF_X5_Y0_N23
-cycloneive_io_obuf \GPIO_2[0]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[0]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[0]~output .bus_hold = "false";
-defparam \GPIO_2[0]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X51_Y34_N23
-cycloneive_io_obuf \GPIO_2[1]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[1]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[1]~output .bus_hold = "false";
-defparam \GPIO_2[1]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y24_N23
-cycloneive_io_obuf \GPIO_2[2]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[2]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[2]~output .bus_hold = "false";
-defparam \GPIO_2[2]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y24_N16
-cycloneive_io_obuf \GPIO_2[3]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[3]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[3]~output .bus_hold = "false";
-defparam \GPIO_2[3]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X5_Y0_N16
-cycloneive_io_obuf \GPIO_2[4]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[4]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[4]~output .bus_hold = "false";
-defparam \GPIO_2[4]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y15_N2
-cycloneive_io_obuf \GPIO_2[5]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[5]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[5]~output .bus_hold = "false";
-defparam \GPIO_2[5]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X3_Y34_N2
-cycloneive_io_obuf \GPIO_2[6]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[6]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[6]~output .bus_hold = "false";
-defparam \GPIO_2[6]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X1_Y34_N9
-cycloneive_io_obuf \GPIO_2[7]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[7]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[7]~output .bus_hold = "false";
-defparam \GPIO_2[7]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X11_Y0_N16
-cycloneive_io_obuf \GPIO_2[8]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[8]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[8]~output .bus_hold = "false";
-defparam \GPIO_2[8]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X3_Y0_N2
-cycloneive_io_obuf \GPIO_2[9]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[9]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[9]~output .bus_hold = "false";
-defparam \GPIO_2[9]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X43_Y34_N23
-cycloneive_io_obuf \GPIO_2[10]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[10]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[10]~output .bus_hold = "false";
-defparam \GPIO_2[10]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X23_Y34_N16
-cycloneive_io_obuf \GPIO_2[11]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[11]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[11]~output .bus_hold = "false";
-defparam \GPIO_2[11]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X20_Y34_N9
-cycloneive_io_obuf \GPIO_2[12]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[12]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[12]~output .bus_hold = "false";
-defparam \GPIO_2[12]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X34_Y34_N9
-cycloneive_io_obuf \GPIO_0_PI[0]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[0]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[0]~output .bus_hold = "false";
-defparam \GPIO_0_PI[0]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y4_N16
-cycloneive_io_obuf \GPIO_0_PI[1]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[1]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[1]~output .bus_hold = "false";
-defparam \GPIO_0_PI[1]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y5_N23
-cycloneive_io_obuf \GPIO_0_PI[2]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[2]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[2]~output .bus_hold = "false";
-defparam \GPIO_0_PI[2]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X18_Y34_N23
-cycloneive_io_obuf \GPIO_0_PI[3]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[3]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[3]~output .bus_hold = "false";
-defparam \GPIO_0_PI[3]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X14_Y0_N16
-cycloneive_io_obuf \GPIO_0_PI[4]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[4]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[4]~output .bus_hold = "false";
-defparam \GPIO_0_PI[4]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X14_Y34_N23
-cycloneive_io_obuf \GPIO_0_PI[5]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[5]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[5]~output .bus_hold = "false";
-defparam \GPIO_0_PI[5]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X53_Y6_N16
-cycloneive_io_obuf \GPIO_0_PI[6]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[6]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[6]~output .bus_hold = "false";
-defparam \GPIO_0_PI[6]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X14_Y0_N23
-cycloneive_io_obuf \GPIO_0_PI[7]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[7]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[7]~output .bus_hold = "false";
-defparam \GPIO_0_PI[7]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y4_N23
-cycloneive_io_obuf \GPIO_0_PI[12]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[12]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[12]~output .bus_hold = "false";
-defparam \GPIO_0_PI[12]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X53_Y8_N23
-cycloneive_io_obuf \GPIO_0_PI[13]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[13]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[13]~output .bus_hold = "false";
-defparam \GPIO_0_PI[13]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X1_Y34_N2
-cycloneive_io_obuf \GPIO_0_PI[14]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[14]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[14]~output .bus_hold = "false";
-defparam \GPIO_0_PI[14]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X34_Y34_N16
-cycloneive_io_obuf \GPIO_0_PI[15]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[15]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[15]~output .bus_hold = "false";
-defparam \GPIO_0_PI[15]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X34_Y34_N2
-cycloneive_io_obuf \GPIO_0_PI[16]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[16]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[16]~output .bus_hold = "false";
-defparam \GPIO_0_PI[16]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X16_Y34_N9
-cycloneive_io_obuf \GPIO_0_PI[17]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[17]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[17]~output .bus_hold = "false";
-defparam \GPIO_0_PI[17]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X1_Y0_N9
-cycloneive_io_obuf \GPIO_0_PI[18]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[18]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[18]~output .bus_hold = "false";
-defparam \GPIO_0_PI[18]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X36_Y0_N9
-cycloneive_io_obuf \GPIO_0_PI[19]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[19]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[19]~output .bus_hold = "false";
-defparam \GPIO_0_PI[19]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y15_N9
-cycloneive_io_obuf \GPIO_0_PI[20]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[20]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[20]~output .bus_hold = "false";
-defparam \GPIO_0_PI[20]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X47_Y34_N23
-cycloneive_io_obuf \GPIO_0_PI[21]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[21]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[21]~output .bus_hold = "false";
-defparam \GPIO_0_PI[21]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X14_Y0_N9
-cycloneive_io_obuf \GPIO_0_PI[22]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[22]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[22]~output .bus_hold = "false";
-defparam \GPIO_0_PI[22]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X20_Y34_N23
-cycloneive_io_obuf \GPIO_0_PI[23]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[23]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[23]~output .bus_hold = "false";
-defparam \GPIO_0_PI[23]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X45_Y34_N2
-cycloneive_io_obuf \GPIO_0_PI[24]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[24]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[24]~output .bus_hold = "false";
-defparam \GPIO_0_PI[24]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X40_Y0_N23
-cycloneive_io_obuf \GPIO_0_PI[25]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[25]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[25]~output .bus_hold = "false";
-defparam \GPIO_0_PI[25]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X18_Y0_N9
-cycloneive_io_obuf \GPIO_0_PI[26]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[26]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[26]~output .bus_hold = "false";
-defparam \GPIO_0_PI[26]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X45_Y34_N16
-cycloneive_io_obuf \GPIO_0_PI[27]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[27]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[27]~output .bus_hold = "false";
-defparam \GPIO_0_PI[27]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X38_Y34_N2
-cycloneive_io_obuf \GPIO_0_PI[28]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[28]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[28]~output .bus_hold = "false";
-defparam \GPIO_0_PI[28]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X40_Y34_N9
-cycloneive_io_obuf \GPIO_0_PI[29]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[29]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[29]~output .bus_hold = "false";
-defparam \GPIO_0_PI[29]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X18_Y34_N2
-cycloneive_io_obuf \GPIO_0_PI[30]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[30]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[30]~output .bus_hold = "false";
-defparam \GPIO_0_PI[30]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X23_Y34_N23
-cycloneive_io_obuf \GPIO_0_PI[32]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[32]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[32]~output .bus_hold = "false";
-defparam \GPIO_0_PI[32]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X53_Y22_N2
-cycloneive_io_obuf \GPIO_0_PI[33]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[33]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[33]~output .bus_hold = "false";
-defparam \GPIO_0_PI[33]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X14_Y0_N2
-cycloneive_io_obuf \GPIO_1[0]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[0]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[0]~output .bus_hold = "false";
-defparam \GPIO_1[0]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X1_Y0_N23
-cycloneive_io_obuf \GPIO_1[1]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[1]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[1]~output .bus_hold = "false";
-defparam \GPIO_1[1]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X53_Y20_N23
-cycloneive_io_obuf \GPIO_1[2]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[2]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[2]~output .bus_hold = "false";
-defparam \GPIO_1[2]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y23_N2
-cycloneive_io_obuf \GPIO_1[3]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[3]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[3]~output .bus_hold = "false";
-defparam \GPIO_1[3]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X7_Y34_N2
-cycloneive_io_obuf \GPIO_1[4]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[4]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[4]~output .bus_hold = "false";
-defparam \GPIO_1[4]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X53_Y11_N2
-cycloneive_io_obuf \GPIO_1[5]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[5]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[5]~output .bus_hold = "false";
-defparam \GPIO_1[5]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X51_Y34_N9
-cycloneive_io_obuf \GPIO_1[6]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[6]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[6]~output .bus_hold = "false";
-defparam \GPIO_1[6]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X5_Y0_N9
-cycloneive_io_obuf \GPIO_1[7]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[7]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[7]~output .bus_hold = "false";
-defparam \GPIO_1[7]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X53_Y22_N9
-cycloneive_io_obuf \GPIO_1[8]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[8]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[8]~output .bus_hold = "false";
-defparam \GPIO_1[8]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X34_Y0_N2
-cycloneive_io_obuf \GPIO_1[9]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[9]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[9]~output .bus_hold = "false";
-defparam \GPIO_1[9]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y11_N9
-cycloneive_io_obuf \GPIO_1[10]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[10]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[10]~output .bus_hold = "false";
-defparam \GPIO_1[10]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X45_Y34_N9
-cycloneive_io_obuf \GPIO_1[11]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[11]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[11]~output .bus_hold = "false";
-defparam \GPIO_1[11]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X53_Y26_N23
-cycloneive_io_obuf \GPIO_1[12]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[12]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[12]~output .bus_hold = "false";
-defparam \GPIO_1[12]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X40_Y0_N16
-cycloneive_io_obuf \GPIO_1[13]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[13]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[13]~output .bus_hold = "false";
-defparam \GPIO_1[13]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X53_Y12_N2
-cycloneive_io_obuf \GPIO_1[14]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[14]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[14]~output .bus_hold = "false";
-defparam \GPIO_1[14]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X53_Y30_N2
-cycloneive_io_obuf \GPIO_1[15]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[15]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[15]~output .bus_hold = "false";
-defparam \GPIO_1[15]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X25_Y0_N16
-cycloneive_io_obuf \GPIO_1[16]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[16]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[16]~output .bus_hold = "false";
-defparam \GPIO_1[16]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X34_Y0_N23
-cycloneive_io_obuf \GPIO_1[17]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[17]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[17]~output .bus_hold = "false";
-defparam \GPIO_1[17]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y7_N2
-cycloneive_io_obuf \GPIO_1[18]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[18]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[18]~output .bus_hold = "false";
-defparam \GPIO_1[18]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X53_Y30_N9
-cycloneive_io_obuf \GPIO_1[19]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[19]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[19]~output .bus_hold = "false";
-defparam \GPIO_1[19]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y27_N2
-cycloneive_io_obuf \GPIO_1[20]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[20]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[20]~output .bus_hold = "false";
-defparam \GPIO_1[20]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X47_Y0_N23
-cycloneive_io_obuf \GPIO_1[21]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[21]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[21]~output .bus_hold = "false";
-defparam \GPIO_1[21]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X11_Y34_N2
-cycloneive_io_obuf \GPIO_1[22]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[22]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[22]~output .bus_hold = "false";
-defparam \GPIO_1[22]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X20_Y0_N9
-cycloneive_io_obuf \GPIO_1[23]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[23]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[23]~output .bus_hold = "false";
-defparam \GPIO_1[23]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X5_Y0_N2
-cycloneive_io_obuf \GPIO_1[24]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[24]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[24]~output .bus_hold = "false";
-defparam \GPIO_1[24]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X53_Y21_N23
-cycloneive_io_obuf \GPIO_1[25]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[25]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[25]~output .bus_hold = "false";
-defparam \GPIO_1[25]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X1_Y0_N16
-cycloneive_io_obuf \GPIO_1[26]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[26]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[26]~output .bus_hold = "false";
-defparam \GPIO_1[26]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X7_Y0_N9
-cycloneive_io_obuf \GPIO_1[27]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[27]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[27]~output .bus_hold = "false";
-defparam \GPIO_1[27]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y23_N23
-cycloneive_io_obuf \GPIO_1[28]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[28]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[28]~output .bus_hold = "false";
-defparam \GPIO_1[28]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X53_Y14_N9
-cycloneive_io_obuf \GPIO_1[29]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[29]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[29]~output .bus_hold = "false";
-defparam \GPIO_1[29]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X45_Y0_N23
-cycloneive_io_obuf \GPIO_1[30]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[30]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[30]~output .bus_hold = "false";
-defparam \GPIO_1[30]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X49_Y0_N2
-cycloneive_io_obuf \GPIO_1[31]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[31]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[31]~output .bus_hold = "false";
-defparam \GPIO_1[31]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X31_Y34_N2
-cycloneive_io_obuf \GPIO_1[32]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[32]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[32]~output .bus_hold = "false";
-defparam \GPIO_1[32]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y6_N16
-cycloneive_io_obuf \GPIO_1[33]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[33]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[33]~output .bus_hold = "false";
-defparam \GPIO_1[33]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y23_N16
-cycloneive_io_obuf \GPIO_0_PI[8]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[8]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[8]~output .bus_hold = "false";
-defparam \GPIO_0_PI[8]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X5_Y34_N16
-cycloneive_io_obuf \GPIO_0_PI[9]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[9]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[9]~output .bus_hold = "false";
-defparam \GPIO_0_PI[9]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X16_Y34_N16
-cycloneive_io_obuf \GPIO_0_PI[10]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[10]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[10]~output .bus_hold = "false";
-defparam \GPIO_0_PI[10]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X16_Y34_N2
-cycloneive_io_obuf \GPIO_0_PI[11]~output (
- .i(\spi_slave_instance|miso~0_combout ),
- .oe(!\GPIO_0_PI[10]~input_o ),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[11]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[11]~output .bus_hold = "false";
-defparam \GPIO_0_PI[11]~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X51_Y34_N16
-cycloneive_io_obuf \GPIO_0_PI[31]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[31]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[31]~output .bus_hold = "false";
-defparam \GPIO_0_PI[31]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X38_Y34_N16
-cycloneive_io_obuf \LED[0]~output (
- .i(gnd),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\LED[0]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \LED[0]~output .bus_hold = "false";
-defparam \LED[0]~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X49_Y34_N2
-cycloneive_io_obuf \LED[1]~output (
- .i(gnd),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\LED[1]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \LED[1]~output .bus_hold = "false";
-defparam \LED[1]~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X49_Y34_N9
-cycloneive_io_obuf \LED[2]~output (
- .i(gnd),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\LED[2]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \LED[2]~output .bus_hold = "false";
-defparam \LED[2]~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X40_Y34_N2
-cycloneive_io_obuf \LED[3]~output (
- .i(gnd),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\LED[3]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \LED[3]~output .bus_hold = "false";
-defparam \LED[3]~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y25_N9
-cycloneive_io_obuf \LED[4]~output (
- .i(gnd),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\LED[4]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \LED[4]~output .bus_hold = "false";
-defparam \LED[4]~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y26_N16
-cycloneive_io_obuf \LED[5]~output (
- .i(gnd),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\LED[5]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \LED[5]~output .bus_hold = "false";
-defparam \LED[5]~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y28_N9
-cycloneive_io_obuf \LED[6]~output (
- .i(gnd),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\LED[6]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \LED[6]~output .bus_hold = "false";
-defparam \LED[6]~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y10_N23
-cycloneive_io_obuf \LED[7]~output (
- .i(gnd),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\LED[7]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \LED[7]~output .bus_hold = "false";
-defparam \LED[7]~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y23_N15
-cycloneive_io_ibuf \GPIO_0_PI[8]~input (
- .i(GPIO_0_PI[8]),
- .ibar(gnd),
- .o(\GPIO_0_PI[8]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[8]~input .bus_hold = "false";
-defparam \GPIO_0_PI[8]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: CLKCTRL_G0
-cycloneive_clkctrl \GPIO_0_PI[8]~inputclkctrl (
- .ena(vcc),
- .inclk({vcc,vcc,vcc,\GPIO_0_PI[8]~input_o }),
- .clkselect(2'b00),
- .devclrn(devclrn),
- .devpor(devpor),
- .outclk(\GPIO_0_PI[8]~inputclkctrl_outclk ));
-// synopsys translate_off
-defparam \GPIO_0_PI[8]~inputclkctrl .clock_type = "global clock";
-defparam \GPIO_0_PI[8]~inputclkctrl .ena_register_mode = "none";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N12
-cycloneive_lcell_comb \spi_slave_instance|cnt[0]~12 (
-// Equation(s):
-// \spi_slave_instance|cnt[0]~12_combout = !\spi_slave_instance|cnt [0]
-
- .dataa(gnd),
- .datab(gnd),
- .datac(\spi_slave_instance|cnt [0]),
- .datad(gnd),
- .cin(gnd),
- .combout(\spi_slave_instance|cnt[0]~12_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|cnt[0]~12 .lut_mask = 16'h0F0F;
-defparam \spi_slave_instance|cnt[0]~12 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N13
-dffeas \spi_slave_instance|cnt[0] (
- .clk(!\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|cnt[0]~12_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|cnt [0]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|cnt[0] .is_wysiwyg = "true";
-defparam \spi_slave_instance|cnt[0] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N2
-cycloneive_lcell_comb \spi_slave_instance|cnt[1]~4 (
-// Equation(s):
-// \spi_slave_instance|cnt[1]~4_combout = (\spi_slave_instance|cnt [0] & (\spi_slave_instance|cnt [1] $ (VCC))) # (!\spi_slave_instance|cnt [0] & (\spi_slave_instance|cnt [1] & VCC))
-// \spi_slave_instance|cnt[1]~5 = CARRY((\spi_slave_instance|cnt [0] & \spi_slave_instance|cnt [1]))
-
- .dataa(\spi_slave_instance|cnt [0]),
- .datab(\spi_slave_instance|cnt [1]),
- .datac(gnd),
- .datad(vcc),
- .cin(gnd),
- .combout(\spi_slave_instance|cnt[1]~4_combout ),
- .cout(\spi_slave_instance|cnt[1]~5 ));
-// synopsys translate_off
-defparam \spi_slave_instance|cnt[1]~4 .lut_mask = 16'h6688;
-defparam \spi_slave_instance|cnt[1]~4 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N3
-dffeas \spi_slave_instance|cnt[1] (
- .clk(!\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|cnt[1]~4_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|cnt [1]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|cnt[1] .is_wysiwyg = "true";
-defparam \spi_slave_instance|cnt[1] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N4
-cycloneive_lcell_comb \spi_slave_instance|cnt[2]~6 (
-// Equation(s):
-// \spi_slave_instance|cnt[2]~6_combout = (\spi_slave_instance|cnt [2] & (!\spi_slave_instance|cnt[1]~5 )) # (!\spi_slave_instance|cnt [2] & ((\spi_slave_instance|cnt[1]~5 ) # (GND)))
-// \spi_slave_instance|cnt[2]~7 = CARRY((!\spi_slave_instance|cnt[1]~5 ) # (!\spi_slave_instance|cnt [2]))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|cnt [2]),
- .datac(gnd),
- .datad(vcc),
- .cin(\spi_slave_instance|cnt[1]~5 ),
- .combout(\spi_slave_instance|cnt[2]~6_combout ),
- .cout(\spi_slave_instance|cnt[2]~7 ));
-// synopsys translate_off
-defparam \spi_slave_instance|cnt[2]~6 .lut_mask = 16'h3C3F;
-defparam \spi_slave_instance|cnt[2]~6 .sum_lutc_input = "cin";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N5
-dffeas \spi_slave_instance|cnt[2] (
- .clk(!\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|cnt[2]~6_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|cnt [2]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|cnt[2] .is_wysiwyg = "true";
-defparam \spi_slave_instance|cnt[2] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N6
-cycloneive_lcell_comb \spi_slave_instance|cnt[3]~8 (
-// Equation(s):
-// \spi_slave_instance|cnt[3]~8_combout = (\spi_slave_instance|cnt [3] & (\spi_slave_instance|cnt[2]~7 $ (GND))) # (!\spi_slave_instance|cnt [3] & (!\spi_slave_instance|cnt[2]~7 & VCC))
-// \spi_slave_instance|cnt[3]~9 = CARRY((\spi_slave_instance|cnt [3] & !\spi_slave_instance|cnt[2]~7 ))
-
- .dataa(\spi_slave_instance|cnt [3]),
- .datab(gnd),
- .datac(gnd),
- .datad(vcc),
- .cin(\spi_slave_instance|cnt[2]~7 ),
- .combout(\spi_slave_instance|cnt[3]~8_combout ),
- .cout(\spi_slave_instance|cnt[3]~9 ));
-// synopsys translate_off
-defparam \spi_slave_instance|cnt[3]~8 .lut_mask = 16'hA50A;
-defparam \spi_slave_instance|cnt[3]~8 .sum_lutc_input = "cin";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N7
-dffeas \spi_slave_instance|cnt[3] (
- .clk(!\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|cnt[3]~8_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|cnt [3]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|cnt[3] .is_wysiwyg = "true";
-defparam \spi_slave_instance|cnt[3] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N8
-cycloneive_lcell_comb \spi_slave_instance|cnt[4]~10 (
-// Equation(s):
-// \spi_slave_instance|cnt[4]~10_combout = \spi_slave_instance|cnt [4] $ (\spi_slave_instance|cnt[3]~9 )
-
- .dataa(gnd),
- .datab(\spi_slave_instance|cnt [4]),
- .datac(gnd),
- .datad(gnd),
- .cin(\spi_slave_instance|cnt[3]~9 ),
- .combout(\spi_slave_instance|cnt[4]~10_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|cnt[4]~10 .lut_mask = 16'h3C3C;
-defparam \spi_slave_instance|cnt[4]~10 .sum_lutc_input = "cin";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N9
-dffeas \spi_slave_instance|cnt[4] (
- .clk(!\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|cnt[4]~10_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|cnt [4]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|cnt[4] .is_wysiwyg = "true";
-defparam \spi_slave_instance|cnt[4] .power_up = "low";
-// synopsys translate_on
-
-// Location: IOIBUF_X51_Y34_N15
-cycloneive_io_ibuf \GPIO_0_PI[31]~input (
- .i(GPIO_0_PI[31]),
- .ibar(gnd),
- .o(\GPIO_0_PI[31]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[31]~input .bus_hold = "false";
-defparam \GPIO_0_PI[31]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X5_Y34_N15
-cycloneive_io_ibuf \GPIO_0_PI[9]~input (
- .i(GPIO_0_PI[9]),
- .ibar(gnd),
- .o(\GPIO_0_PI[9]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[9]~input .bus_hold = "false";
-defparam \GPIO_0_PI[9]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: FF_X21_Y31_N5
-dffeas \spi_slave_instance|q[0] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(gnd),
- .asdata(\GPIO_0_PI[9]~input_o ),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(vcc),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [0]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[0] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[0] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N18
-cycloneive_lcell_comb \spi_slave_instance|Equal0~0 (
-// Equation(s):
-// \spi_slave_instance|Equal0~0_combout = (!\spi_slave_instance|cnt [0] & (!\spi_slave_instance|cnt [1] & (!\spi_slave_instance|cnt [2] & !\spi_slave_instance|cnt [3])))
-
- .dataa(\spi_slave_instance|cnt [0]),
- .datab(\spi_slave_instance|cnt [1]),
- .datac(\spi_slave_instance|cnt [2]),
- .datad(\spi_slave_instance|cnt [3]),
- .cin(gnd),
- .combout(\spi_slave_instance|Equal0~0_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|Equal0~0 .lut_mask = 16'h0001;
-defparam \spi_slave_instance|Equal0~0 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: LCCOMB_X21_Y31_N22
-cycloneive_lcell_comb \spi_slave_instance|q~31 (
-// Equation(s):
-// \spi_slave_instance|q~31_combout = (\spi_slave_instance|cnt [4] & (((\spi_slave_instance|q [0])))) # (!\spi_slave_instance|cnt [4] & ((\spi_slave_instance|Equal0~0_combout & (\GPIO_0_PI[31]~input_o )) # (!\spi_slave_instance|Equal0~0_combout &
-// ((\spi_slave_instance|q [0])))))
-
- .dataa(\spi_slave_instance|cnt [4]),
- .datab(\GPIO_0_PI[31]~input_o ),
- .datac(\spi_slave_instance|q [0]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~31_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~31 .lut_mask = 16'hE4F0;
-defparam \spi_slave_instance|q~31 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X21_Y31_N23
-dffeas \spi_slave_instance|q[1] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~31_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [1]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[1] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[1] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X21_Y31_N24
-cycloneive_lcell_comb \spi_slave_instance|q~30 (
-// Equation(s):
-// \spi_slave_instance|q~30_combout = (\spi_slave_instance|q [1] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(\spi_slave_instance|cnt [4]),
- .datab(gnd),
- .datac(\spi_slave_instance|q [1]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~30_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~30 .lut_mask = 16'hA0F0;
-defparam \spi_slave_instance|q~30 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X21_Y31_N25
-dffeas \spi_slave_instance|q[2] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~30_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [2]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[2] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[2] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X21_Y31_N30
-cycloneive_lcell_comb \spi_slave_instance|q~29 (
-// Equation(s):
-// \spi_slave_instance|q~29_combout = (\spi_slave_instance|q [2] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(\spi_slave_instance|cnt [4]),
- .datab(\spi_slave_instance|q [2]),
- .datac(gnd),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~29_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~29 .lut_mask = 16'h88CC;
-defparam \spi_slave_instance|q~29 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X21_Y31_N31
-dffeas \spi_slave_instance|q[3] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~29_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [3]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[3] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[3] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X21_Y31_N8
-cycloneive_lcell_comb \spi_slave_instance|q~28 (
-// Equation(s):
-// \spi_slave_instance|q~28_combout = (\spi_slave_instance|q [3] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(\spi_slave_instance|cnt [4]),
- .datab(gnd),
- .datac(\spi_slave_instance|q [3]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~28_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~28 .lut_mask = 16'hA0F0;
-defparam \spi_slave_instance|q~28 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X21_Y31_N9
-dffeas \spi_slave_instance|q[4] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~28_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [4]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[4] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[4] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X21_Y31_N18
-cycloneive_lcell_comb \spi_slave_instance|q~27 (
-// Equation(s):
-// \spi_slave_instance|q~27_combout = (\spi_slave_instance|q [4] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(\spi_slave_instance|cnt [4]),
- .datab(gnd),
- .datac(\spi_slave_instance|q [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~27_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~27 .lut_mask = 16'hA0F0;
-defparam \spi_slave_instance|q~27 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X21_Y31_N19
-dffeas \spi_slave_instance|q[5] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~27_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [5]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[5] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[5] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X21_Y31_N28
-cycloneive_lcell_comb \spi_slave_instance|q~26 (
-// Equation(s):
-// \spi_slave_instance|q~26_combout = (\spi_slave_instance|q [5] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(\spi_slave_instance|cnt [4]),
- .datab(\spi_slave_instance|q [5]),
- .datac(gnd),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~26_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~26 .lut_mask = 16'h88CC;
-defparam \spi_slave_instance|q~26 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X21_Y31_N29
-dffeas \spi_slave_instance|q[6] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~26_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [6]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[6] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[6] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X21_Y31_N10
-cycloneive_lcell_comb \spi_slave_instance|q~25 (
-// Equation(s):
-// \spi_slave_instance|q~25_combout = (\spi_slave_instance|q [6] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(\spi_slave_instance|cnt [4]),
- .datab(\spi_slave_instance|q [6]),
- .datac(gnd),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~25_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~25 .lut_mask = 16'h88CC;
-defparam \spi_slave_instance|q~25 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X21_Y31_N11
-dffeas \spi_slave_instance|q[7] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~25_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [7]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[7] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[7] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N14
-cycloneive_lcell_comb \spi_slave_instance|q~24 (
-// Equation(s):
-// \spi_slave_instance|q~24_combout = (\spi_slave_instance|q [7] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|cnt [4]),
- .datac(\spi_slave_instance|q [7]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~24_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~24 .lut_mask = 16'hC0F0;
-defparam \spi_slave_instance|q~24 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N15
-dffeas \spi_slave_instance|q[8] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~24_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [8]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[8] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[8] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N28
-cycloneive_lcell_comb \spi_slave_instance|q~23 (
-// Equation(s):
-// \spi_slave_instance|q~23_combout = (\spi_slave_instance|q [8] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|q [8]),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~23_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~23 .lut_mask = 16'hC0CC;
-defparam \spi_slave_instance|q~23 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N29
-dffeas \spi_slave_instance|q[9] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~23_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [9]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[9] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[9] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N30
-cycloneive_lcell_comb \spi_slave_instance|q~22 (
-// Equation(s):
-// \spi_slave_instance|q~22_combout = (\spi_slave_instance|q [9] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|q [9]),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~22_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~22 .lut_mask = 16'hC0CC;
-defparam \spi_slave_instance|q~22 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N31
-dffeas \spi_slave_instance|q[10] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~22_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [10]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[10] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[10] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N24
-cycloneive_lcell_comb \spi_slave_instance|q~21 (
-// Equation(s):
-// \spi_slave_instance|q~21_combout = (\spi_slave_instance|q [10] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|cnt [4]),
- .datac(\spi_slave_instance|q [10]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~21_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~21 .lut_mask = 16'hC0F0;
-defparam \spi_slave_instance|q~21 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N25
-dffeas \spi_slave_instance|q[11] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~21_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [11]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[11] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[11] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N26
-cycloneive_lcell_comb \spi_slave_instance|q~20 (
-// Equation(s):
-// \spi_slave_instance|q~20_combout = (\spi_slave_instance|q [11] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|q [11]),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~20_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~20 .lut_mask = 16'hC0CC;
-defparam \spi_slave_instance|q~20 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N27
-dffeas \spi_slave_instance|q[12] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~20_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [12]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[12] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[12] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X21_Y31_N20
-cycloneive_lcell_comb \spi_slave_instance|q~19 (
-// Equation(s):
-// \spi_slave_instance|q~19_combout = (\spi_slave_instance|q [12] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(\spi_slave_instance|cnt [4]),
- .datab(gnd),
- .datac(\spi_slave_instance|q [12]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~19_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~19 .lut_mask = 16'hA0F0;
-defparam \spi_slave_instance|q~19 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X21_Y31_N21
-dffeas \spi_slave_instance|q[13] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~19_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [13]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[13] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[13] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N16
-cycloneive_lcell_comb \spi_slave_instance|q~18 (
-// Equation(s):
-// \spi_slave_instance|q~18_combout = (\spi_slave_instance|q [13] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|cnt [4]),
- .datac(\spi_slave_instance|q [13]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~18_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~18 .lut_mask = 16'hC0F0;
-defparam \spi_slave_instance|q~18 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N17
-dffeas \spi_slave_instance|q[14] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~18_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [14]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[14] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[14] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N10
-cycloneive_lcell_comb \spi_slave_instance|q~17 (
-// Equation(s):
-// \spi_slave_instance|q~17_combout = (\spi_slave_instance|q [14] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|q [14]),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~17_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~17 .lut_mask = 16'hC0CC;
-defparam \spi_slave_instance|q~17 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N11
-dffeas \spi_slave_instance|q[15] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~17_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [15]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[15] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[15] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N20
-cycloneive_lcell_comb \spi_slave_instance|q~16 (
-// Equation(s):
-// \spi_slave_instance|q~16_combout = (\spi_slave_instance|q [15] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|cnt [4]),
- .datac(\spi_slave_instance|q [15]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~16_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~16 .lut_mask = 16'hC0F0;
-defparam \spi_slave_instance|q~16 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N21
-dffeas \spi_slave_instance|q[16] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~16_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [16]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[16] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[16] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N22
-cycloneive_lcell_comb \spi_slave_instance|q~15 (
-// Equation(s):
-// \spi_slave_instance|q~15_combout = (\spi_slave_instance|q [16] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|q [16]),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~15_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~15 .lut_mask = 16'hC0CC;
-defparam \spi_slave_instance|q~15 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N23
-dffeas \spi_slave_instance|q[17] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~15_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [17]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[17] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[17] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N0
-cycloneive_lcell_comb \spi_slave_instance|q~14 (
-// Equation(s):
-// \spi_slave_instance|q~14_combout = (\spi_slave_instance|q [17] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|cnt [4]),
- .datac(\spi_slave_instance|q [17]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~14_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~14 .lut_mask = 16'hC0F0;
-defparam \spi_slave_instance|q~14 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N1
-dffeas \spi_slave_instance|q[18] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~14_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [18]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[18] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[18] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N28
-cycloneive_lcell_comb \spi_slave_instance|q~13 (
-// Equation(s):
-// \spi_slave_instance|q~13_combout = (\spi_slave_instance|q [18] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|cnt [4]),
- .datac(\spi_slave_instance|q [18]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~13_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~13 .lut_mask = 16'hC0F0;
-defparam \spi_slave_instance|q~13 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N29
-dffeas \spi_slave_instance|q[19] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~13_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [19]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[19] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[19] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N8
-cycloneive_lcell_comb \spi_slave_instance|q~12 (
-// Equation(s):
-// \spi_slave_instance|q~12_combout = (\spi_slave_instance|q [19] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|q [19]),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~12_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~12 .lut_mask = 16'hC0CC;
-defparam \spi_slave_instance|q~12 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N9
-dffeas \spi_slave_instance|q[20] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~12_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [20]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[20] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[20] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N10
-cycloneive_lcell_comb \spi_slave_instance|q~10 (
-// Equation(s):
-// \spi_slave_instance|q~10_combout = (\spi_slave_instance|cnt [1]) # ((\spi_slave_instance|cnt [4]) # (\spi_slave_instance|cnt [3]))
-
- .dataa(\spi_slave_instance|cnt [1]),
- .datab(gnd),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|cnt [3]),
- .cin(gnd),
- .combout(\spi_slave_instance|q~10_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~10 .lut_mask = 16'hFFFA;
-defparam \spi_slave_instance|q~10 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N26
-cycloneive_lcell_comb \spi_slave_instance|q~11 (
-// Equation(s):
-// \spi_slave_instance|q~11_combout = (\spi_slave_instance|q [20] & ((\spi_slave_instance|cnt [2]) # ((\spi_slave_instance|cnt [0]) # (\spi_slave_instance|q~10_combout ))))
-
- .dataa(\spi_slave_instance|cnt [2]),
- .datab(\spi_slave_instance|q [20]),
- .datac(\spi_slave_instance|cnt [0]),
- .datad(\spi_slave_instance|q~10_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~11_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~11 .lut_mask = 16'hCCC8;
-defparam \spi_slave_instance|q~11 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N27
-dffeas \spi_slave_instance|q[21] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~11_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [21]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[21] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[21] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N12
-cycloneive_lcell_comb \spi_slave_instance|q~9 (
-// Equation(s):
-// \spi_slave_instance|q~9_combout = (\spi_slave_instance|q [21] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(\spi_slave_instance|q [21]),
- .datab(gnd),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~9_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~9 .lut_mask = 16'hA0AA;
-defparam \spi_slave_instance|q~9 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N13
-dffeas \spi_slave_instance|q[22] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~9_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [22]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[22] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[22] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N6
-cycloneive_lcell_comb \spi_slave_instance|q~8 (
-// Equation(s):
-// \spi_slave_instance|q~8_combout = (\spi_slave_instance|q [22] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(\spi_slave_instance|q [22]),
- .datab(gnd),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~8_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~8 .lut_mask = 16'hA0AA;
-defparam \spi_slave_instance|q~8 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N7
-dffeas \spi_slave_instance|q[23] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~8_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [23]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[23] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[23] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N4
-cycloneive_lcell_comb \spi_slave_instance|q~7 (
-// Equation(s):
-// \spi_slave_instance|q~7_combout = (\spi_slave_instance|q [23] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(\spi_slave_instance|q [23]),
- .datab(gnd),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~7_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~7 .lut_mask = 16'hA0AA;
-defparam \spi_slave_instance|q~7 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N5
-dffeas \spi_slave_instance|q[24] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~7_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [24]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[24] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[24] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N30
-cycloneive_lcell_comb \spi_slave_instance|q~6 (
-// Equation(s):
-// \spi_slave_instance|q~6_combout = (\spi_slave_instance|q [24] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|q [24]),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~6_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~6 .lut_mask = 16'hC0CC;
-defparam \spi_slave_instance|q~6 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N31
-dffeas \spi_slave_instance|q[25] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~6_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [25]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[25] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[25] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N20
-cycloneive_lcell_comb \spi_slave_instance|q~5 (
-// Equation(s):
-// \spi_slave_instance|q~5_combout = (\spi_slave_instance|q [25] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(\spi_slave_instance|q [25]),
- .datab(gnd),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~5_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~5 .lut_mask = 16'hA0AA;
-defparam \spi_slave_instance|q~5 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N21
-dffeas \spi_slave_instance|q[26] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~5_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [26]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[26] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[26] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N14
-cycloneive_lcell_comb \spi_slave_instance|q~4 (
-// Equation(s):
-// \spi_slave_instance|q~4_combout = (\spi_slave_instance|q [26] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|q [26]),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~4_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~4 .lut_mask = 16'hC0CC;
-defparam \spi_slave_instance|q~4 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N15
-dffeas \spi_slave_instance|q[27] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~4_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [27]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[27] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[27] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N16
-cycloneive_lcell_comb \spi_slave_instance|q~3 (
-// Equation(s):
-// \spi_slave_instance|q~3_combout = (\spi_slave_instance|q [27] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|q [27]),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~3_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~3 .lut_mask = 16'hC0CC;
-defparam \spi_slave_instance|q~3 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N17
-dffeas \spi_slave_instance|q[28] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~3_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [28]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[28] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[28] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N18
-cycloneive_lcell_comb \spi_slave_instance|q~2 (
-// Equation(s):
-// \spi_slave_instance|q~2_combout = (\spi_slave_instance|q [28] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|q [28]),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~2_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~2 .lut_mask = 16'hC0CC;
-defparam \spi_slave_instance|q~2 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N19
-dffeas \spi_slave_instance|q[29] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~2_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [29]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[29] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[29] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N24
-cycloneive_lcell_comb \spi_slave_instance|q~1 (
-// Equation(s):
-// \spi_slave_instance|q~1_combout = (\spi_slave_instance|q [29] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|q [29]),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~1_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~1 .lut_mask = 16'hC0CC;
-defparam \spi_slave_instance|q~1 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N25
-dffeas \spi_slave_instance|q[30] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~1_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [30]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[30] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[30] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N22
-cycloneive_lcell_comb \spi_slave_instance|q~0 (
-// Equation(s):
-// \spi_slave_instance|q~0_combout = (\spi_slave_instance|q [30] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|q [30]),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~0_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~0 .lut_mask = 16'hC0CC;
-defparam \spi_slave_instance|q~0 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N23
-dffeas \spi_slave_instance|q[31] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~0_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [31]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[31] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[31] .power_up = "low";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N1
-dffeas \spi_slave_instance|qdelayed (
- .clk(!\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(gnd),
- .asdata(\spi_slave_instance|q [31]),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(vcc),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|qdelayed~q ),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|qdelayed .is_wysiwyg = "true";
-defparam \spi_slave_instance|qdelayed .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N0
-cycloneive_lcell_comb \spi_slave_instance|miso~0 (
-// Equation(s):
-// \spi_slave_instance|miso~0_combout = (\spi_slave_instance|qdelayed~q & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|cnt [4]),
- .datac(\spi_slave_instance|qdelayed~q ),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|miso~0_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|miso~0 .lut_mask = 16'hC0F0;
-defparam \spi_slave_instance|miso~0 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: IOIBUF_X16_Y34_N15
-cycloneive_io_ibuf \GPIO_0_PI[10]~input (
- .i(GPIO_0_PI[10]),
- .ibar(gnd),
- .o(\GPIO_0_PI[10]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[10]~input .bus_hold = "false";
-defparam \GPIO_0_PI[10]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X16_Y0_N15
-cycloneive_io_ibuf \CLOCK_50~input (
- .i(CLOCK_50),
- .ibar(gnd),
- .o(\CLOCK_50~input_o ));
-// synopsys translate_off
-defparam \CLOCK_50~input .bus_hold = "false";
-defparam \CLOCK_50~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y14_N1
-cycloneive_io_ibuf \KEY[0]~input (
- .i(KEY[0]),
- .ibar(gnd),
- .o(\KEY[0]~input_o ));
-// synopsys translate_off
-defparam \KEY[0]~input .bus_hold = "false";
-defparam \KEY[0]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y16_N8
-cycloneive_io_ibuf \KEY[1]~input (
- .i(KEY[1]),
- .ibar(gnd),
- .o(\KEY[1]~input_o ));
-// synopsys translate_off
-defparam \KEY[1]~input .bus_hold = "false";
-defparam \KEY[1]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y17_N8
-cycloneive_io_ibuf \GPIO_2_IN[0]~input (
- .i(GPIO_2_IN[0]),
- .ibar(gnd),
- .o(\GPIO_2_IN[0]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2_IN[0]~input .bus_hold = "false";
-defparam \GPIO_2_IN[0]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y17_N1
-cycloneive_io_ibuf \GPIO_2_IN[1]~input (
- .i(GPIO_2_IN[1]),
- .ibar(gnd),
- .o(\GPIO_2_IN[1]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2_IN[1]~input .bus_hold = "false";
-defparam \GPIO_2_IN[1]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X9_Y34_N8
-cycloneive_io_ibuf \GPIO_2_IN[2]~input (
- .i(GPIO_2_IN[2]),
- .ibar(gnd),
- .o(\GPIO_2_IN[2]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2_IN[2]~input .bus_hold = "false";
-defparam \GPIO_2_IN[2]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X14_Y34_N15
-cycloneive_io_ibuf \GPIO_0_PI_IN[0]~input (
- .i(GPIO_0_PI_IN[0]),
- .ibar(gnd),
- .o(\GPIO_0_PI_IN[0]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI_IN[0]~input .bus_hold = "false";
-defparam \GPIO_0_PI_IN[0]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X51_Y34_N1
-cycloneive_io_ibuf \GPIO_0_PI_IN[1]~input (
- .i(GPIO_0_PI_IN[1]),
- .ibar(gnd),
- .o(\GPIO_0_PI_IN[1]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI_IN[1]~input .bus_hold = "false";
-defparam \GPIO_0_PI_IN[1]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X43_Y34_N15
-cycloneive_io_ibuf \GPIO_1_IN[0]~input (
- .i(GPIO_1_IN[0]),
- .ibar(gnd),
- .o(\GPIO_1_IN[0]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1_IN[0]~input .bus_hold = "false";
-defparam \GPIO_1_IN[0]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X34_Y0_N15
-cycloneive_io_ibuf \GPIO_1_IN[1]~input (
- .i(GPIO_1_IN[1]),
- .ibar(gnd),
- .o(\GPIO_1_IN[1]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1_IN[1]~input .bus_hold = "false";
-defparam \GPIO_1_IN[1]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X5_Y0_N22
-cycloneive_io_ibuf \GPIO_2[0]~input (
- .i(GPIO_2[0]),
- .ibar(gnd),
- .o(\GPIO_2[0]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[0]~input .bus_hold = "false";
-defparam \GPIO_2[0]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X51_Y34_N22
-cycloneive_io_ibuf \GPIO_2[1]~input (
- .i(GPIO_2[1]),
- .ibar(gnd),
- .o(\GPIO_2[1]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[1]~input .bus_hold = "false";
-defparam \GPIO_2[1]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y24_N22
-cycloneive_io_ibuf \GPIO_2[2]~input (
- .i(GPIO_2[2]),
- .ibar(gnd),
- .o(\GPIO_2[2]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[2]~input .bus_hold = "false";
-defparam \GPIO_2[2]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y24_N15
-cycloneive_io_ibuf \GPIO_2[3]~input (
- .i(GPIO_2[3]),
- .ibar(gnd),
- .o(\GPIO_2[3]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[3]~input .bus_hold = "false";
-defparam \GPIO_2[3]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X5_Y0_N15
-cycloneive_io_ibuf \GPIO_2[4]~input (
- .i(GPIO_2[4]),
- .ibar(gnd),
- .o(\GPIO_2[4]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[4]~input .bus_hold = "false";
-defparam \GPIO_2[4]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y15_N1
-cycloneive_io_ibuf \GPIO_2[5]~input (
- .i(GPIO_2[5]),
- .ibar(gnd),
- .o(\GPIO_2[5]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[5]~input .bus_hold = "false";
-defparam \GPIO_2[5]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X3_Y34_N1
-cycloneive_io_ibuf \GPIO_2[6]~input (
- .i(GPIO_2[6]),
- .ibar(gnd),
- .o(\GPIO_2[6]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[6]~input .bus_hold = "false";
-defparam \GPIO_2[6]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X1_Y34_N8
-cycloneive_io_ibuf \GPIO_2[7]~input (
- .i(GPIO_2[7]),
- .ibar(gnd),
- .o(\GPIO_2[7]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[7]~input .bus_hold = "false";
-defparam \GPIO_2[7]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X11_Y0_N15
-cycloneive_io_ibuf \GPIO_2[8]~input (
- .i(GPIO_2[8]),
- .ibar(gnd),
- .o(\GPIO_2[8]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[8]~input .bus_hold = "false";
-defparam \GPIO_2[8]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X3_Y0_N1
-cycloneive_io_ibuf \GPIO_2[9]~input (
- .i(GPIO_2[9]),
- .ibar(gnd),
- .o(\GPIO_2[9]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[9]~input .bus_hold = "false";
-defparam \GPIO_2[9]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X43_Y34_N22
-cycloneive_io_ibuf \GPIO_2[10]~input (
- .i(GPIO_2[10]),
- .ibar(gnd),
- .o(\GPIO_2[10]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[10]~input .bus_hold = "false";
-defparam \GPIO_2[10]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X23_Y34_N15
-cycloneive_io_ibuf \GPIO_2[11]~input (
- .i(GPIO_2[11]),
- .ibar(gnd),
- .o(\GPIO_2[11]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[11]~input .bus_hold = "false";
-defparam \GPIO_2[11]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X20_Y34_N8
-cycloneive_io_ibuf \GPIO_2[12]~input (
- .i(GPIO_2[12]),
- .ibar(gnd),
- .o(\GPIO_2[12]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[12]~input .bus_hold = "false";
-defparam \GPIO_2[12]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X34_Y34_N8
-cycloneive_io_ibuf \GPIO_0_PI[0]~input (
- .i(GPIO_0_PI[0]),
- .ibar(gnd),
- .o(\GPIO_0_PI[0]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[0]~input .bus_hold = "false";
-defparam \GPIO_0_PI[0]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y4_N15
-cycloneive_io_ibuf \GPIO_0_PI[1]~input (
- .i(GPIO_0_PI[1]),
- .ibar(gnd),
- .o(\GPIO_0_PI[1]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[1]~input .bus_hold = "false";
-defparam \GPIO_0_PI[1]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y5_N22
-cycloneive_io_ibuf \GPIO_0_PI[2]~input (
- .i(GPIO_0_PI[2]),
- .ibar(gnd),
- .o(\GPIO_0_PI[2]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[2]~input .bus_hold = "false";
-defparam \GPIO_0_PI[2]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X18_Y34_N22
-cycloneive_io_ibuf \GPIO_0_PI[3]~input (
- .i(GPIO_0_PI[3]),
- .ibar(gnd),
- .o(\GPIO_0_PI[3]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[3]~input .bus_hold = "false";
-defparam \GPIO_0_PI[3]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X14_Y0_N15
-cycloneive_io_ibuf \GPIO_0_PI[4]~input (
- .i(GPIO_0_PI[4]),
- .ibar(gnd),
- .o(\GPIO_0_PI[4]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[4]~input .bus_hold = "false";
-defparam \GPIO_0_PI[4]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X14_Y34_N22
-cycloneive_io_ibuf \GPIO_0_PI[5]~input (
- .i(GPIO_0_PI[5]),
- .ibar(gnd),
- .o(\GPIO_0_PI[5]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[5]~input .bus_hold = "false";
-defparam \GPIO_0_PI[5]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y6_N15
-cycloneive_io_ibuf \GPIO_0_PI[6]~input (
- .i(GPIO_0_PI[6]),
- .ibar(gnd),
- .o(\GPIO_0_PI[6]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[6]~input .bus_hold = "false";
-defparam \GPIO_0_PI[6]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X14_Y0_N22
-cycloneive_io_ibuf \GPIO_0_PI[7]~input (
- .i(GPIO_0_PI[7]),
- .ibar(gnd),
- .o(\GPIO_0_PI[7]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[7]~input .bus_hold = "false";
-defparam \GPIO_0_PI[7]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y4_N22
-cycloneive_io_ibuf \GPIO_0_PI[12]~input (
- .i(GPIO_0_PI[12]),
- .ibar(gnd),
- .o(\GPIO_0_PI[12]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[12]~input .bus_hold = "false";
-defparam \GPIO_0_PI[12]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y8_N22
-cycloneive_io_ibuf \GPIO_0_PI[13]~input (
- .i(GPIO_0_PI[13]),
- .ibar(gnd),
- .o(\GPIO_0_PI[13]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[13]~input .bus_hold = "false";
-defparam \GPIO_0_PI[13]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X1_Y34_N1
-cycloneive_io_ibuf \GPIO_0_PI[14]~input (
- .i(GPIO_0_PI[14]),
- .ibar(gnd),
- .o(\GPIO_0_PI[14]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[14]~input .bus_hold = "false";
-defparam \GPIO_0_PI[14]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X34_Y34_N15
-cycloneive_io_ibuf \GPIO_0_PI[15]~input (
- .i(GPIO_0_PI[15]),
- .ibar(gnd),
- .o(\GPIO_0_PI[15]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[15]~input .bus_hold = "false";
-defparam \GPIO_0_PI[15]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X34_Y34_N1
-cycloneive_io_ibuf \GPIO_0_PI[16]~input (
- .i(GPIO_0_PI[16]),
- .ibar(gnd),
- .o(\GPIO_0_PI[16]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[16]~input .bus_hold = "false";
-defparam \GPIO_0_PI[16]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X16_Y34_N8
-cycloneive_io_ibuf \GPIO_0_PI[17]~input (
- .i(GPIO_0_PI[17]),
- .ibar(gnd),
- .o(\GPIO_0_PI[17]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[17]~input .bus_hold = "false";
-defparam \GPIO_0_PI[17]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X1_Y0_N8
-cycloneive_io_ibuf \GPIO_0_PI[18]~input (
- .i(GPIO_0_PI[18]),
- .ibar(gnd),
- .o(\GPIO_0_PI[18]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[18]~input .bus_hold = "false";
-defparam \GPIO_0_PI[18]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X36_Y0_N8
-cycloneive_io_ibuf \GPIO_0_PI[19]~input (
- .i(GPIO_0_PI[19]),
- .ibar(gnd),
- .o(\GPIO_0_PI[19]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[19]~input .bus_hold = "false";
-defparam \GPIO_0_PI[19]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y15_N8
-cycloneive_io_ibuf \GPIO_0_PI[20]~input (
- .i(GPIO_0_PI[20]),
- .ibar(gnd),
- .o(\GPIO_0_PI[20]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[20]~input .bus_hold = "false";
-defparam \GPIO_0_PI[20]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X47_Y34_N22
-cycloneive_io_ibuf \GPIO_0_PI[21]~input (
- .i(GPIO_0_PI[21]),
- .ibar(gnd),
- .o(\GPIO_0_PI[21]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[21]~input .bus_hold = "false";
-defparam \GPIO_0_PI[21]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X14_Y0_N8
-cycloneive_io_ibuf \GPIO_0_PI[22]~input (
- .i(GPIO_0_PI[22]),
- .ibar(gnd),
- .o(\GPIO_0_PI[22]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[22]~input .bus_hold = "false";
-defparam \GPIO_0_PI[22]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X20_Y34_N22
-cycloneive_io_ibuf \GPIO_0_PI[23]~input (
- .i(GPIO_0_PI[23]),
- .ibar(gnd),
- .o(\GPIO_0_PI[23]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[23]~input .bus_hold = "false";
-defparam \GPIO_0_PI[23]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X45_Y34_N1
-cycloneive_io_ibuf \GPIO_0_PI[24]~input (
- .i(GPIO_0_PI[24]),
- .ibar(gnd),
- .o(\GPIO_0_PI[24]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[24]~input .bus_hold = "false";
-defparam \GPIO_0_PI[24]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X40_Y0_N22
-cycloneive_io_ibuf \GPIO_0_PI[25]~input (
- .i(GPIO_0_PI[25]),
- .ibar(gnd),
- .o(\GPIO_0_PI[25]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[25]~input .bus_hold = "false";
-defparam \GPIO_0_PI[25]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X18_Y0_N8
-cycloneive_io_ibuf \GPIO_0_PI[26]~input (
- .i(GPIO_0_PI[26]),
- .ibar(gnd),
- .o(\GPIO_0_PI[26]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[26]~input .bus_hold = "false";
-defparam \GPIO_0_PI[26]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X45_Y34_N15
-cycloneive_io_ibuf \GPIO_0_PI[27]~input (
- .i(GPIO_0_PI[27]),
- .ibar(gnd),
- .o(\GPIO_0_PI[27]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[27]~input .bus_hold = "false";
-defparam \GPIO_0_PI[27]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X38_Y34_N1
-cycloneive_io_ibuf \GPIO_0_PI[28]~input (
- .i(GPIO_0_PI[28]),
- .ibar(gnd),
- .o(\GPIO_0_PI[28]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[28]~input .bus_hold = "false";
-defparam \GPIO_0_PI[28]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X40_Y34_N8
-cycloneive_io_ibuf \GPIO_0_PI[29]~input (
- .i(GPIO_0_PI[29]),
- .ibar(gnd),
- .o(\GPIO_0_PI[29]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[29]~input .bus_hold = "false";
-defparam \GPIO_0_PI[29]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X18_Y34_N1
-cycloneive_io_ibuf \GPIO_0_PI[30]~input (
- .i(GPIO_0_PI[30]),
- .ibar(gnd),
- .o(\GPIO_0_PI[30]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[30]~input .bus_hold = "false";
-defparam \GPIO_0_PI[30]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X23_Y34_N22
-cycloneive_io_ibuf \GPIO_0_PI[32]~input (
- .i(GPIO_0_PI[32]),
- .ibar(gnd),
- .o(\GPIO_0_PI[32]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[32]~input .bus_hold = "false";
-defparam \GPIO_0_PI[32]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y22_N1
-cycloneive_io_ibuf \GPIO_0_PI[33]~input (
- .i(GPIO_0_PI[33]),
- .ibar(gnd),
- .o(\GPIO_0_PI[33]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[33]~input .bus_hold = "false";
-defparam \GPIO_0_PI[33]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X14_Y0_N1
-cycloneive_io_ibuf \GPIO_1[0]~input (
- .i(GPIO_1[0]),
- .ibar(gnd),
- .o(\GPIO_1[0]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[0]~input .bus_hold = "false";
-defparam \GPIO_1[0]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X1_Y0_N22
-cycloneive_io_ibuf \GPIO_1[1]~input (
- .i(GPIO_1[1]),
- .ibar(gnd),
- .o(\GPIO_1[1]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[1]~input .bus_hold = "false";
-defparam \GPIO_1[1]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y20_N22
-cycloneive_io_ibuf \GPIO_1[2]~input (
- .i(GPIO_1[2]),
- .ibar(gnd),
- .o(\GPIO_1[2]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[2]~input .bus_hold = "false";
-defparam \GPIO_1[2]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y23_N1
-cycloneive_io_ibuf \GPIO_1[3]~input (
- .i(GPIO_1[3]),
- .ibar(gnd),
- .o(\GPIO_1[3]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[3]~input .bus_hold = "false";
-defparam \GPIO_1[3]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X7_Y34_N1
-cycloneive_io_ibuf \GPIO_1[4]~input (
- .i(GPIO_1[4]),
- .ibar(gnd),
- .o(\GPIO_1[4]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[4]~input .bus_hold = "false";
-defparam \GPIO_1[4]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y11_N1
-cycloneive_io_ibuf \GPIO_1[5]~input (
- .i(GPIO_1[5]),
- .ibar(gnd),
- .o(\GPIO_1[5]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[5]~input .bus_hold = "false";
-defparam \GPIO_1[5]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X51_Y34_N8
-cycloneive_io_ibuf \GPIO_1[6]~input (
- .i(GPIO_1[6]),
- .ibar(gnd),
- .o(\GPIO_1[6]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[6]~input .bus_hold = "false";
-defparam \GPIO_1[6]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X5_Y0_N8
-cycloneive_io_ibuf \GPIO_1[7]~input (
- .i(GPIO_1[7]),
- .ibar(gnd),
- .o(\GPIO_1[7]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[7]~input .bus_hold = "false";
-defparam \GPIO_1[7]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y22_N8
-cycloneive_io_ibuf \GPIO_1[8]~input (
- .i(GPIO_1[8]),
- .ibar(gnd),
- .o(\GPIO_1[8]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[8]~input .bus_hold = "false";
-defparam \GPIO_1[8]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X34_Y0_N1
-cycloneive_io_ibuf \GPIO_1[9]~input (
- .i(GPIO_1[9]),
- .ibar(gnd),
- .o(\GPIO_1[9]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[9]~input .bus_hold = "false";
-defparam \GPIO_1[9]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y11_N8
-cycloneive_io_ibuf \GPIO_1[10]~input (
- .i(GPIO_1[10]),
- .ibar(gnd),
- .o(\GPIO_1[10]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[10]~input .bus_hold = "false";
-defparam \GPIO_1[10]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X45_Y34_N8
-cycloneive_io_ibuf \GPIO_1[11]~input (
- .i(GPIO_1[11]),
- .ibar(gnd),
- .o(\GPIO_1[11]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[11]~input .bus_hold = "false";
-defparam \GPIO_1[11]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y26_N22
-cycloneive_io_ibuf \GPIO_1[12]~input (
- .i(GPIO_1[12]),
- .ibar(gnd),
- .o(\GPIO_1[12]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[12]~input .bus_hold = "false";
-defparam \GPIO_1[12]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X40_Y0_N15
-cycloneive_io_ibuf \GPIO_1[13]~input (
- .i(GPIO_1[13]),
- .ibar(gnd),
- .o(\GPIO_1[13]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[13]~input .bus_hold = "false";
-defparam \GPIO_1[13]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y12_N1
-cycloneive_io_ibuf \GPIO_1[14]~input (
- .i(GPIO_1[14]),
- .ibar(gnd),
- .o(\GPIO_1[14]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[14]~input .bus_hold = "false";
-defparam \GPIO_1[14]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y30_N1
-cycloneive_io_ibuf \GPIO_1[15]~input (
- .i(GPIO_1[15]),
- .ibar(gnd),
- .o(\GPIO_1[15]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[15]~input .bus_hold = "false";
-defparam \GPIO_1[15]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X25_Y0_N15
-cycloneive_io_ibuf \GPIO_1[16]~input (
- .i(GPIO_1[16]),
- .ibar(gnd),
- .o(\GPIO_1[16]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[16]~input .bus_hold = "false";
-defparam \GPIO_1[16]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X34_Y0_N22
-cycloneive_io_ibuf \GPIO_1[17]~input (
- .i(GPIO_1[17]),
- .ibar(gnd),
- .o(\GPIO_1[17]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[17]~input .bus_hold = "false";
-defparam \GPIO_1[17]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y7_N1
-cycloneive_io_ibuf \GPIO_1[18]~input (
- .i(GPIO_1[18]),
- .ibar(gnd),
- .o(\GPIO_1[18]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[18]~input .bus_hold = "false";
-defparam \GPIO_1[18]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y30_N8
-cycloneive_io_ibuf \GPIO_1[19]~input (
- .i(GPIO_1[19]),
- .ibar(gnd),
- .o(\GPIO_1[19]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[19]~input .bus_hold = "false";
-defparam \GPIO_1[19]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y27_N1
-cycloneive_io_ibuf \GPIO_1[20]~input (
- .i(GPIO_1[20]),
- .ibar(gnd),
- .o(\GPIO_1[20]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[20]~input .bus_hold = "false";
-defparam \GPIO_1[20]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X47_Y0_N22
-cycloneive_io_ibuf \GPIO_1[21]~input (
- .i(GPIO_1[21]),
- .ibar(gnd),
- .o(\GPIO_1[21]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[21]~input .bus_hold = "false";
-defparam \GPIO_1[21]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X11_Y34_N1
-cycloneive_io_ibuf \GPIO_1[22]~input (
- .i(GPIO_1[22]),
- .ibar(gnd),
- .o(\GPIO_1[22]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[22]~input .bus_hold = "false";
-defparam \GPIO_1[22]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X20_Y0_N8
-cycloneive_io_ibuf \GPIO_1[23]~input (
- .i(GPIO_1[23]),
- .ibar(gnd),
- .o(\GPIO_1[23]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[23]~input .bus_hold = "false";
-defparam \GPIO_1[23]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X5_Y0_N1
-cycloneive_io_ibuf \GPIO_1[24]~input (
- .i(GPIO_1[24]),
- .ibar(gnd),
- .o(\GPIO_1[24]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[24]~input .bus_hold = "false";
-defparam \GPIO_1[24]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y21_N22
-cycloneive_io_ibuf \GPIO_1[25]~input (
- .i(GPIO_1[25]),
- .ibar(gnd),
- .o(\GPIO_1[25]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[25]~input .bus_hold = "false";
-defparam \GPIO_1[25]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X1_Y0_N15
-cycloneive_io_ibuf \GPIO_1[26]~input (
- .i(GPIO_1[26]),
- .ibar(gnd),
- .o(\GPIO_1[26]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[26]~input .bus_hold = "false";
-defparam \GPIO_1[26]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X7_Y0_N8
-cycloneive_io_ibuf \GPIO_1[27]~input (
- .i(GPIO_1[27]),
- .ibar(gnd),
- .o(\GPIO_1[27]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[27]~input .bus_hold = "false";
-defparam \GPIO_1[27]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y23_N22
-cycloneive_io_ibuf \GPIO_1[28]~input (
- .i(GPIO_1[28]),
- .ibar(gnd),
- .o(\GPIO_1[28]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[28]~input .bus_hold = "false";
-defparam \GPIO_1[28]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y14_N8
-cycloneive_io_ibuf \GPIO_1[29]~input (
- .i(GPIO_1[29]),
- .ibar(gnd),
- .o(\GPIO_1[29]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[29]~input .bus_hold = "false";
-defparam \GPIO_1[29]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X45_Y0_N22
-cycloneive_io_ibuf \GPIO_1[30]~input (
- .i(GPIO_1[30]),
- .ibar(gnd),
- .o(\GPIO_1[30]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[30]~input .bus_hold = "false";
-defparam \GPIO_1[30]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X49_Y0_N1
-cycloneive_io_ibuf \GPIO_1[31]~input (
- .i(GPIO_1[31]),
- .ibar(gnd),
- .o(\GPIO_1[31]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[31]~input .bus_hold = "false";
-defparam \GPIO_1[31]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X31_Y34_N1
-cycloneive_io_ibuf \GPIO_1[32]~input (
- .i(GPIO_1[32]),
- .ibar(gnd),
- .o(\GPIO_1[32]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[32]~input .bus_hold = "false";
-defparam \GPIO_1[32]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y6_N15
-cycloneive_io_ibuf \GPIO_1[33]~input (
- .i(GPIO_1[33]),
- .ibar(gnd),
- .o(\GPIO_1[33]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[33]~input .bus_hold = "false";
-defparam \GPIO_1[33]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X16_Y34_N1
-cycloneive_io_ibuf \GPIO_0_PI[11]~input (
- .i(GPIO_0_PI[11]),
- .ibar(gnd),
- .o(\GPIO_0_PI[11]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[11]~input .bus_hold = "false";
-defparam \GPIO_0_PI[11]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-assign LED[0] = \LED[0]~output_o ;
-
-assign LED[1] = \LED[1]~output_o ;
-
-assign LED[2] = \LED[2]~output_o ;
-
-assign LED[3] = \LED[3]~output_o ;
-
-assign LED[4] = \LED[4]~output_o ;
-
-assign LED[5] = \LED[5]~output_o ;
-
-assign LED[6] = \LED[6]~output_o ;
-
-assign LED[7] = \LED[7]~output_o ;
-
-assign GPIO_2[0] = \GPIO_2[0]~output_o ;
-
-assign GPIO_2[1] = \GPIO_2[1]~output_o ;
-
-assign GPIO_2[2] = \GPIO_2[2]~output_o ;
-
-assign GPIO_2[3] = \GPIO_2[3]~output_o ;
-
-assign GPIO_2[4] = \GPIO_2[4]~output_o ;
-
-assign GPIO_2[5] = \GPIO_2[5]~output_o ;
-
-assign GPIO_2[6] = \GPIO_2[6]~output_o ;
-
-assign GPIO_2[7] = \GPIO_2[7]~output_o ;
-
-assign GPIO_2[8] = \GPIO_2[8]~output_o ;
-
-assign GPIO_2[9] = \GPIO_2[9]~output_o ;
-
-assign GPIO_2[10] = \GPIO_2[10]~output_o ;
-
-assign GPIO_2[11] = \GPIO_2[11]~output_o ;
-
-assign GPIO_2[12] = \GPIO_2[12]~output_o ;
-
-assign GPIO_0_PI[0] = \GPIO_0_PI[0]~output_o ;
-
-assign GPIO_0_PI[1] = \GPIO_0_PI[1]~output_o ;
-
-assign GPIO_0_PI[2] = \GPIO_0_PI[2]~output_o ;
-
-assign GPIO_0_PI[3] = \GPIO_0_PI[3]~output_o ;
-
-assign GPIO_0_PI[4] = \GPIO_0_PI[4]~output_o ;
-
-assign GPIO_0_PI[5] = \GPIO_0_PI[5]~output_o ;
-
-assign GPIO_0_PI[6] = \GPIO_0_PI[6]~output_o ;
-
-assign GPIO_0_PI[7] = \GPIO_0_PI[7]~output_o ;
-
-assign GPIO_0_PI[12] = \GPIO_0_PI[12]~output_o ;
-
-assign GPIO_0_PI[13] = \GPIO_0_PI[13]~output_o ;
-
-assign GPIO_0_PI[14] = \GPIO_0_PI[14]~output_o ;
-
-assign GPIO_0_PI[15] = \GPIO_0_PI[15]~output_o ;
-
-assign GPIO_0_PI[16] = \GPIO_0_PI[16]~output_o ;
-
-assign GPIO_0_PI[17] = \GPIO_0_PI[17]~output_o ;
-
-assign GPIO_0_PI[18] = \GPIO_0_PI[18]~output_o ;
-
-assign GPIO_0_PI[19] = \GPIO_0_PI[19]~output_o ;
-
-assign GPIO_0_PI[20] = \GPIO_0_PI[20]~output_o ;
-
-assign GPIO_0_PI[21] = \GPIO_0_PI[21]~output_o ;
-
-assign GPIO_0_PI[22] = \GPIO_0_PI[22]~output_o ;
-
-assign GPIO_0_PI[23] = \GPIO_0_PI[23]~output_o ;
-
-assign GPIO_0_PI[24] = \GPIO_0_PI[24]~output_o ;
-
-assign GPIO_0_PI[25] = \GPIO_0_PI[25]~output_o ;
-
-assign GPIO_0_PI[26] = \GPIO_0_PI[26]~output_o ;
-
-assign GPIO_0_PI[27] = \GPIO_0_PI[27]~output_o ;
-
-assign GPIO_0_PI[28] = \GPIO_0_PI[28]~output_o ;
-
-assign GPIO_0_PI[29] = \GPIO_0_PI[29]~output_o ;
-
-assign GPIO_0_PI[30] = \GPIO_0_PI[30]~output_o ;
-
-assign GPIO_0_PI[32] = \GPIO_0_PI[32]~output_o ;
-
-assign GPIO_0_PI[33] = \GPIO_0_PI[33]~output_o ;
-
-assign GPIO_1[0] = \GPIO_1[0]~output_o ;
-
-assign GPIO_1[1] = \GPIO_1[1]~output_o ;
-
-assign GPIO_1[2] = \GPIO_1[2]~output_o ;
-
-assign GPIO_1[3] = \GPIO_1[3]~output_o ;
-
-assign GPIO_1[4] = \GPIO_1[4]~output_o ;
-
-assign GPIO_1[5] = \GPIO_1[5]~output_o ;
-
-assign GPIO_1[6] = \GPIO_1[6]~output_o ;
-
-assign GPIO_1[7] = \GPIO_1[7]~output_o ;
-
-assign GPIO_1[8] = \GPIO_1[8]~output_o ;
-
-assign GPIO_1[9] = \GPIO_1[9]~output_o ;
-
-assign GPIO_1[10] = \GPIO_1[10]~output_o ;
-
-assign GPIO_1[11] = \GPIO_1[11]~output_o ;
-
-assign GPIO_1[12] = \GPIO_1[12]~output_o ;
-
-assign GPIO_1[13] = \GPIO_1[13]~output_o ;
-
-assign GPIO_1[14] = \GPIO_1[14]~output_o ;
-
-assign GPIO_1[15] = \GPIO_1[15]~output_o ;
-
-assign GPIO_1[16] = \GPIO_1[16]~output_o ;
-
-assign GPIO_1[17] = \GPIO_1[17]~output_o ;
-
-assign GPIO_1[18] = \GPIO_1[18]~output_o ;
-
-assign GPIO_1[19] = \GPIO_1[19]~output_o ;
-
-assign GPIO_1[20] = \GPIO_1[20]~output_o ;
-
-assign GPIO_1[21] = \GPIO_1[21]~output_o ;
-
-assign GPIO_1[22] = \GPIO_1[22]~output_o ;
-
-assign GPIO_1[23] = \GPIO_1[23]~output_o ;
-
-assign GPIO_1[24] = \GPIO_1[24]~output_o ;
-
-assign GPIO_1[25] = \GPIO_1[25]~output_o ;
-
-assign GPIO_1[26] = \GPIO_1[26]~output_o ;
-
-assign GPIO_1[27] = \GPIO_1[27]~output_o ;
-
-assign GPIO_1[28] = \GPIO_1[28]~output_o ;
-
-assign GPIO_1[29] = \GPIO_1[29]~output_o ;
-
-assign GPIO_1[30] = \GPIO_1[30]~output_o ;
-
-assign GPIO_1[31] = \GPIO_1[31]~output_o ;
-
-assign GPIO_1[32] = \GPIO_1[32]~output_o ;
-
-assign GPIO_1[33] = \GPIO_1[33]~output_o ;
-
-assign GPIO_0_PI[8] = \GPIO_0_PI[8]~output_o ;
-
-assign GPIO_0_PI[9] = \GPIO_0_PI[9]~output_o ;
-
-assign GPIO_0_PI[10] = \GPIO_0_PI[10]~output_o ;
-
-assign GPIO_0_PI[11] = \GPIO_0_PI[11]~output_o ;
-
-assign GPIO_0_PI[31] = \GPIO_0_PI[31]~output_o ;
-
-endmodule
-
-module hard_block (
-
- devpor,
- devclrn,
- devoe);
-
-// Design Ports Information
-// ~ALTERA_ASDO_DATA1~ => Location: PIN_C1, I/O Standard: 2.5 V, Current Strength: Default
-// ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_D2, I/O Standard: 2.5 V, Current Strength: Default
-// ~ALTERA_DCLK~ => Location: PIN_H1, I/O Standard: 2.5 V, Current Strength: Default
-// ~ALTERA_DATA0~ => Location: PIN_H2, I/O Standard: 2.5 V, Current Strength: Default
-// ~ALTERA_nCEO~ => Location: PIN_F16, I/O Standard: 2.5 V, Current Strength: 8mA
-
-input devpor;
-input devclrn;
-input devoe;
-
-wire gnd;
-wire vcc;
-wire unknown;
-
-assign gnd = 1'b0;
-assign vcc = 1'b1;
-assign unknown = 1'bx;
-
-wire \~ALTERA_ASDO_DATA1~~padout ;
-wire \~ALTERA_FLASH_nCE_nCSO~~padout ;
-wire \~ALTERA_DATA0~~padout ;
-wire \~ALTERA_ASDO_DATA1~~ibuf_o ;
-wire \~ALTERA_FLASH_nCE_nCSO~~ibuf_o ;
-wire \~ALTERA_DATA0~~ibuf_o ;
-
-
-endmodule
diff --git a/SPI/simulation/modelsim/SPI_test_6_1200mv_0c_slow.svo b/SPI/simulation/modelsim/SPI_test_6_1200mv_0c_slow.svo
deleted file mode 100644
index 7c4b3b0c90139bb9ef1c042cd1bd99d1f144e489..0000000000000000000000000000000000000000
--- a/SPI/simulation/modelsim/SPI_test_6_1200mv_0c_slow.svo
+++ /dev/null
@@ -1,4083 +0,0 @@
-// Copyright (C) 2018 Intel Corporation. All rights reserved.
-// Your use of Intel Corporation's design tools, logic functions
-// and other software and tools, and its AMPP partner logic
-// functions, and any output files from any of the foregoing
-// (including device programming or simulation files), and any
-// associated documentation or information are expressly subject
-// to the terms and conditions of the Intel Program License
-// Subscription Agreement, the Intel Quartus Prime License Agreement,
-// the Intel FPGA IP License Agreement, or other applicable license
-// agreement, including, without limitation, that your use is for
-// the sole purpose of programming logic devices manufactured by
-// Intel and sold by Intel or its authorized distributors. Please
-// refer to the applicable agreement for further details.
-
-// VENDOR "Altera"
-// PROGRAM "Quartus Prime"
-// VERSION "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition"
-
-// DATE "11/16/2022 16:51:48"
-
-//
-// Device: Altera EP4CE22F17C6 Package FBGA256
-//
-
-//
-// This Verilog file should be used for ModelSim-Altera (SystemVerilog) only
-//
-
-`timescale 1 ps/ 1 ps
-
-module MyDE0_Nano (
- CLOCK_50,
- LED,
- KEY,
- GPIO_2,
- GPIO_2_IN,
- GPIO_0_PI,
- GPIO_0_PI_IN,
- GPIO_1,
- GPIO_1_IN);
-input CLOCK_50;
-output [7:0] LED;
-input [1:0] KEY;
-output [12:0] GPIO_2;
-input [2:0] GPIO_2_IN;
-output [33:0] GPIO_0_PI;
-input [1:0] GPIO_0_PI_IN;
-output [33:0] GPIO_1;
-input [1:0] GPIO_1_IN;
-
-// Design Ports Information
-// CLOCK_50 => Location: PIN_R7, I/O Standard: 2.5 V, Current Strength: Default
-// LED[0] => Location: PIN_A15, I/O Standard: 2.5 V, Current Strength: Default
-// LED[1] => Location: PIN_A13, I/O Standard: 2.5 V, Current Strength: Default
-// LED[2] => Location: PIN_B13, I/O Standard: 2.5 V, Current Strength: Default
-// LED[3] => Location: PIN_A11, I/O Standard: 2.5 V, Current Strength: Default
-// LED[4] => Location: PIN_D1, I/O Standard: 2.5 V, Current Strength: Default
-// LED[5] => Location: PIN_F3, I/O Standard: 2.5 V, Current Strength: Default
-// LED[6] => Location: PIN_B1, I/O Standard: 2.5 V, Current Strength: Default
-// LED[7] => Location: PIN_L3, I/O Standard: 2.5 V, Current Strength: Default
-// KEY[0] => Location: PIN_J15, I/O Standard: 2.5 V, Current Strength: Default
-// KEY[1] => Location: PIN_E1, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2_IN[0] => Location: PIN_E16, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2_IN[1] => Location: PIN_E15, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2_IN[2] => Location: PIN_D6, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI_IN[0] => Location: PIN_E6, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI_IN[1] => Location: PIN_C14, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1_IN[0] => Location: PIN_A12, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1_IN[1] => Location: PIN_T10, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[0] => Location: PIN_R4, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[1] => Location: PIN_D12, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[2] => Location: PIN_F2, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[3] => Location: PIN_G5, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[4] => Location: PIN_T4, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[5] => Location: PIN_J2, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[6] => Location: PIN_B3, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[7] => Location: PIN_D3, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[8] => Location: PIN_M7, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[9] => Location: PIN_T2, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[10] => Location: PIN_B12, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[11] => Location: PIN_C8, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[12] => Location: PIN_E8, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[0] => Location: PIN_A10, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[1] => Location: PIN_P2, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[2] => Location: PIN_R1, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[3] => Location: PIN_C6, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[4] => Location: PIN_T5, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[5] => Location: PIN_A5, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[6] => Location: PIN_P15, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[7] => Location: PIN_R5, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[12] => Location: PIN_P1, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[13] => Location: PIN_R16, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[14] => Location: PIN_C3, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[15] => Location: PIN_B10, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[16] => Location: PIN_F9, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[17] => Location: PIN_B6, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[18] => Location: PIN_R3, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[19] => Location: PIN_T12, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[20] => Location: PIN_J1, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[21] => Location: PIN_A14, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[22] => Location: PIN_R6, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[23] => Location: PIN_A7, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[24] => Location: PIN_B14, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[25] => Location: PIN_R13, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[26] => Location: PIN_L8, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[27] => Location: PIN_E10, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[28] => Location: PIN_C11, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[29] => Location: PIN_B11, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[30] => Location: PIN_B7, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[32] => Location: PIN_D8, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[33] => Location: PIN_B16, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[0] => Location: PIN_T6, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[1] => Location: PIN_N3, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[2] => Location: PIN_G16, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[3] => Location: PIN_F1, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[4] => Location: PIN_B4, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[5] => Location: PIN_L15, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[6] => Location: PIN_D14, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[7] => Location: PIN_N5, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[8] => Location: PIN_F15, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[9] => Location: PIN_R11, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[10] => Location: PIN_L1, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[11] => Location: PIN_E11, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[12] => Location: PIN_D15, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[13] => Location: PIN_T13, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[14] => Location: PIN_K16, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[15] => Location: PIN_C15, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[16] => Location: PIN_P8, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[17] => Location: PIN_R10, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[18] => Location: PIN_N1, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[19] => Location: PIN_C16, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[20] => Location: PIN_C2, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[21] => Location: PIN_N12, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[22] => Location: PIN_B5, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[23] => Location: PIN_M8, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[24] => Location: PIN_N6, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[25] => Location: PIN_F13, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[26] => Location: PIN_P3, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[27] => Location: PIN_M6, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[28] => Location: PIN_G1, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[29] => Location: PIN_J16, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[30] => Location: PIN_T14, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[31] => Location: PIN_R14, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[32] => Location: PIN_C9, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[33] => Location: PIN_L4, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[8] => Location: PIN_G2, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[9] => Location: PIN_D5, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[10] => Location: PIN_E7, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[11] => Location: PIN_A6, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[31] => Location: PIN_D11, I/O Standard: 2.5 V, Current Strength: Default
-
-
-wire gnd;
-wire vcc;
-wire unknown;
-
-assign gnd = 1'b0;
-assign vcc = 1'b1;
-assign unknown = 1'bx;
-
-tri1 devclrn;
-tri1 devpor;
-tri1 devoe;
-// synopsys translate_off
-initial $sdf_annotate("SPI_test_6_1200mv_0c_v_slow.sdo");
-// synopsys translate_on
-
-wire \CLOCK_50~input_o ;
-wire \KEY[0]~input_o ;
-wire \KEY[1]~input_o ;
-wire \GPIO_2_IN[0]~input_o ;
-wire \GPIO_2_IN[1]~input_o ;
-wire \GPIO_2_IN[2]~input_o ;
-wire \GPIO_0_PI_IN[0]~input_o ;
-wire \GPIO_0_PI_IN[1]~input_o ;
-wire \GPIO_1_IN[0]~input_o ;
-wire \GPIO_1_IN[1]~input_o ;
-wire \GPIO_2[0]~input_o ;
-wire \GPIO_2[1]~input_o ;
-wire \GPIO_2[2]~input_o ;
-wire \GPIO_2[3]~input_o ;
-wire \GPIO_2[4]~input_o ;
-wire \GPIO_2[5]~input_o ;
-wire \GPIO_2[6]~input_o ;
-wire \GPIO_2[7]~input_o ;
-wire \GPIO_2[8]~input_o ;
-wire \GPIO_2[9]~input_o ;
-wire \GPIO_2[10]~input_o ;
-wire \GPIO_2[11]~input_o ;
-wire \GPIO_2[12]~input_o ;
-wire \GPIO_0_PI[0]~input_o ;
-wire \GPIO_0_PI[1]~input_o ;
-wire \GPIO_0_PI[2]~input_o ;
-wire \GPIO_0_PI[3]~input_o ;
-wire \GPIO_0_PI[4]~input_o ;
-wire \GPIO_0_PI[5]~input_o ;
-wire \GPIO_0_PI[6]~input_o ;
-wire \GPIO_0_PI[7]~input_o ;
-wire \GPIO_0_PI[12]~input_o ;
-wire \GPIO_0_PI[13]~input_o ;
-wire \GPIO_0_PI[14]~input_o ;
-wire \GPIO_0_PI[15]~input_o ;
-wire \GPIO_0_PI[16]~input_o ;
-wire \GPIO_0_PI[17]~input_o ;
-wire \GPIO_0_PI[18]~input_o ;
-wire \GPIO_0_PI[19]~input_o ;
-wire \GPIO_0_PI[20]~input_o ;
-wire \GPIO_0_PI[21]~input_o ;
-wire \GPIO_0_PI[22]~input_o ;
-wire \GPIO_0_PI[23]~input_o ;
-wire \GPIO_0_PI[24]~input_o ;
-wire \GPIO_0_PI[25]~input_o ;
-wire \GPIO_0_PI[26]~input_o ;
-wire \GPIO_0_PI[27]~input_o ;
-wire \GPIO_0_PI[28]~input_o ;
-wire \GPIO_0_PI[29]~input_o ;
-wire \GPIO_0_PI[30]~input_o ;
-wire \GPIO_0_PI[32]~input_o ;
-wire \GPIO_0_PI[33]~input_o ;
-wire \GPIO_1[0]~input_o ;
-wire \GPIO_1[1]~input_o ;
-wire \GPIO_1[2]~input_o ;
-wire \GPIO_1[3]~input_o ;
-wire \GPIO_1[4]~input_o ;
-wire \GPIO_1[5]~input_o ;
-wire \GPIO_1[6]~input_o ;
-wire \GPIO_1[7]~input_o ;
-wire \GPIO_1[8]~input_o ;
-wire \GPIO_1[9]~input_o ;
-wire \GPIO_1[10]~input_o ;
-wire \GPIO_1[11]~input_o ;
-wire \GPIO_1[12]~input_o ;
-wire \GPIO_1[13]~input_o ;
-wire \GPIO_1[14]~input_o ;
-wire \GPIO_1[15]~input_o ;
-wire \GPIO_1[16]~input_o ;
-wire \GPIO_1[17]~input_o ;
-wire \GPIO_1[18]~input_o ;
-wire \GPIO_1[19]~input_o ;
-wire \GPIO_1[20]~input_o ;
-wire \GPIO_1[21]~input_o ;
-wire \GPIO_1[22]~input_o ;
-wire \GPIO_1[23]~input_o ;
-wire \GPIO_1[24]~input_o ;
-wire \GPIO_1[25]~input_o ;
-wire \GPIO_1[26]~input_o ;
-wire \GPIO_1[27]~input_o ;
-wire \GPIO_1[28]~input_o ;
-wire \GPIO_1[29]~input_o ;
-wire \GPIO_1[30]~input_o ;
-wire \GPIO_1[31]~input_o ;
-wire \GPIO_1[32]~input_o ;
-wire \GPIO_1[33]~input_o ;
-wire \GPIO_0_PI[11]~input_o ;
-wire \GPIO_2[0]~output_o ;
-wire \GPIO_2[1]~output_o ;
-wire \GPIO_2[2]~output_o ;
-wire \GPIO_2[3]~output_o ;
-wire \GPIO_2[4]~output_o ;
-wire \GPIO_2[5]~output_o ;
-wire \GPIO_2[6]~output_o ;
-wire \GPIO_2[7]~output_o ;
-wire \GPIO_2[8]~output_o ;
-wire \GPIO_2[9]~output_o ;
-wire \GPIO_2[10]~output_o ;
-wire \GPIO_2[11]~output_o ;
-wire \GPIO_2[12]~output_o ;
-wire \GPIO_0_PI[0]~output_o ;
-wire \GPIO_0_PI[1]~output_o ;
-wire \GPIO_0_PI[2]~output_o ;
-wire \GPIO_0_PI[3]~output_o ;
-wire \GPIO_0_PI[4]~output_o ;
-wire \GPIO_0_PI[5]~output_o ;
-wire \GPIO_0_PI[6]~output_o ;
-wire \GPIO_0_PI[7]~output_o ;
-wire \GPIO_0_PI[12]~output_o ;
-wire \GPIO_0_PI[13]~output_o ;
-wire \GPIO_0_PI[14]~output_o ;
-wire \GPIO_0_PI[15]~output_o ;
-wire \GPIO_0_PI[16]~output_o ;
-wire \GPIO_0_PI[17]~output_o ;
-wire \GPIO_0_PI[18]~output_o ;
-wire \GPIO_0_PI[19]~output_o ;
-wire \GPIO_0_PI[20]~output_o ;
-wire \GPIO_0_PI[21]~output_o ;
-wire \GPIO_0_PI[22]~output_o ;
-wire \GPIO_0_PI[23]~output_o ;
-wire \GPIO_0_PI[24]~output_o ;
-wire \GPIO_0_PI[25]~output_o ;
-wire \GPIO_0_PI[26]~output_o ;
-wire \GPIO_0_PI[27]~output_o ;
-wire \GPIO_0_PI[28]~output_o ;
-wire \GPIO_0_PI[29]~output_o ;
-wire \GPIO_0_PI[30]~output_o ;
-wire \GPIO_0_PI[32]~output_o ;
-wire \GPIO_0_PI[33]~output_o ;
-wire \GPIO_1[0]~output_o ;
-wire \GPIO_1[1]~output_o ;
-wire \GPIO_1[2]~output_o ;
-wire \GPIO_1[3]~output_o ;
-wire \GPIO_1[4]~output_o ;
-wire \GPIO_1[5]~output_o ;
-wire \GPIO_1[6]~output_o ;
-wire \GPIO_1[7]~output_o ;
-wire \GPIO_1[8]~output_o ;
-wire \GPIO_1[9]~output_o ;
-wire \GPIO_1[10]~output_o ;
-wire \GPIO_1[11]~output_o ;
-wire \GPIO_1[12]~output_o ;
-wire \GPIO_1[13]~output_o ;
-wire \GPIO_1[14]~output_o ;
-wire \GPIO_1[15]~output_o ;
-wire \GPIO_1[16]~output_o ;
-wire \GPIO_1[17]~output_o ;
-wire \GPIO_1[18]~output_o ;
-wire \GPIO_1[19]~output_o ;
-wire \GPIO_1[20]~output_o ;
-wire \GPIO_1[21]~output_o ;
-wire \GPIO_1[22]~output_o ;
-wire \GPIO_1[23]~output_o ;
-wire \GPIO_1[24]~output_o ;
-wire \GPIO_1[25]~output_o ;
-wire \GPIO_1[26]~output_o ;
-wire \GPIO_1[27]~output_o ;
-wire \GPIO_1[28]~output_o ;
-wire \GPIO_1[29]~output_o ;
-wire \GPIO_1[30]~output_o ;
-wire \GPIO_1[31]~output_o ;
-wire \GPIO_1[32]~output_o ;
-wire \GPIO_1[33]~output_o ;
-wire \GPIO_0_PI[8]~output_o ;
-wire \GPIO_0_PI[9]~output_o ;
-wire \GPIO_0_PI[10]~output_o ;
-wire \GPIO_0_PI[11]~output_o ;
-wire \GPIO_0_PI[31]~output_o ;
-wire \LED[0]~output_o ;
-wire \LED[1]~output_o ;
-wire \LED[2]~output_o ;
-wire \LED[3]~output_o ;
-wire \LED[4]~output_o ;
-wire \LED[5]~output_o ;
-wire \LED[6]~output_o ;
-wire \LED[7]~output_o ;
-wire \GPIO_0_PI[8]~input_o ;
-wire \GPIO_0_PI[8]~inputclkctrl_outclk ;
-wire \spi_slave_instance|cnt[0]~12_combout ;
-wire \spi_slave_instance|cnt[1]~4_combout ;
-wire \spi_slave_instance|cnt[1]~5 ;
-wire \spi_slave_instance|cnt[2]~6_combout ;
-wire \spi_slave_instance|cnt[2]~7 ;
-wire \spi_slave_instance|cnt[3]~8_combout ;
-wire \spi_slave_instance|cnt[3]~9 ;
-wire \spi_slave_instance|cnt[4]~10_combout ;
-wire \GPIO_0_PI[31]~input_o ;
-wire \GPIO_0_PI[9]~input_o ;
-wire \spi_slave_instance|Equal0~0_combout ;
-wire \spi_slave_instance|q~31_combout ;
-wire \spi_slave_instance|q~30_combout ;
-wire \spi_slave_instance|q~29_combout ;
-wire \spi_slave_instance|q~28_combout ;
-wire \spi_slave_instance|q~27_combout ;
-wire \spi_slave_instance|q~26_combout ;
-wire \spi_slave_instance|q~25_combout ;
-wire \spi_slave_instance|q~24_combout ;
-wire \spi_slave_instance|q~23_combout ;
-wire \spi_slave_instance|q~22_combout ;
-wire \spi_slave_instance|q~21_combout ;
-wire \spi_slave_instance|q~20_combout ;
-wire \spi_slave_instance|q~19_combout ;
-wire \spi_slave_instance|q~18_combout ;
-wire \spi_slave_instance|q~17_combout ;
-wire \spi_slave_instance|q~16_combout ;
-wire \spi_slave_instance|q~15_combout ;
-wire \spi_slave_instance|q~14_combout ;
-wire \spi_slave_instance|q~13_combout ;
-wire \spi_slave_instance|q~12_combout ;
-wire \spi_slave_instance|q~10_combout ;
-wire \spi_slave_instance|q~11_combout ;
-wire \spi_slave_instance|q~9_combout ;
-wire \spi_slave_instance|q~8_combout ;
-wire \spi_slave_instance|q~7_combout ;
-wire \spi_slave_instance|q~6_combout ;
-wire \spi_slave_instance|q~5_combout ;
-wire \spi_slave_instance|q~4_combout ;
-wire \spi_slave_instance|q~3_combout ;
-wire \spi_slave_instance|q~2_combout ;
-wire \spi_slave_instance|q~1_combout ;
-wire \spi_slave_instance|q~0_combout ;
-wire \spi_slave_instance|qdelayed~q ;
-wire \spi_slave_instance|miso~0_combout ;
-wire \GPIO_0_PI[10]~input_o ;
-wire [4:0] \spi_slave_instance|cnt ;
-wire [31:0] \spi_slave_instance|q ;
-
-
-hard_block auto_generated_inst(
- .devpor(devpor),
- .devclrn(devclrn),
- .devoe(devoe));
-
-// Location: IOOBUF_X5_Y0_N23
-cycloneive_io_obuf \GPIO_2[0]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[0]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[0]~output .bus_hold = "false";
-defparam \GPIO_2[0]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X51_Y34_N23
-cycloneive_io_obuf \GPIO_2[1]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[1]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[1]~output .bus_hold = "false";
-defparam \GPIO_2[1]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y24_N23
-cycloneive_io_obuf \GPIO_2[2]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[2]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[2]~output .bus_hold = "false";
-defparam \GPIO_2[2]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y24_N16
-cycloneive_io_obuf \GPIO_2[3]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[3]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[3]~output .bus_hold = "false";
-defparam \GPIO_2[3]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X5_Y0_N16
-cycloneive_io_obuf \GPIO_2[4]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[4]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[4]~output .bus_hold = "false";
-defparam \GPIO_2[4]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y15_N2
-cycloneive_io_obuf \GPIO_2[5]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[5]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[5]~output .bus_hold = "false";
-defparam \GPIO_2[5]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X3_Y34_N2
-cycloneive_io_obuf \GPIO_2[6]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[6]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[6]~output .bus_hold = "false";
-defparam \GPIO_2[6]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X1_Y34_N9
-cycloneive_io_obuf \GPIO_2[7]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[7]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[7]~output .bus_hold = "false";
-defparam \GPIO_2[7]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X11_Y0_N16
-cycloneive_io_obuf \GPIO_2[8]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[8]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[8]~output .bus_hold = "false";
-defparam \GPIO_2[8]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X3_Y0_N2
-cycloneive_io_obuf \GPIO_2[9]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[9]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[9]~output .bus_hold = "false";
-defparam \GPIO_2[9]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X43_Y34_N23
-cycloneive_io_obuf \GPIO_2[10]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[10]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[10]~output .bus_hold = "false";
-defparam \GPIO_2[10]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X23_Y34_N16
-cycloneive_io_obuf \GPIO_2[11]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[11]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[11]~output .bus_hold = "false";
-defparam \GPIO_2[11]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X20_Y34_N9
-cycloneive_io_obuf \GPIO_2[12]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[12]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[12]~output .bus_hold = "false";
-defparam \GPIO_2[12]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X34_Y34_N9
-cycloneive_io_obuf \GPIO_0_PI[0]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[0]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[0]~output .bus_hold = "false";
-defparam \GPIO_0_PI[0]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y4_N16
-cycloneive_io_obuf \GPIO_0_PI[1]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[1]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[1]~output .bus_hold = "false";
-defparam \GPIO_0_PI[1]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y5_N23
-cycloneive_io_obuf \GPIO_0_PI[2]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[2]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[2]~output .bus_hold = "false";
-defparam \GPIO_0_PI[2]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X18_Y34_N23
-cycloneive_io_obuf \GPIO_0_PI[3]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[3]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[3]~output .bus_hold = "false";
-defparam \GPIO_0_PI[3]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X14_Y0_N16
-cycloneive_io_obuf \GPIO_0_PI[4]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[4]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[4]~output .bus_hold = "false";
-defparam \GPIO_0_PI[4]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X14_Y34_N23
-cycloneive_io_obuf \GPIO_0_PI[5]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[5]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[5]~output .bus_hold = "false";
-defparam \GPIO_0_PI[5]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X53_Y6_N16
-cycloneive_io_obuf \GPIO_0_PI[6]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[6]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[6]~output .bus_hold = "false";
-defparam \GPIO_0_PI[6]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X14_Y0_N23
-cycloneive_io_obuf \GPIO_0_PI[7]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[7]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[7]~output .bus_hold = "false";
-defparam \GPIO_0_PI[7]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y4_N23
-cycloneive_io_obuf \GPIO_0_PI[12]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[12]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[12]~output .bus_hold = "false";
-defparam \GPIO_0_PI[12]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X53_Y8_N23
-cycloneive_io_obuf \GPIO_0_PI[13]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[13]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[13]~output .bus_hold = "false";
-defparam \GPIO_0_PI[13]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X1_Y34_N2
-cycloneive_io_obuf \GPIO_0_PI[14]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[14]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[14]~output .bus_hold = "false";
-defparam \GPIO_0_PI[14]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X34_Y34_N16
-cycloneive_io_obuf \GPIO_0_PI[15]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[15]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[15]~output .bus_hold = "false";
-defparam \GPIO_0_PI[15]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X34_Y34_N2
-cycloneive_io_obuf \GPIO_0_PI[16]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[16]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[16]~output .bus_hold = "false";
-defparam \GPIO_0_PI[16]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X16_Y34_N9
-cycloneive_io_obuf \GPIO_0_PI[17]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[17]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[17]~output .bus_hold = "false";
-defparam \GPIO_0_PI[17]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X1_Y0_N9
-cycloneive_io_obuf \GPIO_0_PI[18]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[18]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[18]~output .bus_hold = "false";
-defparam \GPIO_0_PI[18]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X36_Y0_N9
-cycloneive_io_obuf \GPIO_0_PI[19]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[19]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[19]~output .bus_hold = "false";
-defparam \GPIO_0_PI[19]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y15_N9
-cycloneive_io_obuf \GPIO_0_PI[20]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[20]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[20]~output .bus_hold = "false";
-defparam \GPIO_0_PI[20]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X47_Y34_N23
-cycloneive_io_obuf \GPIO_0_PI[21]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[21]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[21]~output .bus_hold = "false";
-defparam \GPIO_0_PI[21]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X14_Y0_N9
-cycloneive_io_obuf \GPIO_0_PI[22]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[22]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[22]~output .bus_hold = "false";
-defparam \GPIO_0_PI[22]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X20_Y34_N23
-cycloneive_io_obuf \GPIO_0_PI[23]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[23]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[23]~output .bus_hold = "false";
-defparam \GPIO_0_PI[23]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X45_Y34_N2
-cycloneive_io_obuf \GPIO_0_PI[24]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[24]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[24]~output .bus_hold = "false";
-defparam \GPIO_0_PI[24]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X40_Y0_N23
-cycloneive_io_obuf \GPIO_0_PI[25]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[25]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[25]~output .bus_hold = "false";
-defparam \GPIO_0_PI[25]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X18_Y0_N9
-cycloneive_io_obuf \GPIO_0_PI[26]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[26]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[26]~output .bus_hold = "false";
-defparam \GPIO_0_PI[26]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X45_Y34_N16
-cycloneive_io_obuf \GPIO_0_PI[27]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[27]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[27]~output .bus_hold = "false";
-defparam \GPIO_0_PI[27]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X38_Y34_N2
-cycloneive_io_obuf \GPIO_0_PI[28]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[28]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[28]~output .bus_hold = "false";
-defparam \GPIO_0_PI[28]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X40_Y34_N9
-cycloneive_io_obuf \GPIO_0_PI[29]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[29]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[29]~output .bus_hold = "false";
-defparam \GPIO_0_PI[29]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X18_Y34_N2
-cycloneive_io_obuf \GPIO_0_PI[30]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[30]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[30]~output .bus_hold = "false";
-defparam \GPIO_0_PI[30]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X23_Y34_N23
-cycloneive_io_obuf \GPIO_0_PI[32]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[32]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[32]~output .bus_hold = "false";
-defparam \GPIO_0_PI[32]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X53_Y22_N2
-cycloneive_io_obuf \GPIO_0_PI[33]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[33]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[33]~output .bus_hold = "false";
-defparam \GPIO_0_PI[33]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X14_Y0_N2
-cycloneive_io_obuf \GPIO_1[0]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[0]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[0]~output .bus_hold = "false";
-defparam \GPIO_1[0]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X1_Y0_N23
-cycloneive_io_obuf \GPIO_1[1]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[1]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[1]~output .bus_hold = "false";
-defparam \GPIO_1[1]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X53_Y20_N23
-cycloneive_io_obuf \GPIO_1[2]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[2]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[2]~output .bus_hold = "false";
-defparam \GPIO_1[2]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y23_N2
-cycloneive_io_obuf \GPIO_1[3]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[3]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[3]~output .bus_hold = "false";
-defparam \GPIO_1[3]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X7_Y34_N2
-cycloneive_io_obuf \GPIO_1[4]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[4]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[4]~output .bus_hold = "false";
-defparam \GPIO_1[4]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X53_Y11_N2
-cycloneive_io_obuf \GPIO_1[5]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[5]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[5]~output .bus_hold = "false";
-defparam \GPIO_1[5]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X51_Y34_N9
-cycloneive_io_obuf \GPIO_1[6]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[6]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[6]~output .bus_hold = "false";
-defparam \GPIO_1[6]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X5_Y0_N9
-cycloneive_io_obuf \GPIO_1[7]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[7]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[7]~output .bus_hold = "false";
-defparam \GPIO_1[7]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X53_Y22_N9
-cycloneive_io_obuf \GPIO_1[8]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[8]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[8]~output .bus_hold = "false";
-defparam \GPIO_1[8]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X34_Y0_N2
-cycloneive_io_obuf \GPIO_1[9]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[9]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[9]~output .bus_hold = "false";
-defparam \GPIO_1[9]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y11_N9
-cycloneive_io_obuf \GPIO_1[10]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[10]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[10]~output .bus_hold = "false";
-defparam \GPIO_1[10]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X45_Y34_N9
-cycloneive_io_obuf \GPIO_1[11]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[11]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[11]~output .bus_hold = "false";
-defparam \GPIO_1[11]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X53_Y26_N23
-cycloneive_io_obuf \GPIO_1[12]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[12]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[12]~output .bus_hold = "false";
-defparam \GPIO_1[12]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X40_Y0_N16
-cycloneive_io_obuf \GPIO_1[13]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[13]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[13]~output .bus_hold = "false";
-defparam \GPIO_1[13]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X53_Y12_N2
-cycloneive_io_obuf \GPIO_1[14]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[14]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[14]~output .bus_hold = "false";
-defparam \GPIO_1[14]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X53_Y30_N2
-cycloneive_io_obuf \GPIO_1[15]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[15]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[15]~output .bus_hold = "false";
-defparam \GPIO_1[15]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X25_Y0_N16
-cycloneive_io_obuf \GPIO_1[16]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[16]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[16]~output .bus_hold = "false";
-defparam \GPIO_1[16]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X34_Y0_N23
-cycloneive_io_obuf \GPIO_1[17]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[17]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[17]~output .bus_hold = "false";
-defparam \GPIO_1[17]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y7_N2
-cycloneive_io_obuf \GPIO_1[18]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[18]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[18]~output .bus_hold = "false";
-defparam \GPIO_1[18]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X53_Y30_N9
-cycloneive_io_obuf \GPIO_1[19]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[19]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[19]~output .bus_hold = "false";
-defparam \GPIO_1[19]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y27_N2
-cycloneive_io_obuf \GPIO_1[20]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[20]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[20]~output .bus_hold = "false";
-defparam \GPIO_1[20]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X47_Y0_N23
-cycloneive_io_obuf \GPIO_1[21]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[21]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[21]~output .bus_hold = "false";
-defparam \GPIO_1[21]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X11_Y34_N2
-cycloneive_io_obuf \GPIO_1[22]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[22]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[22]~output .bus_hold = "false";
-defparam \GPIO_1[22]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X20_Y0_N9
-cycloneive_io_obuf \GPIO_1[23]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[23]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[23]~output .bus_hold = "false";
-defparam \GPIO_1[23]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X5_Y0_N2
-cycloneive_io_obuf \GPIO_1[24]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[24]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[24]~output .bus_hold = "false";
-defparam \GPIO_1[24]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X53_Y21_N23
-cycloneive_io_obuf \GPIO_1[25]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[25]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[25]~output .bus_hold = "false";
-defparam \GPIO_1[25]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X1_Y0_N16
-cycloneive_io_obuf \GPIO_1[26]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[26]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[26]~output .bus_hold = "false";
-defparam \GPIO_1[26]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X7_Y0_N9
-cycloneive_io_obuf \GPIO_1[27]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[27]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[27]~output .bus_hold = "false";
-defparam \GPIO_1[27]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y23_N23
-cycloneive_io_obuf \GPIO_1[28]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[28]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[28]~output .bus_hold = "false";
-defparam \GPIO_1[28]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X53_Y14_N9
-cycloneive_io_obuf \GPIO_1[29]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[29]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[29]~output .bus_hold = "false";
-defparam \GPIO_1[29]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X45_Y0_N23
-cycloneive_io_obuf \GPIO_1[30]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[30]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[30]~output .bus_hold = "false";
-defparam \GPIO_1[30]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X49_Y0_N2
-cycloneive_io_obuf \GPIO_1[31]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[31]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[31]~output .bus_hold = "false";
-defparam \GPIO_1[31]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X31_Y34_N2
-cycloneive_io_obuf \GPIO_1[32]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[32]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[32]~output .bus_hold = "false";
-defparam \GPIO_1[32]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y6_N16
-cycloneive_io_obuf \GPIO_1[33]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[33]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[33]~output .bus_hold = "false";
-defparam \GPIO_1[33]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y23_N16
-cycloneive_io_obuf \GPIO_0_PI[8]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[8]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[8]~output .bus_hold = "false";
-defparam \GPIO_0_PI[8]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X5_Y34_N16
-cycloneive_io_obuf \GPIO_0_PI[9]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[9]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[9]~output .bus_hold = "false";
-defparam \GPIO_0_PI[9]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X16_Y34_N16
-cycloneive_io_obuf \GPIO_0_PI[10]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[10]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[10]~output .bus_hold = "false";
-defparam \GPIO_0_PI[10]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X16_Y34_N2
-cycloneive_io_obuf \GPIO_0_PI[11]~output (
- .i(\spi_slave_instance|miso~0_combout ),
- .oe(!\GPIO_0_PI[10]~input_o ),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[11]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[11]~output .bus_hold = "false";
-defparam \GPIO_0_PI[11]~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X51_Y34_N16
-cycloneive_io_obuf \GPIO_0_PI[31]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[31]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[31]~output .bus_hold = "false";
-defparam \GPIO_0_PI[31]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X38_Y34_N16
-cycloneive_io_obuf \LED[0]~output (
- .i(gnd),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\LED[0]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \LED[0]~output .bus_hold = "false";
-defparam \LED[0]~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X49_Y34_N2
-cycloneive_io_obuf \LED[1]~output (
- .i(gnd),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\LED[1]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \LED[1]~output .bus_hold = "false";
-defparam \LED[1]~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X49_Y34_N9
-cycloneive_io_obuf \LED[2]~output (
- .i(gnd),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\LED[2]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \LED[2]~output .bus_hold = "false";
-defparam \LED[2]~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X40_Y34_N2
-cycloneive_io_obuf \LED[3]~output (
- .i(gnd),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\LED[3]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \LED[3]~output .bus_hold = "false";
-defparam \LED[3]~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y25_N9
-cycloneive_io_obuf \LED[4]~output (
- .i(gnd),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\LED[4]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \LED[4]~output .bus_hold = "false";
-defparam \LED[4]~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y26_N16
-cycloneive_io_obuf \LED[5]~output (
- .i(gnd),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\LED[5]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \LED[5]~output .bus_hold = "false";
-defparam \LED[5]~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y28_N9
-cycloneive_io_obuf \LED[6]~output (
- .i(gnd),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\LED[6]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \LED[6]~output .bus_hold = "false";
-defparam \LED[6]~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y10_N23
-cycloneive_io_obuf \LED[7]~output (
- .i(gnd),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\LED[7]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \LED[7]~output .bus_hold = "false";
-defparam \LED[7]~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y23_N15
-cycloneive_io_ibuf \GPIO_0_PI[8]~input (
- .i(GPIO_0_PI[8]),
- .ibar(gnd),
- .o(\GPIO_0_PI[8]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[8]~input .bus_hold = "false";
-defparam \GPIO_0_PI[8]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: CLKCTRL_G0
-cycloneive_clkctrl \GPIO_0_PI[8]~inputclkctrl (
- .ena(vcc),
- .inclk({vcc,vcc,vcc,\GPIO_0_PI[8]~input_o }),
- .clkselect(2'b00),
- .devclrn(devclrn),
- .devpor(devpor),
- .outclk(\GPIO_0_PI[8]~inputclkctrl_outclk ));
-// synopsys translate_off
-defparam \GPIO_0_PI[8]~inputclkctrl .clock_type = "global clock";
-defparam \GPIO_0_PI[8]~inputclkctrl .ena_register_mode = "none";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N12
-cycloneive_lcell_comb \spi_slave_instance|cnt[0]~12 (
-// Equation(s):
-// \spi_slave_instance|cnt[0]~12_combout = !\spi_slave_instance|cnt [0]
-
- .dataa(gnd),
- .datab(gnd),
- .datac(\spi_slave_instance|cnt [0]),
- .datad(gnd),
- .cin(gnd),
- .combout(\spi_slave_instance|cnt[0]~12_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|cnt[0]~12 .lut_mask = 16'h0F0F;
-defparam \spi_slave_instance|cnt[0]~12 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N13
-dffeas \spi_slave_instance|cnt[0] (
- .clk(!\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|cnt[0]~12_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|cnt [0]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|cnt[0] .is_wysiwyg = "true";
-defparam \spi_slave_instance|cnt[0] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N2
-cycloneive_lcell_comb \spi_slave_instance|cnt[1]~4 (
-// Equation(s):
-// \spi_slave_instance|cnt[1]~4_combout = (\spi_slave_instance|cnt [0] & (\spi_slave_instance|cnt [1] $ (VCC))) # (!\spi_slave_instance|cnt [0] & (\spi_slave_instance|cnt [1] & VCC))
-// \spi_slave_instance|cnt[1]~5 = CARRY((\spi_slave_instance|cnt [0] & \spi_slave_instance|cnt [1]))
-
- .dataa(\spi_slave_instance|cnt [0]),
- .datab(\spi_slave_instance|cnt [1]),
- .datac(gnd),
- .datad(vcc),
- .cin(gnd),
- .combout(\spi_slave_instance|cnt[1]~4_combout ),
- .cout(\spi_slave_instance|cnt[1]~5 ));
-// synopsys translate_off
-defparam \spi_slave_instance|cnt[1]~4 .lut_mask = 16'h6688;
-defparam \spi_slave_instance|cnt[1]~4 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N3
-dffeas \spi_slave_instance|cnt[1] (
- .clk(!\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|cnt[1]~4_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|cnt [1]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|cnt[1] .is_wysiwyg = "true";
-defparam \spi_slave_instance|cnt[1] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N4
-cycloneive_lcell_comb \spi_slave_instance|cnt[2]~6 (
-// Equation(s):
-// \spi_slave_instance|cnt[2]~6_combout = (\spi_slave_instance|cnt [2] & (!\spi_slave_instance|cnt[1]~5 )) # (!\spi_slave_instance|cnt [2] & ((\spi_slave_instance|cnt[1]~5 ) # (GND)))
-// \spi_slave_instance|cnt[2]~7 = CARRY((!\spi_slave_instance|cnt[1]~5 ) # (!\spi_slave_instance|cnt [2]))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|cnt [2]),
- .datac(gnd),
- .datad(vcc),
- .cin(\spi_slave_instance|cnt[1]~5 ),
- .combout(\spi_slave_instance|cnt[2]~6_combout ),
- .cout(\spi_slave_instance|cnt[2]~7 ));
-// synopsys translate_off
-defparam \spi_slave_instance|cnt[2]~6 .lut_mask = 16'h3C3F;
-defparam \spi_slave_instance|cnt[2]~6 .sum_lutc_input = "cin";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N5
-dffeas \spi_slave_instance|cnt[2] (
- .clk(!\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|cnt[2]~6_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|cnt [2]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|cnt[2] .is_wysiwyg = "true";
-defparam \spi_slave_instance|cnt[2] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N6
-cycloneive_lcell_comb \spi_slave_instance|cnt[3]~8 (
-// Equation(s):
-// \spi_slave_instance|cnt[3]~8_combout = (\spi_slave_instance|cnt [3] & (\spi_slave_instance|cnt[2]~7 $ (GND))) # (!\spi_slave_instance|cnt [3] & (!\spi_slave_instance|cnt[2]~7 & VCC))
-// \spi_slave_instance|cnt[3]~9 = CARRY((\spi_slave_instance|cnt [3] & !\spi_slave_instance|cnt[2]~7 ))
-
- .dataa(\spi_slave_instance|cnt [3]),
- .datab(gnd),
- .datac(gnd),
- .datad(vcc),
- .cin(\spi_slave_instance|cnt[2]~7 ),
- .combout(\spi_slave_instance|cnt[3]~8_combout ),
- .cout(\spi_slave_instance|cnt[3]~9 ));
-// synopsys translate_off
-defparam \spi_slave_instance|cnt[3]~8 .lut_mask = 16'hA50A;
-defparam \spi_slave_instance|cnt[3]~8 .sum_lutc_input = "cin";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N7
-dffeas \spi_slave_instance|cnt[3] (
- .clk(!\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|cnt[3]~8_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|cnt [3]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|cnt[3] .is_wysiwyg = "true";
-defparam \spi_slave_instance|cnt[3] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N8
-cycloneive_lcell_comb \spi_slave_instance|cnt[4]~10 (
-// Equation(s):
-// \spi_slave_instance|cnt[4]~10_combout = \spi_slave_instance|cnt [4] $ (\spi_slave_instance|cnt[3]~9 )
-
- .dataa(gnd),
- .datab(\spi_slave_instance|cnt [4]),
- .datac(gnd),
- .datad(gnd),
- .cin(\spi_slave_instance|cnt[3]~9 ),
- .combout(\spi_slave_instance|cnt[4]~10_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|cnt[4]~10 .lut_mask = 16'h3C3C;
-defparam \spi_slave_instance|cnt[4]~10 .sum_lutc_input = "cin";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N9
-dffeas \spi_slave_instance|cnt[4] (
- .clk(!\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|cnt[4]~10_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|cnt [4]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|cnt[4] .is_wysiwyg = "true";
-defparam \spi_slave_instance|cnt[4] .power_up = "low";
-// synopsys translate_on
-
-// Location: IOIBUF_X51_Y34_N15
-cycloneive_io_ibuf \GPIO_0_PI[31]~input (
- .i(GPIO_0_PI[31]),
- .ibar(gnd),
- .o(\GPIO_0_PI[31]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[31]~input .bus_hold = "false";
-defparam \GPIO_0_PI[31]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X5_Y34_N15
-cycloneive_io_ibuf \GPIO_0_PI[9]~input (
- .i(GPIO_0_PI[9]),
- .ibar(gnd),
- .o(\GPIO_0_PI[9]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[9]~input .bus_hold = "false";
-defparam \GPIO_0_PI[9]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: FF_X21_Y31_N5
-dffeas \spi_slave_instance|q[0] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(gnd),
- .asdata(\GPIO_0_PI[9]~input_o ),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(vcc),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [0]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[0] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[0] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N18
-cycloneive_lcell_comb \spi_slave_instance|Equal0~0 (
-// Equation(s):
-// \spi_slave_instance|Equal0~0_combout = (!\spi_slave_instance|cnt [0] & (!\spi_slave_instance|cnt [1] & (!\spi_slave_instance|cnt [2] & !\spi_slave_instance|cnt [3])))
-
- .dataa(\spi_slave_instance|cnt [0]),
- .datab(\spi_slave_instance|cnt [1]),
- .datac(\spi_slave_instance|cnt [2]),
- .datad(\spi_slave_instance|cnt [3]),
- .cin(gnd),
- .combout(\spi_slave_instance|Equal0~0_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|Equal0~0 .lut_mask = 16'h0001;
-defparam \spi_slave_instance|Equal0~0 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: LCCOMB_X21_Y31_N22
-cycloneive_lcell_comb \spi_slave_instance|q~31 (
-// Equation(s):
-// \spi_slave_instance|q~31_combout = (\spi_slave_instance|cnt [4] & (((\spi_slave_instance|q [0])))) # (!\spi_slave_instance|cnt [4] & ((\spi_slave_instance|Equal0~0_combout & (\GPIO_0_PI[31]~input_o )) # (!\spi_slave_instance|Equal0~0_combout &
-// ((\spi_slave_instance|q [0])))))
-
- .dataa(\spi_slave_instance|cnt [4]),
- .datab(\GPIO_0_PI[31]~input_o ),
- .datac(\spi_slave_instance|q [0]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~31_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~31 .lut_mask = 16'hE4F0;
-defparam \spi_slave_instance|q~31 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X21_Y31_N23
-dffeas \spi_slave_instance|q[1] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~31_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [1]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[1] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[1] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X21_Y31_N24
-cycloneive_lcell_comb \spi_slave_instance|q~30 (
-// Equation(s):
-// \spi_slave_instance|q~30_combout = (\spi_slave_instance|q [1] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(\spi_slave_instance|cnt [4]),
- .datab(gnd),
- .datac(\spi_slave_instance|q [1]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~30_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~30 .lut_mask = 16'hA0F0;
-defparam \spi_slave_instance|q~30 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X21_Y31_N25
-dffeas \spi_slave_instance|q[2] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~30_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [2]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[2] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[2] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X21_Y31_N30
-cycloneive_lcell_comb \spi_slave_instance|q~29 (
-// Equation(s):
-// \spi_slave_instance|q~29_combout = (\spi_slave_instance|q [2] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(\spi_slave_instance|cnt [4]),
- .datab(\spi_slave_instance|q [2]),
- .datac(gnd),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~29_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~29 .lut_mask = 16'h88CC;
-defparam \spi_slave_instance|q~29 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X21_Y31_N31
-dffeas \spi_slave_instance|q[3] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~29_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [3]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[3] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[3] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X21_Y31_N8
-cycloneive_lcell_comb \spi_slave_instance|q~28 (
-// Equation(s):
-// \spi_slave_instance|q~28_combout = (\spi_slave_instance|q [3] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(\spi_slave_instance|cnt [4]),
- .datab(gnd),
- .datac(\spi_slave_instance|q [3]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~28_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~28 .lut_mask = 16'hA0F0;
-defparam \spi_slave_instance|q~28 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X21_Y31_N9
-dffeas \spi_slave_instance|q[4] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~28_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [4]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[4] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[4] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X21_Y31_N18
-cycloneive_lcell_comb \spi_slave_instance|q~27 (
-// Equation(s):
-// \spi_slave_instance|q~27_combout = (\spi_slave_instance|q [4] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(\spi_slave_instance|cnt [4]),
- .datab(gnd),
- .datac(\spi_slave_instance|q [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~27_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~27 .lut_mask = 16'hA0F0;
-defparam \spi_slave_instance|q~27 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X21_Y31_N19
-dffeas \spi_slave_instance|q[5] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~27_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [5]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[5] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[5] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X21_Y31_N28
-cycloneive_lcell_comb \spi_slave_instance|q~26 (
-// Equation(s):
-// \spi_slave_instance|q~26_combout = (\spi_slave_instance|q [5] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(\spi_slave_instance|cnt [4]),
- .datab(\spi_slave_instance|q [5]),
- .datac(gnd),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~26_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~26 .lut_mask = 16'h88CC;
-defparam \spi_slave_instance|q~26 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X21_Y31_N29
-dffeas \spi_slave_instance|q[6] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~26_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [6]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[6] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[6] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X21_Y31_N10
-cycloneive_lcell_comb \spi_slave_instance|q~25 (
-// Equation(s):
-// \spi_slave_instance|q~25_combout = (\spi_slave_instance|q [6] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(\spi_slave_instance|cnt [4]),
- .datab(\spi_slave_instance|q [6]),
- .datac(gnd),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~25_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~25 .lut_mask = 16'h88CC;
-defparam \spi_slave_instance|q~25 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X21_Y31_N11
-dffeas \spi_slave_instance|q[7] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~25_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [7]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[7] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[7] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N14
-cycloneive_lcell_comb \spi_slave_instance|q~24 (
-// Equation(s):
-// \spi_slave_instance|q~24_combout = (\spi_slave_instance|q [7] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|cnt [4]),
- .datac(\spi_slave_instance|q [7]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~24_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~24 .lut_mask = 16'hC0F0;
-defparam \spi_slave_instance|q~24 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N15
-dffeas \spi_slave_instance|q[8] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~24_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [8]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[8] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[8] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N28
-cycloneive_lcell_comb \spi_slave_instance|q~23 (
-// Equation(s):
-// \spi_slave_instance|q~23_combout = (\spi_slave_instance|q [8] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|q [8]),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~23_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~23 .lut_mask = 16'hC0CC;
-defparam \spi_slave_instance|q~23 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N29
-dffeas \spi_slave_instance|q[9] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~23_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [9]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[9] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[9] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N30
-cycloneive_lcell_comb \spi_slave_instance|q~22 (
-// Equation(s):
-// \spi_slave_instance|q~22_combout = (\spi_slave_instance|q [9] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|q [9]),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~22_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~22 .lut_mask = 16'hC0CC;
-defparam \spi_slave_instance|q~22 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N31
-dffeas \spi_slave_instance|q[10] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~22_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [10]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[10] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[10] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N24
-cycloneive_lcell_comb \spi_slave_instance|q~21 (
-// Equation(s):
-// \spi_slave_instance|q~21_combout = (\spi_slave_instance|q [10] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|cnt [4]),
- .datac(\spi_slave_instance|q [10]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~21_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~21 .lut_mask = 16'hC0F0;
-defparam \spi_slave_instance|q~21 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N25
-dffeas \spi_slave_instance|q[11] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~21_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [11]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[11] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[11] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N26
-cycloneive_lcell_comb \spi_slave_instance|q~20 (
-// Equation(s):
-// \spi_slave_instance|q~20_combout = (\spi_slave_instance|q [11] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|q [11]),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~20_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~20 .lut_mask = 16'hC0CC;
-defparam \spi_slave_instance|q~20 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N27
-dffeas \spi_slave_instance|q[12] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~20_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [12]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[12] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[12] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X21_Y31_N20
-cycloneive_lcell_comb \spi_slave_instance|q~19 (
-// Equation(s):
-// \spi_slave_instance|q~19_combout = (\spi_slave_instance|q [12] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(\spi_slave_instance|cnt [4]),
- .datab(gnd),
- .datac(\spi_slave_instance|q [12]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~19_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~19 .lut_mask = 16'hA0F0;
-defparam \spi_slave_instance|q~19 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X21_Y31_N21
-dffeas \spi_slave_instance|q[13] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~19_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [13]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[13] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[13] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N16
-cycloneive_lcell_comb \spi_slave_instance|q~18 (
-// Equation(s):
-// \spi_slave_instance|q~18_combout = (\spi_slave_instance|q [13] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|cnt [4]),
- .datac(\spi_slave_instance|q [13]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~18_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~18 .lut_mask = 16'hC0F0;
-defparam \spi_slave_instance|q~18 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N17
-dffeas \spi_slave_instance|q[14] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~18_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [14]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[14] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[14] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N10
-cycloneive_lcell_comb \spi_slave_instance|q~17 (
-// Equation(s):
-// \spi_slave_instance|q~17_combout = (\spi_slave_instance|q [14] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|q [14]),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~17_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~17 .lut_mask = 16'hC0CC;
-defparam \spi_slave_instance|q~17 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N11
-dffeas \spi_slave_instance|q[15] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~17_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [15]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[15] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[15] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N20
-cycloneive_lcell_comb \spi_slave_instance|q~16 (
-// Equation(s):
-// \spi_slave_instance|q~16_combout = (\spi_slave_instance|q [15] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|cnt [4]),
- .datac(\spi_slave_instance|q [15]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~16_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~16 .lut_mask = 16'hC0F0;
-defparam \spi_slave_instance|q~16 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N21
-dffeas \spi_slave_instance|q[16] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~16_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [16]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[16] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[16] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N22
-cycloneive_lcell_comb \spi_slave_instance|q~15 (
-// Equation(s):
-// \spi_slave_instance|q~15_combout = (\spi_slave_instance|q [16] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|q [16]),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~15_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~15 .lut_mask = 16'hC0CC;
-defparam \spi_slave_instance|q~15 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N23
-dffeas \spi_slave_instance|q[17] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~15_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [17]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[17] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[17] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N0
-cycloneive_lcell_comb \spi_slave_instance|q~14 (
-// Equation(s):
-// \spi_slave_instance|q~14_combout = (\spi_slave_instance|q [17] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|cnt [4]),
- .datac(\spi_slave_instance|q [17]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~14_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~14 .lut_mask = 16'hC0F0;
-defparam \spi_slave_instance|q~14 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N1
-dffeas \spi_slave_instance|q[18] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~14_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [18]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[18] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[18] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N28
-cycloneive_lcell_comb \spi_slave_instance|q~13 (
-// Equation(s):
-// \spi_slave_instance|q~13_combout = (\spi_slave_instance|q [18] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|cnt [4]),
- .datac(\spi_slave_instance|q [18]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~13_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~13 .lut_mask = 16'hC0F0;
-defparam \spi_slave_instance|q~13 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N29
-dffeas \spi_slave_instance|q[19] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~13_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [19]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[19] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[19] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N8
-cycloneive_lcell_comb \spi_slave_instance|q~12 (
-// Equation(s):
-// \spi_slave_instance|q~12_combout = (\spi_slave_instance|q [19] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|q [19]),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~12_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~12 .lut_mask = 16'hC0CC;
-defparam \spi_slave_instance|q~12 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N9
-dffeas \spi_slave_instance|q[20] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~12_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [20]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[20] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[20] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N10
-cycloneive_lcell_comb \spi_slave_instance|q~10 (
-// Equation(s):
-// \spi_slave_instance|q~10_combout = (\spi_slave_instance|cnt [1]) # ((\spi_slave_instance|cnt [4]) # (\spi_slave_instance|cnt [3]))
-
- .dataa(\spi_slave_instance|cnt [1]),
- .datab(gnd),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|cnt [3]),
- .cin(gnd),
- .combout(\spi_slave_instance|q~10_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~10 .lut_mask = 16'hFFFA;
-defparam \spi_slave_instance|q~10 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N26
-cycloneive_lcell_comb \spi_slave_instance|q~11 (
-// Equation(s):
-// \spi_slave_instance|q~11_combout = (\spi_slave_instance|q [20] & ((\spi_slave_instance|cnt [2]) # ((\spi_slave_instance|cnt [0]) # (\spi_slave_instance|q~10_combout ))))
-
- .dataa(\spi_slave_instance|cnt [2]),
- .datab(\spi_slave_instance|q [20]),
- .datac(\spi_slave_instance|cnt [0]),
- .datad(\spi_slave_instance|q~10_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~11_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~11 .lut_mask = 16'hCCC8;
-defparam \spi_slave_instance|q~11 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N27
-dffeas \spi_slave_instance|q[21] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~11_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [21]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[21] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[21] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N12
-cycloneive_lcell_comb \spi_slave_instance|q~9 (
-// Equation(s):
-// \spi_slave_instance|q~9_combout = (\spi_slave_instance|q [21] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(\spi_slave_instance|q [21]),
- .datab(gnd),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~9_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~9 .lut_mask = 16'hA0AA;
-defparam \spi_slave_instance|q~9 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N13
-dffeas \spi_slave_instance|q[22] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~9_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [22]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[22] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[22] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N6
-cycloneive_lcell_comb \spi_slave_instance|q~8 (
-// Equation(s):
-// \spi_slave_instance|q~8_combout = (\spi_slave_instance|q [22] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(\spi_slave_instance|q [22]),
- .datab(gnd),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~8_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~8 .lut_mask = 16'hA0AA;
-defparam \spi_slave_instance|q~8 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N7
-dffeas \spi_slave_instance|q[23] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~8_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [23]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[23] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[23] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N4
-cycloneive_lcell_comb \spi_slave_instance|q~7 (
-// Equation(s):
-// \spi_slave_instance|q~7_combout = (\spi_slave_instance|q [23] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(\spi_slave_instance|q [23]),
- .datab(gnd),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~7_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~7 .lut_mask = 16'hA0AA;
-defparam \spi_slave_instance|q~7 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N5
-dffeas \spi_slave_instance|q[24] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~7_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [24]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[24] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[24] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N30
-cycloneive_lcell_comb \spi_slave_instance|q~6 (
-// Equation(s):
-// \spi_slave_instance|q~6_combout = (\spi_slave_instance|q [24] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|q [24]),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~6_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~6 .lut_mask = 16'hC0CC;
-defparam \spi_slave_instance|q~6 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N31
-dffeas \spi_slave_instance|q[25] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~6_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [25]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[25] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[25] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N20
-cycloneive_lcell_comb \spi_slave_instance|q~5 (
-// Equation(s):
-// \spi_slave_instance|q~5_combout = (\spi_slave_instance|q [25] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(\spi_slave_instance|q [25]),
- .datab(gnd),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~5_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~5 .lut_mask = 16'hA0AA;
-defparam \spi_slave_instance|q~5 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N21
-dffeas \spi_slave_instance|q[26] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~5_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [26]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[26] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[26] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N14
-cycloneive_lcell_comb \spi_slave_instance|q~4 (
-// Equation(s):
-// \spi_slave_instance|q~4_combout = (\spi_slave_instance|q [26] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|q [26]),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~4_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~4 .lut_mask = 16'hC0CC;
-defparam \spi_slave_instance|q~4 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N15
-dffeas \spi_slave_instance|q[27] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~4_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [27]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[27] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[27] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N16
-cycloneive_lcell_comb \spi_slave_instance|q~3 (
-// Equation(s):
-// \spi_slave_instance|q~3_combout = (\spi_slave_instance|q [27] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|q [27]),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~3_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~3 .lut_mask = 16'hC0CC;
-defparam \spi_slave_instance|q~3 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N17
-dffeas \spi_slave_instance|q[28] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~3_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [28]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[28] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[28] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N18
-cycloneive_lcell_comb \spi_slave_instance|q~2 (
-// Equation(s):
-// \spi_slave_instance|q~2_combout = (\spi_slave_instance|q [28] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|q [28]),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~2_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~2 .lut_mask = 16'hC0CC;
-defparam \spi_slave_instance|q~2 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N19
-dffeas \spi_slave_instance|q[29] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~2_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [29]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[29] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[29] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N24
-cycloneive_lcell_comb \spi_slave_instance|q~1 (
-// Equation(s):
-// \spi_slave_instance|q~1_combout = (\spi_slave_instance|q [29] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|q [29]),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~1_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~1 .lut_mask = 16'hC0CC;
-defparam \spi_slave_instance|q~1 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N25
-dffeas \spi_slave_instance|q[30] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~1_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [30]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[30] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[30] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N22
-cycloneive_lcell_comb \spi_slave_instance|q~0 (
-// Equation(s):
-// \spi_slave_instance|q~0_combout = (\spi_slave_instance|q [30] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|q [30]),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~0_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~0 .lut_mask = 16'hC0CC;
-defparam \spi_slave_instance|q~0 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N23
-dffeas \spi_slave_instance|q[31] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~0_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [31]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[31] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[31] .power_up = "low";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N1
-dffeas \spi_slave_instance|qdelayed (
- .clk(!\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(gnd),
- .asdata(\spi_slave_instance|q [31]),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(vcc),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|qdelayed~q ),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|qdelayed .is_wysiwyg = "true";
-defparam \spi_slave_instance|qdelayed .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N0
-cycloneive_lcell_comb \spi_slave_instance|miso~0 (
-// Equation(s):
-// \spi_slave_instance|miso~0_combout = (\spi_slave_instance|qdelayed~q & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|cnt [4]),
- .datac(\spi_slave_instance|qdelayed~q ),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|miso~0_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|miso~0 .lut_mask = 16'hC0F0;
-defparam \spi_slave_instance|miso~0 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: IOIBUF_X16_Y34_N15
-cycloneive_io_ibuf \GPIO_0_PI[10]~input (
- .i(GPIO_0_PI[10]),
- .ibar(gnd),
- .o(\GPIO_0_PI[10]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[10]~input .bus_hold = "false";
-defparam \GPIO_0_PI[10]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X16_Y0_N15
-cycloneive_io_ibuf \CLOCK_50~input (
- .i(CLOCK_50),
- .ibar(gnd),
- .o(\CLOCK_50~input_o ));
-// synopsys translate_off
-defparam \CLOCK_50~input .bus_hold = "false";
-defparam \CLOCK_50~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y14_N1
-cycloneive_io_ibuf \KEY[0]~input (
- .i(KEY[0]),
- .ibar(gnd),
- .o(\KEY[0]~input_o ));
-// synopsys translate_off
-defparam \KEY[0]~input .bus_hold = "false";
-defparam \KEY[0]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y16_N8
-cycloneive_io_ibuf \KEY[1]~input (
- .i(KEY[1]),
- .ibar(gnd),
- .o(\KEY[1]~input_o ));
-// synopsys translate_off
-defparam \KEY[1]~input .bus_hold = "false";
-defparam \KEY[1]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y17_N8
-cycloneive_io_ibuf \GPIO_2_IN[0]~input (
- .i(GPIO_2_IN[0]),
- .ibar(gnd),
- .o(\GPIO_2_IN[0]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2_IN[0]~input .bus_hold = "false";
-defparam \GPIO_2_IN[0]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y17_N1
-cycloneive_io_ibuf \GPIO_2_IN[1]~input (
- .i(GPIO_2_IN[1]),
- .ibar(gnd),
- .o(\GPIO_2_IN[1]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2_IN[1]~input .bus_hold = "false";
-defparam \GPIO_2_IN[1]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X9_Y34_N8
-cycloneive_io_ibuf \GPIO_2_IN[2]~input (
- .i(GPIO_2_IN[2]),
- .ibar(gnd),
- .o(\GPIO_2_IN[2]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2_IN[2]~input .bus_hold = "false";
-defparam \GPIO_2_IN[2]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X14_Y34_N15
-cycloneive_io_ibuf \GPIO_0_PI_IN[0]~input (
- .i(GPIO_0_PI_IN[0]),
- .ibar(gnd),
- .o(\GPIO_0_PI_IN[0]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI_IN[0]~input .bus_hold = "false";
-defparam \GPIO_0_PI_IN[0]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X51_Y34_N1
-cycloneive_io_ibuf \GPIO_0_PI_IN[1]~input (
- .i(GPIO_0_PI_IN[1]),
- .ibar(gnd),
- .o(\GPIO_0_PI_IN[1]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI_IN[1]~input .bus_hold = "false";
-defparam \GPIO_0_PI_IN[1]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X43_Y34_N15
-cycloneive_io_ibuf \GPIO_1_IN[0]~input (
- .i(GPIO_1_IN[0]),
- .ibar(gnd),
- .o(\GPIO_1_IN[0]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1_IN[0]~input .bus_hold = "false";
-defparam \GPIO_1_IN[0]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X34_Y0_N15
-cycloneive_io_ibuf \GPIO_1_IN[1]~input (
- .i(GPIO_1_IN[1]),
- .ibar(gnd),
- .o(\GPIO_1_IN[1]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1_IN[1]~input .bus_hold = "false";
-defparam \GPIO_1_IN[1]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X5_Y0_N22
-cycloneive_io_ibuf \GPIO_2[0]~input (
- .i(GPIO_2[0]),
- .ibar(gnd),
- .o(\GPIO_2[0]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[0]~input .bus_hold = "false";
-defparam \GPIO_2[0]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X51_Y34_N22
-cycloneive_io_ibuf \GPIO_2[1]~input (
- .i(GPIO_2[1]),
- .ibar(gnd),
- .o(\GPIO_2[1]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[1]~input .bus_hold = "false";
-defparam \GPIO_2[1]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y24_N22
-cycloneive_io_ibuf \GPIO_2[2]~input (
- .i(GPIO_2[2]),
- .ibar(gnd),
- .o(\GPIO_2[2]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[2]~input .bus_hold = "false";
-defparam \GPIO_2[2]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y24_N15
-cycloneive_io_ibuf \GPIO_2[3]~input (
- .i(GPIO_2[3]),
- .ibar(gnd),
- .o(\GPIO_2[3]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[3]~input .bus_hold = "false";
-defparam \GPIO_2[3]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X5_Y0_N15
-cycloneive_io_ibuf \GPIO_2[4]~input (
- .i(GPIO_2[4]),
- .ibar(gnd),
- .o(\GPIO_2[4]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[4]~input .bus_hold = "false";
-defparam \GPIO_2[4]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y15_N1
-cycloneive_io_ibuf \GPIO_2[5]~input (
- .i(GPIO_2[5]),
- .ibar(gnd),
- .o(\GPIO_2[5]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[5]~input .bus_hold = "false";
-defparam \GPIO_2[5]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X3_Y34_N1
-cycloneive_io_ibuf \GPIO_2[6]~input (
- .i(GPIO_2[6]),
- .ibar(gnd),
- .o(\GPIO_2[6]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[6]~input .bus_hold = "false";
-defparam \GPIO_2[6]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X1_Y34_N8
-cycloneive_io_ibuf \GPIO_2[7]~input (
- .i(GPIO_2[7]),
- .ibar(gnd),
- .o(\GPIO_2[7]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[7]~input .bus_hold = "false";
-defparam \GPIO_2[7]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X11_Y0_N15
-cycloneive_io_ibuf \GPIO_2[8]~input (
- .i(GPIO_2[8]),
- .ibar(gnd),
- .o(\GPIO_2[8]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[8]~input .bus_hold = "false";
-defparam \GPIO_2[8]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X3_Y0_N1
-cycloneive_io_ibuf \GPIO_2[9]~input (
- .i(GPIO_2[9]),
- .ibar(gnd),
- .o(\GPIO_2[9]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[9]~input .bus_hold = "false";
-defparam \GPIO_2[9]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X43_Y34_N22
-cycloneive_io_ibuf \GPIO_2[10]~input (
- .i(GPIO_2[10]),
- .ibar(gnd),
- .o(\GPIO_2[10]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[10]~input .bus_hold = "false";
-defparam \GPIO_2[10]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X23_Y34_N15
-cycloneive_io_ibuf \GPIO_2[11]~input (
- .i(GPIO_2[11]),
- .ibar(gnd),
- .o(\GPIO_2[11]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[11]~input .bus_hold = "false";
-defparam \GPIO_2[11]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X20_Y34_N8
-cycloneive_io_ibuf \GPIO_2[12]~input (
- .i(GPIO_2[12]),
- .ibar(gnd),
- .o(\GPIO_2[12]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[12]~input .bus_hold = "false";
-defparam \GPIO_2[12]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X34_Y34_N8
-cycloneive_io_ibuf \GPIO_0_PI[0]~input (
- .i(GPIO_0_PI[0]),
- .ibar(gnd),
- .o(\GPIO_0_PI[0]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[0]~input .bus_hold = "false";
-defparam \GPIO_0_PI[0]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y4_N15
-cycloneive_io_ibuf \GPIO_0_PI[1]~input (
- .i(GPIO_0_PI[1]),
- .ibar(gnd),
- .o(\GPIO_0_PI[1]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[1]~input .bus_hold = "false";
-defparam \GPIO_0_PI[1]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y5_N22
-cycloneive_io_ibuf \GPIO_0_PI[2]~input (
- .i(GPIO_0_PI[2]),
- .ibar(gnd),
- .o(\GPIO_0_PI[2]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[2]~input .bus_hold = "false";
-defparam \GPIO_0_PI[2]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X18_Y34_N22
-cycloneive_io_ibuf \GPIO_0_PI[3]~input (
- .i(GPIO_0_PI[3]),
- .ibar(gnd),
- .o(\GPIO_0_PI[3]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[3]~input .bus_hold = "false";
-defparam \GPIO_0_PI[3]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X14_Y0_N15
-cycloneive_io_ibuf \GPIO_0_PI[4]~input (
- .i(GPIO_0_PI[4]),
- .ibar(gnd),
- .o(\GPIO_0_PI[4]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[4]~input .bus_hold = "false";
-defparam \GPIO_0_PI[4]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X14_Y34_N22
-cycloneive_io_ibuf \GPIO_0_PI[5]~input (
- .i(GPIO_0_PI[5]),
- .ibar(gnd),
- .o(\GPIO_0_PI[5]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[5]~input .bus_hold = "false";
-defparam \GPIO_0_PI[5]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y6_N15
-cycloneive_io_ibuf \GPIO_0_PI[6]~input (
- .i(GPIO_0_PI[6]),
- .ibar(gnd),
- .o(\GPIO_0_PI[6]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[6]~input .bus_hold = "false";
-defparam \GPIO_0_PI[6]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X14_Y0_N22
-cycloneive_io_ibuf \GPIO_0_PI[7]~input (
- .i(GPIO_0_PI[7]),
- .ibar(gnd),
- .o(\GPIO_0_PI[7]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[7]~input .bus_hold = "false";
-defparam \GPIO_0_PI[7]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y4_N22
-cycloneive_io_ibuf \GPIO_0_PI[12]~input (
- .i(GPIO_0_PI[12]),
- .ibar(gnd),
- .o(\GPIO_0_PI[12]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[12]~input .bus_hold = "false";
-defparam \GPIO_0_PI[12]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y8_N22
-cycloneive_io_ibuf \GPIO_0_PI[13]~input (
- .i(GPIO_0_PI[13]),
- .ibar(gnd),
- .o(\GPIO_0_PI[13]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[13]~input .bus_hold = "false";
-defparam \GPIO_0_PI[13]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X1_Y34_N1
-cycloneive_io_ibuf \GPIO_0_PI[14]~input (
- .i(GPIO_0_PI[14]),
- .ibar(gnd),
- .o(\GPIO_0_PI[14]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[14]~input .bus_hold = "false";
-defparam \GPIO_0_PI[14]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X34_Y34_N15
-cycloneive_io_ibuf \GPIO_0_PI[15]~input (
- .i(GPIO_0_PI[15]),
- .ibar(gnd),
- .o(\GPIO_0_PI[15]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[15]~input .bus_hold = "false";
-defparam \GPIO_0_PI[15]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X34_Y34_N1
-cycloneive_io_ibuf \GPIO_0_PI[16]~input (
- .i(GPIO_0_PI[16]),
- .ibar(gnd),
- .o(\GPIO_0_PI[16]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[16]~input .bus_hold = "false";
-defparam \GPIO_0_PI[16]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X16_Y34_N8
-cycloneive_io_ibuf \GPIO_0_PI[17]~input (
- .i(GPIO_0_PI[17]),
- .ibar(gnd),
- .o(\GPIO_0_PI[17]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[17]~input .bus_hold = "false";
-defparam \GPIO_0_PI[17]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X1_Y0_N8
-cycloneive_io_ibuf \GPIO_0_PI[18]~input (
- .i(GPIO_0_PI[18]),
- .ibar(gnd),
- .o(\GPIO_0_PI[18]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[18]~input .bus_hold = "false";
-defparam \GPIO_0_PI[18]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X36_Y0_N8
-cycloneive_io_ibuf \GPIO_0_PI[19]~input (
- .i(GPIO_0_PI[19]),
- .ibar(gnd),
- .o(\GPIO_0_PI[19]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[19]~input .bus_hold = "false";
-defparam \GPIO_0_PI[19]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y15_N8
-cycloneive_io_ibuf \GPIO_0_PI[20]~input (
- .i(GPIO_0_PI[20]),
- .ibar(gnd),
- .o(\GPIO_0_PI[20]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[20]~input .bus_hold = "false";
-defparam \GPIO_0_PI[20]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X47_Y34_N22
-cycloneive_io_ibuf \GPIO_0_PI[21]~input (
- .i(GPIO_0_PI[21]),
- .ibar(gnd),
- .o(\GPIO_0_PI[21]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[21]~input .bus_hold = "false";
-defparam \GPIO_0_PI[21]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X14_Y0_N8
-cycloneive_io_ibuf \GPIO_0_PI[22]~input (
- .i(GPIO_0_PI[22]),
- .ibar(gnd),
- .o(\GPIO_0_PI[22]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[22]~input .bus_hold = "false";
-defparam \GPIO_0_PI[22]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X20_Y34_N22
-cycloneive_io_ibuf \GPIO_0_PI[23]~input (
- .i(GPIO_0_PI[23]),
- .ibar(gnd),
- .o(\GPIO_0_PI[23]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[23]~input .bus_hold = "false";
-defparam \GPIO_0_PI[23]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X45_Y34_N1
-cycloneive_io_ibuf \GPIO_0_PI[24]~input (
- .i(GPIO_0_PI[24]),
- .ibar(gnd),
- .o(\GPIO_0_PI[24]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[24]~input .bus_hold = "false";
-defparam \GPIO_0_PI[24]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X40_Y0_N22
-cycloneive_io_ibuf \GPIO_0_PI[25]~input (
- .i(GPIO_0_PI[25]),
- .ibar(gnd),
- .o(\GPIO_0_PI[25]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[25]~input .bus_hold = "false";
-defparam \GPIO_0_PI[25]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X18_Y0_N8
-cycloneive_io_ibuf \GPIO_0_PI[26]~input (
- .i(GPIO_0_PI[26]),
- .ibar(gnd),
- .o(\GPIO_0_PI[26]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[26]~input .bus_hold = "false";
-defparam \GPIO_0_PI[26]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X45_Y34_N15
-cycloneive_io_ibuf \GPIO_0_PI[27]~input (
- .i(GPIO_0_PI[27]),
- .ibar(gnd),
- .o(\GPIO_0_PI[27]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[27]~input .bus_hold = "false";
-defparam \GPIO_0_PI[27]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X38_Y34_N1
-cycloneive_io_ibuf \GPIO_0_PI[28]~input (
- .i(GPIO_0_PI[28]),
- .ibar(gnd),
- .o(\GPIO_0_PI[28]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[28]~input .bus_hold = "false";
-defparam \GPIO_0_PI[28]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X40_Y34_N8
-cycloneive_io_ibuf \GPIO_0_PI[29]~input (
- .i(GPIO_0_PI[29]),
- .ibar(gnd),
- .o(\GPIO_0_PI[29]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[29]~input .bus_hold = "false";
-defparam \GPIO_0_PI[29]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X18_Y34_N1
-cycloneive_io_ibuf \GPIO_0_PI[30]~input (
- .i(GPIO_0_PI[30]),
- .ibar(gnd),
- .o(\GPIO_0_PI[30]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[30]~input .bus_hold = "false";
-defparam \GPIO_0_PI[30]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X23_Y34_N22
-cycloneive_io_ibuf \GPIO_0_PI[32]~input (
- .i(GPIO_0_PI[32]),
- .ibar(gnd),
- .o(\GPIO_0_PI[32]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[32]~input .bus_hold = "false";
-defparam \GPIO_0_PI[32]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y22_N1
-cycloneive_io_ibuf \GPIO_0_PI[33]~input (
- .i(GPIO_0_PI[33]),
- .ibar(gnd),
- .o(\GPIO_0_PI[33]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[33]~input .bus_hold = "false";
-defparam \GPIO_0_PI[33]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X14_Y0_N1
-cycloneive_io_ibuf \GPIO_1[0]~input (
- .i(GPIO_1[0]),
- .ibar(gnd),
- .o(\GPIO_1[0]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[0]~input .bus_hold = "false";
-defparam \GPIO_1[0]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X1_Y0_N22
-cycloneive_io_ibuf \GPIO_1[1]~input (
- .i(GPIO_1[1]),
- .ibar(gnd),
- .o(\GPIO_1[1]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[1]~input .bus_hold = "false";
-defparam \GPIO_1[1]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y20_N22
-cycloneive_io_ibuf \GPIO_1[2]~input (
- .i(GPIO_1[2]),
- .ibar(gnd),
- .o(\GPIO_1[2]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[2]~input .bus_hold = "false";
-defparam \GPIO_1[2]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y23_N1
-cycloneive_io_ibuf \GPIO_1[3]~input (
- .i(GPIO_1[3]),
- .ibar(gnd),
- .o(\GPIO_1[3]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[3]~input .bus_hold = "false";
-defparam \GPIO_1[3]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X7_Y34_N1
-cycloneive_io_ibuf \GPIO_1[4]~input (
- .i(GPIO_1[4]),
- .ibar(gnd),
- .o(\GPIO_1[4]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[4]~input .bus_hold = "false";
-defparam \GPIO_1[4]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y11_N1
-cycloneive_io_ibuf \GPIO_1[5]~input (
- .i(GPIO_1[5]),
- .ibar(gnd),
- .o(\GPIO_1[5]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[5]~input .bus_hold = "false";
-defparam \GPIO_1[5]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X51_Y34_N8
-cycloneive_io_ibuf \GPIO_1[6]~input (
- .i(GPIO_1[6]),
- .ibar(gnd),
- .o(\GPIO_1[6]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[6]~input .bus_hold = "false";
-defparam \GPIO_1[6]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X5_Y0_N8
-cycloneive_io_ibuf \GPIO_1[7]~input (
- .i(GPIO_1[7]),
- .ibar(gnd),
- .o(\GPIO_1[7]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[7]~input .bus_hold = "false";
-defparam \GPIO_1[7]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y22_N8
-cycloneive_io_ibuf \GPIO_1[8]~input (
- .i(GPIO_1[8]),
- .ibar(gnd),
- .o(\GPIO_1[8]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[8]~input .bus_hold = "false";
-defparam \GPIO_1[8]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X34_Y0_N1
-cycloneive_io_ibuf \GPIO_1[9]~input (
- .i(GPIO_1[9]),
- .ibar(gnd),
- .o(\GPIO_1[9]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[9]~input .bus_hold = "false";
-defparam \GPIO_1[9]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y11_N8
-cycloneive_io_ibuf \GPIO_1[10]~input (
- .i(GPIO_1[10]),
- .ibar(gnd),
- .o(\GPIO_1[10]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[10]~input .bus_hold = "false";
-defparam \GPIO_1[10]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X45_Y34_N8
-cycloneive_io_ibuf \GPIO_1[11]~input (
- .i(GPIO_1[11]),
- .ibar(gnd),
- .o(\GPIO_1[11]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[11]~input .bus_hold = "false";
-defparam \GPIO_1[11]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y26_N22
-cycloneive_io_ibuf \GPIO_1[12]~input (
- .i(GPIO_1[12]),
- .ibar(gnd),
- .o(\GPIO_1[12]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[12]~input .bus_hold = "false";
-defparam \GPIO_1[12]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X40_Y0_N15
-cycloneive_io_ibuf \GPIO_1[13]~input (
- .i(GPIO_1[13]),
- .ibar(gnd),
- .o(\GPIO_1[13]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[13]~input .bus_hold = "false";
-defparam \GPIO_1[13]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y12_N1
-cycloneive_io_ibuf \GPIO_1[14]~input (
- .i(GPIO_1[14]),
- .ibar(gnd),
- .o(\GPIO_1[14]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[14]~input .bus_hold = "false";
-defparam \GPIO_1[14]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y30_N1
-cycloneive_io_ibuf \GPIO_1[15]~input (
- .i(GPIO_1[15]),
- .ibar(gnd),
- .o(\GPIO_1[15]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[15]~input .bus_hold = "false";
-defparam \GPIO_1[15]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X25_Y0_N15
-cycloneive_io_ibuf \GPIO_1[16]~input (
- .i(GPIO_1[16]),
- .ibar(gnd),
- .o(\GPIO_1[16]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[16]~input .bus_hold = "false";
-defparam \GPIO_1[16]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X34_Y0_N22
-cycloneive_io_ibuf \GPIO_1[17]~input (
- .i(GPIO_1[17]),
- .ibar(gnd),
- .o(\GPIO_1[17]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[17]~input .bus_hold = "false";
-defparam \GPIO_1[17]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y7_N1
-cycloneive_io_ibuf \GPIO_1[18]~input (
- .i(GPIO_1[18]),
- .ibar(gnd),
- .o(\GPIO_1[18]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[18]~input .bus_hold = "false";
-defparam \GPIO_1[18]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y30_N8
-cycloneive_io_ibuf \GPIO_1[19]~input (
- .i(GPIO_1[19]),
- .ibar(gnd),
- .o(\GPIO_1[19]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[19]~input .bus_hold = "false";
-defparam \GPIO_1[19]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y27_N1
-cycloneive_io_ibuf \GPIO_1[20]~input (
- .i(GPIO_1[20]),
- .ibar(gnd),
- .o(\GPIO_1[20]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[20]~input .bus_hold = "false";
-defparam \GPIO_1[20]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X47_Y0_N22
-cycloneive_io_ibuf \GPIO_1[21]~input (
- .i(GPIO_1[21]),
- .ibar(gnd),
- .o(\GPIO_1[21]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[21]~input .bus_hold = "false";
-defparam \GPIO_1[21]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X11_Y34_N1
-cycloneive_io_ibuf \GPIO_1[22]~input (
- .i(GPIO_1[22]),
- .ibar(gnd),
- .o(\GPIO_1[22]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[22]~input .bus_hold = "false";
-defparam \GPIO_1[22]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X20_Y0_N8
-cycloneive_io_ibuf \GPIO_1[23]~input (
- .i(GPIO_1[23]),
- .ibar(gnd),
- .o(\GPIO_1[23]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[23]~input .bus_hold = "false";
-defparam \GPIO_1[23]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X5_Y0_N1
-cycloneive_io_ibuf \GPIO_1[24]~input (
- .i(GPIO_1[24]),
- .ibar(gnd),
- .o(\GPIO_1[24]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[24]~input .bus_hold = "false";
-defparam \GPIO_1[24]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y21_N22
-cycloneive_io_ibuf \GPIO_1[25]~input (
- .i(GPIO_1[25]),
- .ibar(gnd),
- .o(\GPIO_1[25]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[25]~input .bus_hold = "false";
-defparam \GPIO_1[25]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X1_Y0_N15
-cycloneive_io_ibuf \GPIO_1[26]~input (
- .i(GPIO_1[26]),
- .ibar(gnd),
- .o(\GPIO_1[26]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[26]~input .bus_hold = "false";
-defparam \GPIO_1[26]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X7_Y0_N8
-cycloneive_io_ibuf \GPIO_1[27]~input (
- .i(GPIO_1[27]),
- .ibar(gnd),
- .o(\GPIO_1[27]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[27]~input .bus_hold = "false";
-defparam \GPIO_1[27]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y23_N22
-cycloneive_io_ibuf \GPIO_1[28]~input (
- .i(GPIO_1[28]),
- .ibar(gnd),
- .o(\GPIO_1[28]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[28]~input .bus_hold = "false";
-defparam \GPIO_1[28]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y14_N8
-cycloneive_io_ibuf \GPIO_1[29]~input (
- .i(GPIO_1[29]),
- .ibar(gnd),
- .o(\GPIO_1[29]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[29]~input .bus_hold = "false";
-defparam \GPIO_1[29]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X45_Y0_N22
-cycloneive_io_ibuf \GPIO_1[30]~input (
- .i(GPIO_1[30]),
- .ibar(gnd),
- .o(\GPIO_1[30]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[30]~input .bus_hold = "false";
-defparam \GPIO_1[30]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X49_Y0_N1
-cycloneive_io_ibuf \GPIO_1[31]~input (
- .i(GPIO_1[31]),
- .ibar(gnd),
- .o(\GPIO_1[31]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[31]~input .bus_hold = "false";
-defparam \GPIO_1[31]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X31_Y34_N1
-cycloneive_io_ibuf \GPIO_1[32]~input (
- .i(GPIO_1[32]),
- .ibar(gnd),
- .o(\GPIO_1[32]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[32]~input .bus_hold = "false";
-defparam \GPIO_1[32]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y6_N15
-cycloneive_io_ibuf \GPIO_1[33]~input (
- .i(GPIO_1[33]),
- .ibar(gnd),
- .o(\GPIO_1[33]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[33]~input .bus_hold = "false";
-defparam \GPIO_1[33]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X16_Y34_N1
-cycloneive_io_ibuf \GPIO_0_PI[11]~input (
- .i(GPIO_0_PI[11]),
- .ibar(gnd),
- .o(\GPIO_0_PI[11]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[11]~input .bus_hold = "false";
-defparam \GPIO_0_PI[11]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-assign LED[0] = \LED[0]~output_o ;
-
-assign LED[1] = \LED[1]~output_o ;
-
-assign LED[2] = \LED[2]~output_o ;
-
-assign LED[3] = \LED[3]~output_o ;
-
-assign LED[4] = \LED[4]~output_o ;
-
-assign LED[5] = \LED[5]~output_o ;
-
-assign LED[6] = \LED[6]~output_o ;
-
-assign LED[7] = \LED[7]~output_o ;
-
-assign GPIO_2[0] = \GPIO_2[0]~output_o ;
-
-assign GPIO_2[1] = \GPIO_2[1]~output_o ;
-
-assign GPIO_2[2] = \GPIO_2[2]~output_o ;
-
-assign GPIO_2[3] = \GPIO_2[3]~output_o ;
-
-assign GPIO_2[4] = \GPIO_2[4]~output_o ;
-
-assign GPIO_2[5] = \GPIO_2[5]~output_o ;
-
-assign GPIO_2[6] = \GPIO_2[6]~output_o ;
-
-assign GPIO_2[7] = \GPIO_2[7]~output_o ;
-
-assign GPIO_2[8] = \GPIO_2[8]~output_o ;
-
-assign GPIO_2[9] = \GPIO_2[9]~output_o ;
-
-assign GPIO_2[10] = \GPIO_2[10]~output_o ;
-
-assign GPIO_2[11] = \GPIO_2[11]~output_o ;
-
-assign GPIO_2[12] = \GPIO_2[12]~output_o ;
-
-assign GPIO_0_PI[0] = \GPIO_0_PI[0]~output_o ;
-
-assign GPIO_0_PI[1] = \GPIO_0_PI[1]~output_o ;
-
-assign GPIO_0_PI[2] = \GPIO_0_PI[2]~output_o ;
-
-assign GPIO_0_PI[3] = \GPIO_0_PI[3]~output_o ;
-
-assign GPIO_0_PI[4] = \GPIO_0_PI[4]~output_o ;
-
-assign GPIO_0_PI[5] = \GPIO_0_PI[5]~output_o ;
-
-assign GPIO_0_PI[6] = \GPIO_0_PI[6]~output_o ;
-
-assign GPIO_0_PI[7] = \GPIO_0_PI[7]~output_o ;
-
-assign GPIO_0_PI[12] = \GPIO_0_PI[12]~output_o ;
-
-assign GPIO_0_PI[13] = \GPIO_0_PI[13]~output_o ;
-
-assign GPIO_0_PI[14] = \GPIO_0_PI[14]~output_o ;
-
-assign GPIO_0_PI[15] = \GPIO_0_PI[15]~output_o ;
-
-assign GPIO_0_PI[16] = \GPIO_0_PI[16]~output_o ;
-
-assign GPIO_0_PI[17] = \GPIO_0_PI[17]~output_o ;
-
-assign GPIO_0_PI[18] = \GPIO_0_PI[18]~output_o ;
-
-assign GPIO_0_PI[19] = \GPIO_0_PI[19]~output_o ;
-
-assign GPIO_0_PI[20] = \GPIO_0_PI[20]~output_o ;
-
-assign GPIO_0_PI[21] = \GPIO_0_PI[21]~output_o ;
-
-assign GPIO_0_PI[22] = \GPIO_0_PI[22]~output_o ;
-
-assign GPIO_0_PI[23] = \GPIO_0_PI[23]~output_o ;
-
-assign GPIO_0_PI[24] = \GPIO_0_PI[24]~output_o ;
-
-assign GPIO_0_PI[25] = \GPIO_0_PI[25]~output_o ;
-
-assign GPIO_0_PI[26] = \GPIO_0_PI[26]~output_o ;
-
-assign GPIO_0_PI[27] = \GPIO_0_PI[27]~output_o ;
-
-assign GPIO_0_PI[28] = \GPIO_0_PI[28]~output_o ;
-
-assign GPIO_0_PI[29] = \GPIO_0_PI[29]~output_o ;
-
-assign GPIO_0_PI[30] = \GPIO_0_PI[30]~output_o ;
-
-assign GPIO_0_PI[32] = \GPIO_0_PI[32]~output_o ;
-
-assign GPIO_0_PI[33] = \GPIO_0_PI[33]~output_o ;
-
-assign GPIO_1[0] = \GPIO_1[0]~output_o ;
-
-assign GPIO_1[1] = \GPIO_1[1]~output_o ;
-
-assign GPIO_1[2] = \GPIO_1[2]~output_o ;
-
-assign GPIO_1[3] = \GPIO_1[3]~output_o ;
-
-assign GPIO_1[4] = \GPIO_1[4]~output_o ;
-
-assign GPIO_1[5] = \GPIO_1[5]~output_o ;
-
-assign GPIO_1[6] = \GPIO_1[6]~output_o ;
-
-assign GPIO_1[7] = \GPIO_1[7]~output_o ;
-
-assign GPIO_1[8] = \GPIO_1[8]~output_o ;
-
-assign GPIO_1[9] = \GPIO_1[9]~output_o ;
-
-assign GPIO_1[10] = \GPIO_1[10]~output_o ;
-
-assign GPIO_1[11] = \GPIO_1[11]~output_o ;
-
-assign GPIO_1[12] = \GPIO_1[12]~output_o ;
-
-assign GPIO_1[13] = \GPIO_1[13]~output_o ;
-
-assign GPIO_1[14] = \GPIO_1[14]~output_o ;
-
-assign GPIO_1[15] = \GPIO_1[15]~output_o ;
-
-assign GPIO_1[16] = \GPIO_1[16]~output_o ;
-
-assign GPIO_1[17] = \GPIO_1[17]~output_o ;
-
-assign GPIO_1[18] = \GPIO_1[18]~output_o ;
-
-assign GPIO_1[19] = \GPIO_1[19]~output_o ;
-
-assign GPIO_1[20] = \GPIO_1[20]~output_o ;
-
-assign GPIO_1[21] = \GPIO_1[21]~output_o ;
-
-assign GPIO_1[22] = \GPIO_1[22]~output_o ;
-
-assign GPIO_1[23] = \GPIO_1[23]~output_o ;
-
-assign GPIO_1[24] = \GPIO_1[24]~output_o ;
-
-assign GPIO_1[25] = \GPIO_1[25]~output_o ;
-
-assign GPIO_1[26] = \GPIO_1[26]~output_o ;
-
-assign GPIO_1[27] = \GPIO_1[27]~output_o ;
-
-assign GPIO_1[28] = \GPIO_1[28]~output_o ;
-
-assign GPIO_1[29] = \GPIO_1[29]~output_o ;
-
-assign GPIO_1[30] = \GPIO_1[30]~output_o ;
-
-assign GPIO_1[31] = \GPIO_1[31]~output_o ;
-
-assign GPIO_1[32] = \GPIO_1[32]~output_o ;
-
-assign GPIO_1[33] = \GPIO_1[33]~output_o ;
-
-assign GPIO_0_PI[8] = \GPIO_0_PI[8]~output_o ;
-
-assign GPIO_0_PI[9] = \GPIO_0_PI[9]~output_o ;
-
-assign GPIO_0_PI[10] = \GPIO_0_PI[10]~output_o ;
-
-assign GPIO_0_PI[11] = \GPIO_0_PI[11]~output_o ;
-
-assign GPIO_0_PI[31] = \GPIO_0_PI[31]~output_o ;
-
-endmodule
-
-module hard_block (
-
- devpor,
- devclrn,
- devoe);
-
-// Design Ports Information
-// ~ALTERA_ASDO_DATA1~ => Location: PIN_C1, I/O Standard: 2.5 V, Current Strength: Default
-// ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_D2, I/O Standard: 2.5 V, Current Strength: Default
-// ~ALTERA_DCLK~ => Location: PIN_H1, I/O Standard: 2.5 V, Current Strength: Default
-// ~ALTERA_DATA0~ => Location: PIN_H2, I/O Standard: 2.5 V, Current Strength: Default
-// ~ALTERA_nCEO~ => Location: PIN_F16, I/O Standard: 2.5 V, Current Strength: 8mA
-
-input devpor;
-input devclrn;
-input devoe;
-
-wire gnd;
-wire vcc;
-wire unknown;
-
-assign gnd = 1'b0;
-assign vcc = 1'b1;
-assign unknown = 1'bx;
-
-wire \~ALTERA_ASDO_DATA1~~padout ;
-wire \~ALTERA_FLASH_nCE_nCSO~~padout ;
-wire \~ALTERA_DATA0~~padout ;
-wire \~ALTERA_ASDO_DATA1~~ibuf_o ;
-wire \~ALTERA_FLASH_nCE_nCSO~~ibuf_o ;
-wire \~ALTERA_DATA0~~ibuf_o ;
-
-
-endmodule
diff --git a/SPI/simulation/modelsim/SPI_test_6_1200mv_0c_v_slow.sdo b/SPI/simulation/modelsim/SPI_test_6_1200mv_0c_v_slow.sdo
deleted file mode 100644
index e221cbbc426e64746c3090e1e0e3d58c8f7f71d3..0000000000000000000000000000000000000000
--- a/SPI/simulation/modelsim/SPI_test_6_1200mv_0c_v_slow.sdo
+++ /dev/null
@@ -1,1172 +0,0 @@
-// Copyright (C) 2018 Intel Corporation. All rights reserved.
-// Your use of Intel Corporation's design tools, logic functions
-// and other software and tools, and its AMPP partner logic
-// functions, and any output files from any of the foregoing
-// (including device programming or simulation files), and any
-// associated documentation or information are expressly subject
-// to the terms and conditions of the Intel Program License
-// Subscription Agreement, the Intel Quartus Prime License Agreement,
-// the Intel FPGA IP License Agreement, or other applicable license
-// agreement, including, without limitation, that your use is for
-// the sole purpose of programming logic devices manufactured by
-// Intel and sold by Intel or its authorized distributors. Please
-// refer to the applicable agreement for further details.
-
-
-//
-// Device: Altera EP4CE22F17C6 Package FBGA256
-//
-
-//
-// This file contains Slow Corner delays for the design using part EP4CE22F17C6,
-// with speed grade 6, core voltage 1.2VmV, and temperature 0 Celsius
-//
-
-//
-// This SDF file should be used for ModelSim-Altera (SystemVerilog) only
-//
-
-(DELAYFILE
- (SDFVERSION "2.1")
- (DESIGN "MyDE0_Nano")
- (DATE "11/16/2022 16:51:48")
- (VENDOR "Altera")
- (PROGRAM "Quartus Prime")
- (VERSION "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition")
- (DIVIDER .)
- (TIMESCALE 1 ps)
-
- (CELL
- (CELLTYPE "cycloneive_io_obuf")
- (INSTANCE GPIO_0_PI\[11\]\~output)
- (DELAY
- (ABSOLUTE
- (PORT i (653:653:653) (604:604:604))
- (PORT oe (2618:2618:2618) (2440:2440:2440))
- (IOPATH i o (2276:2276:2276) (2263:2263:2263))
- (IOPATH oe o (2275:2275:2275) (2224:2224:2224))
- )
- )
- )
- (CELL
- (CELLTYPE "cycloneive_io_ibuf")
- (INSTANCE GPIO_0_PI\[8\]\~input)
- (DELAY
- (ABSOLUTE
- (IOPATH i o (501:501:501) (643:643:643))
- )
- )
- )
- (CELL
- (CELLTYPE "cycloneive_clkctrl")
- (INSTANCE GPIO_0_PI\[8\]\~inputclkctrl)
- (DELAY
- (ABSOLUTE
- (IOPATH inclk outclk (178:178:178) (172:172:172))
- )
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|cnt\[0\]\~12)
- (DELAY
- (ABSOLUTE
- (IOPATH datac combout (312:312:312) (325:325:325))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|cnt\[0\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1365:1365:1365) (1375:1375:1375))
- (PORT d (67:67:67) (78:78:78))
- (IOPATH (posedge clk) q (180:180:180) (180:180:180))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (144:144:144))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|cnt\[1\]\~4)
- (DELAY
- (ABSOLUTE
- (PORT dataa (249:249:249) (325:325:325))
- (PORT datab (244:244:244) (317:317:317))
- (IOPATH dataa combout (300:300:300) (323:323:323))
- (IOPATH dataa cout (376:376:376) (275:275:275))
- (IOPATH datab combout (306:306:306) (324:324:324))
- (IOPATH datab cout (385:385:385) (280:280:280))
- (IOPATH datad combout (119:119:119) (106:106:106))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|cnt\[1\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1365:1365:1365) (1375:1375:1375))
- (PORT d (67:67:67) (78:78:78))
- (IOPATH (posedge clk) q (180:180:180) (180:180:180))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (144:144:144))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|cnt\[2\]\~6)
- (DELAY
- (ABSOLUTE
- (PORT datab (378:378:378) (428:428:428))
- (IOPATH datab combout (325:325:325) (332:332:332))
- (IOPATH datab cout (385:385:385) (280:280:280))
- (IOPATH datad combout (119:119:119) (106:106:106))
- (IOPATH cin combout (408:408:408) (387:387:387))
- (IOPATH cin cout (50:50:50) (50:50:50))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|cnt\[2\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1365:1365:1365) (1375:1375:1375))
- (PORT d (67:67:67) (78:78:78))
- (IOPATH (posedge clk) q (180:180:180) (180:180:180))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (144:144:144))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|cnt\[3\]\~8)
- (DELAY
- (ABSOLUTE
- (PORT dataa (247:247:247) (322:322:322))
- (IOPATH dataa combout (318:318:318) (323:323:323))
- (IOPATH dataa cout (376:376:376) (275:275:275))
- (IOPATH datad combout (119:119:119) (106:106:106))
- (IOPATH cin combout (408:408:408) (387:387:387))
- (IOPATH cin cout (50:50:50) (50:50:50))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|cnt\[3\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1365:1365:1365) (1375:1375:1375))
- (PORT d (67:67:67) (78:78:78))
- (IOPATH (posedge clk) q (180:180:180) (180:180:180))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (144:144:144))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|cnt\[4\]\~10)
- (DELAY
- (ABSOLUTE
- (PORT datab (321:321:321) (422:422:422))
- (IOPATH datab combout (325:325:325) (332:332:332))
- (IOPATH cin combout (408:408:408) (387:387:387))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|cnt\[4\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1365:1365:1365) (1375:1375:1375))
- (PORT d (67:67:67) (78:78:78))
- (IOPATH (posedge clk) q (180:180:180) (180:180:180))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (144:144:144))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_io_ibuf")
- (INSTANCE GPIO_0_PI\[31\]\~input)
- (DELAY
- (ABSOLUTE
- (IOPATH i o (499:499:499) (643:643:643))
- )
- )
- )
- (CELL
- (CELLTYPE "cycloneive_io_ibuf")
- (INSTANCE GPIO_0_PI\[9\]\~input)
- (DELAY
- (ABSOLUTE
- (IOPATH i o (499:499:499) (643:643:643))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[0\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1361:1361:1361) (1380:1380:1380))
- (PORT asdata (3203:3203:3203) (3434:3434:3434))
- (IOPATH (posedge clk) q (180:180:180) (180:180:180))
- )
- )
- (TIMINGCHECK
- (HOLD asdata (posedge clk) (144:144:144))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|Equal0\~0)
- (DELAY
- (ABSOLUTE
- (PORT dataa (248:248:248) (326:326:326))
- (PORT datab (246:246:246) (319:319:319))
- (PORT datac (214:214:214) (281:281:281))
- (PORT datad (224:224:224) (286:286:286))
- (IOPATH dataa combout (309:309:309) (326:326:326))
- (IOPATH datab combout (309:309:309) (328:328:328))
- (IOPATH datac combout (218:218:218) (215:215:215))
- (IOPATH datad combout (119:119:119) (106:106:106))
- )
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~31)
- (DELAY
- (ABSOLUTE
- (PORT dataa (454:454:454) (529:529:529))
- (PORT datab (3164:3164:3164) (3412:3412:3412))
- (PORT datac (198:198:198) (265:265:265))
- (PORT datad (378:378:378) (389:389:389))
- (IOPATH dataa combout (287:287:287) (280:280:280))
- (IOPATH datab combout (275:275:275) (275:275:275))
- (IOPATH datac combout (220:220:220) (216:216:216))
- (IOPATH datad combout (119:119:119) (106:106:106))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[1\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1361:1361:1361) (1380:1380:1380))
- (PORT d (67:67:67) (78:78:78))
- (IOPATH (posedge clk) q (180:180:180) (180:180:180))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (144:144:144))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~30)
- (DELAY
- (ABSOLUTE
- (PORT dataa (454:454:454) (530:530:530))
- (PORT datac (196:196:196) (263:263:263))
- (PORT datad (379:379:379) (387:387:387))
- (IOPATH dataa combout (273:273:273) (269:269:269))
- (IOPATH datac combout (220:220:220) (216:216:216))
- (IOPATH datad combout (119:119:119) (106:106:106))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[2\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1361:1361:1361) (1380:1380:1380))
- (PORT d (67:67:67) (78:78:78))
- (IOPATH (posedge clk) q (180:180:180) (180:180:180))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (144:144:144))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~29)
- (DELAY
- (ABSOLUTE
- (PORT dataa (457:457:457) (530:530:530))
- (PORT datab (222:222:222) (291:291:291))
- (PORT datad (381:381:381) (387:387:387))
- (IOPATH dataa combout (265:265:265) (269:269:269))
- (IOPATH datab combout (319:319:319) (324:324:324))
- (IOPATH datad combout (119:119:119) (106:106:106))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[3\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1361:1361:1361) (1380:1380:1380))
- (PORT d (67:67:67) (78:78:78))
- (IOPATH (posedge clk) q (180:180:180) (180:180:180))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (144:144:144))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~28)
- (DELAY
- (ABSOLUTE
- (PORT dataa (446:446:446) (521:521:521))
- (PORT datac (198:198:198) (265:265:265))
- (PORT datad (381:381:381) (389:389:389))
- (IOPATH dataa combout (273:273:273) (269:269:269))
- (IOPATH datac combout (220:220:220) (216:216:216))
- (IOPATH datad combout (119:119:119) (106:106:106))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[4\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1361:1361:1361) (1380:1380:1380))
- (PORT d (67:67:67) (78:78:78))
- (IOPATH (posedge clk) q (180:180:180) (180:180:180))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (144:144:144))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~27)
- (DELAY
- (ABSOLUTE
- (PORT dataa (453:453:453) (528:528:528))
- (PORT datac (198:198:198) (265:265:265))
- (PORT datad (377:377:377) (387:387:387))
- (IOPATH dataa combout (273:273:273) (269:269:269))
- (IOPATH datac combout (220:220:220) (216:216:216))
- (IOPATH datad combout (119:119:119) (106:106:106))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[5\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1361:1361:1361) (1380:1380:1380))
- (PORT d (67:67:67) (78:78:78))
- (IOPATH (posedge clk) q (180:180:180) (180:180:180))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (144:144:144))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~26)
- (DELAY
- (ABSOLUTE
- (PORT dataa (456:456:456) (529:529:529))
- (PORT datab (223:223:223) (292:292:292))
- (PORT datad (380:380:380) (387:387:387))
- (IOPATH dataa combout (265:265:265) (269:269:269))
- (IOPATH datab combout (319:319:319) (324:324:324))
- (IOPATH datad combout (119:119:119) (106:106:106))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[6\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1361:1361:1361) (1380:1380:1380))
- (PORT d (67:67:67) (78:78:78))
- (IOPATH (posedge clk) q (180:180:180) (180:180:180))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (144:144:144))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~25)
- (DELAY
- (ABSOLUTE
- (PORT dataa (447:447:447) (522:522:522))
- (PORT datab (225:225:225) (295:295:295))
- (PORT datad (381:381:381) (387:387:387))
- (IOPATH dataa combout (265:265:265) (269:269:269))
- (IOPATH datab combout (319:319:319) (324:324:324))
- (IOPATH datad combout (119:119:119) (106:106:106))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[7\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1361:1361:1361) (1380:1380:1380))
- (PORT d (67:67:67) (78:78:78))
- (IOPATH (posedge clk) q (180:180:180) (180:180:180))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (144:144:144))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~24)
- (DELAY
- (ABSOLUTE
- (PORT datab (322:322:322) (427:427:427))
- (PORT datac (336:336:336) (380:380:380))
- (PORT datad (257:257:257) (295:295:295))
- (IOPATH datab combout (275:275:275) (275:275:275))
- (IOPATH datac combout (220:220:220) (216:216:216))
- (IOPATH datad combout (119:119:119) (106:106:106))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[8\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1361:1361:1361) (1379:1379:1379))
- (PORT d (67:67:67) (78:78:78))
- (IOPATH (posedge clk) q (180:180:180) (180:180:180))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (144:144:144))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~23)
- (DELAY
- (ABSOLUTE
- (PORT datab (224:224:224) (294:294:294))
- (PORT datac (294:294:294) (397:397:397))
- (PORT datad (256:256:256) (293:293:293))
- (IOPATH datab combout (319:319:319) (324:324:324))
- (IOPATH datac combout (218:218:218) (216:216:216))
- (IOPATH datad combout (119:119:119) (106:106:106))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[9\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1361:1361:1361) (1379:1379:1379))
- (PORT d (67:67:67) (78:78:78))
- (IOPATH (posedge clk) q (180:180:180) (180:180:180))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (144:144:144))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~22)
- (DELAY
- (ABSOLUTE
- (PORT datab (222:222:222) (291:291:291))
- (PORT datac (294:294:294) (398:398:398))
- (PORT datad (256:256:256) (294:294:294))
- (IOPATH datab combout (319:319:319) (324:324:324))
- (IOPATH datac combout (218:218:218) (216:216:216))
- (IOPATH datad combout (119:119:119) (106:106:106))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[10\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1361:1361:1361) (1379:1379:1379))
- (PORT d (67:67:67) (78:78:78))
- (IOPATH (posedge clk) q (180:180:180) (180:180:180))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (144:144:144))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~21)
- (DELAY
- (ABSOLUTE
- (PORT datab (324:324:324) (430:430:430))
- (PORT datac (196:196:196) (263:263:263))
- (PORT datad (256:256:256) (293:293:293))
- (IOPATH datab combout (275:275:275) (275:275:275))
- (IOPATH datac combout (220:220:220) (216:216:216))
- (IOPATH datad combout (119:119:119) (106:106:106))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[11\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1361:1361:1361) (1379:1379:1379))
- (PORT d (67:67:67) (78:78:78))
- (IOPATH (posedge clk) q (180:180:180) (180:180:180))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (144:144:144))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~20)
- (DELAY
- (ABSOLUTE
- (PORT datab (222:222:222) (291:291:291))
- (PORT datac (293:293:293) (396:396:396))
- (PORT datad (255:255:255) (292:292:292))
- (IOPATH datab combout (319:319:319) (324:324:324))
- (IOPATH datac combout (218:218:218) (216:216:216))
- (IOPATH datad combout (119:119:119) (106:106:106))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[12\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1361:1361:1361) (1379:1379:1379))
- (PORT d (67:67:67) (78:78:78))
- (IOPATH (posedge clk) q (180:180:180) (180:180:180))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (144:144:144))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~19)
- (DELAY
- (ABSOLUTE
- (PORT dataa (454:454:454) (530:530:530))
- (PORT datac (355:355:355) (395:395:395))
- (PORT datad (377:377:377) (388:388:388))
- (IOPATH dataa combout (273:273:273) (269:269:269))
- (IOPATH datac combout (220:220:220) (216:216:216))
- (IOPATH datad combout (119:119:119) (106:106:106))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[13\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1361:1361:1361) (1380:1380:1380))
- (PORT d (67:67:67) (78:78:78))
- (IOPATH (posedge clk) q (180:180:180) (180:180:180))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (144:144:144))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~18)
- (DELAY
- (ABSOLUTE
- (PORT datab (323:323:323) (430:430:430))
- (PORT datac (335:335:335) (380:380:380))
- (PORT datad (257:257:257) (298:298:298))
- (IOPATH datab combout (275:275:275) (275:275:275))
- (IOPATH datac combout (220:220:220) (216:216:216))
- (IOPATH datad combout (119:119:119) (106:106:106))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[14\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1361:1361:1361) (1379:1379:1379))
- (PORT d (67:67:67) (78:78:78))
- (IOPATH (posedge clk) q (180:180:180) (180:180:180))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (144:144:144))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~17)
- (DELAY
- (ABSOLUTE
- (PORT datab (224:224:224) (294:294:294))
- (PORT datac (286:286:286) (394:394:394))
- (PORT datad (257:257:257) (298:298:298))
- (IOPATH datab combout (319:319:319) (324:324:324))
- (IOPATH datac combout (218:218:218) (216:216:216))
- (IOPATH datad combout (119:119:119) (106:106:106))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[15\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1361:1361:1361) (1379:1379:1379))
- (PORT d (67:67:67) (78:78:78))
- (IOPATH (posedge clk) q (180:180:180) (180:180:180))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (144:144:144))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~16)
- (DELAY
- (ABSOLUTE
- (PORT datab (325:325:325) (430:430:430))
- (PORT datac (336:336:336) (375:375:375))
- (PORT datad (258:258:258) (295:295:295))
- (IOPATH datab combout (275:275:275) (275:275:275))
- (IOPATH datac combout (220:220:220) (216:216:216))
- (IOPATH datad combout (119:119:119) (106:106:106))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[16\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1361:1361:1361) (1379:1379:1379))
- (PORT d (67:67:67) (78:78:78))
- (IOPATH (posedge clk) q (180:180:180) (180:180:180))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (144:144:144))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~15)
- (DELAY
- (ABSOLUTE
- (PORT datab (223:223:223) (292:292:292))
- (PORT datac (290:290:290) (397:397:397))
- (PORT datad (257:257:257) (294:294:294))
- (IOPATH datab combout (319:319:319) (324:324:324))
- (IOPATH datac combout (218:218:218) (216:216:216))
- (IOPATH datad combout (119:119:119) (106:106:106))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[17\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1361:1361:1361) (1379:1379:1379))
- (PORT d (67:67:67) (78:78:78))
- (IOPATH (posedge clk) q (180:180:180) (180:180:180))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (144:144:144))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~14)
- (DELAY
- (ABSOLUTE
- (PORT datab (315:315:315) (420:420:420))
- (PORT datac (198:198:198) (266:266:266))
- (PORT datad (256:256:256) (295:295:295))
- (IOPATH datab combout (275:275:275) (275:275:275))
- (IOPATH datac combout (220:220:220) (216:216:216))
- (IOPATH datad combout (119:119:119) (106:106:106))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[18\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1361:1361:1361) (1379:1379:1379))
- (PORT d (67:67:67) (78:78:78))
- (IOPATH (posedge clk) q (180:180:180) (180:180:180))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (144:144:144))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~13)
- (DELAY
- (ABSOLUTE
- (PORT datab (508:508:508) (584:584:584))
- (PORT datac (370:370:370) (406:406:406))
- (PORT datad (437:437:437) (456:456:456))
- (IOPATH datab combout (275:275:275) (275:275:275))
- (IOPATH datac combout (220:220:220) (216:216:216))
- (IOPATH datad combout (119:119:119) (106:106:106))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[19\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1359:1359:1359) (1378:1378:1378))
- (PORT d (67:67:67) (78:78:78))
- (IOPATH (posedge clk) q (180:180:180) (180:180:180))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (144:144:144))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~12)
- (DELAY
- (ABSOLUTE
- (PORT datab (225:225:225) (294:294:294))
- (PORT datac (463:463:463) (549:549:549))
- (PORT datad (442:442:442) (463:463:463))
- (IOPATH datab combout (319:319:319) (324:324:324))
- (IOPATH datac combout (218:218:218) (216:216:216))
- (IOPATH datad combout (119:119:119) (106:106:106))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[20\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1359:1359:1359) (1378:1378:1378))
- (PORT d (67:67:67) (78:78:78))
- (IOPATH (posedge clk) q (180:180:180) (180:180:180))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (144:144:144))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~10)
- (DELAY
- (ABSOLUTE
- (PORT dataa (385:385:385) (432:432:432))
- (PORT datac (464:464:464) (547:547:547))
- (PORT datad (359:359:359) (390:390:390))
- (IOPATH dataa combout (318:318:318) (323:323:323))
- (IOPATH datac combout (220:220:220) (215:215:215))
- (IOPATH datad combout (119:119:119) (106:106:106))
- )
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~11)
- (DELAY
- (ABSOLUTE
- (PORT dataa (432:432:432) (466:466:466))
- (PORT datab (224:224:224) (294:294:294))
- (PORT datac (386:386:386) (419:419:419))
- (PORT datad (161:161:161) (183:183:183))
- (IOPATH dataa combout (300:300:300) (323:323:323))
- (IOPATH datab combout (308:308:308) (324:324:324))
- (IOPATH datac combout (220:220:220) (215:215:215))
- (IOPATH datad combout (119:119:119) (106:106:106))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[21\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1359:1359:1359) (1378:1378:1378))
- (PORT d (67:67:67) (78:78:78))
- (IOPATH (posedge clk) q (180:180:180) (180:180:180))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (144:144:144))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~9)
- (DELAY
- (ABSOLUTE
- (PORT dataa (226:226:226) (300:300:300))
- (PORT datac (466:466:466) (554:554:554))
- (PORT datad (440:440:440) (467:467:467))
- (IOPATH dataa combout (318:318:318) (323:323:323))
- (IOPATH datac combout (218:218:218) (216:216:216))
- (IOPATH datad combout (119:119:119) (106:106:106))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[22\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1359:1359:1359) (1378:1378:1378))
- (PORT d (67:67:67) (78:78:78))
- (IOPATH (posedge clk) q (180:180:180) (180:180:180))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (144:144:144))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~8)
- (DELAY
- (ABSOLUTE
- (PORT dataa (224:224:224) (296:296:296))
- (PORT datac (464:464:464) (546:546:546))
- (PORT datad (442:442:442) (463:463:463))
- (IOPATH dataa combout (318:318:318) (323:323:323))
- (IOPATH datac combout (218:218:218) (216:216:216))
- (IOPATH datad combout (119:119:119) (106:106:106))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[23\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1359:1359:1359) (1378:1378:1378))
- (PORT d (67:67:67) (78:78:78))
- (IOPATH (posedge clk) q (180:180:180) (180:180:180))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (144:144:144))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~7)
- (DELAY
- (ABSOLUTE
- (PORT dataa (223:223:223) (296:296:296))
- (PORT datac (465:465:465) (543:543:543))
- (PORT datad (440:440:440) (464:464:464))
- (IOPATH dataa combout (318:318:318) (323:323:323))
- (IOPATH datac combout (218:218:218) (216:216:216))
- (IOPATH datad combout (119:119:119) (106:106:106))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[24\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1359:1359:1359) (1378:1378:1378))
- (PORT d (67:67:67) (78:78:78))
- (IOPATH (posedge clk) q (180:180:180) (180:180:180))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (144:144:144))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~6)
- (DELAY
- (ABSOLUTE
- (PORT datab (225:225:225) (296:296:296))
- (PORT datac (475:475:475) (554:554:554))
- (PORT datad (437:437:437) (457:457:457))
- (IOPATH datab combout (319:319:319) (324:324:324))
- (IOPATH datac combout (218:218:218) (216:216:216))
- (IOPATH datad combout (119:119:119) (106:106:106))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[25\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1359:1359:1359) (1378:1378:1378))
- (PORT d (67:67:67) (78:78:78))
- (IOPATH (posedge clk) q (180:180:180) (180:180:180))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (144:144:144))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~5)
- (DELAY
- (ABSOLUTE
- (PORT dataa (224:224:224) (298:298:298))
- (PORT datac (476:476:476) (555:555:555))
- (PORT datad (433:433:433) (460:460:460))
- (IOPATH dataa combout (318:318:318) (323:323:323))
- (IOPATH datac combout (218:218:218) (216:216:216))
- (IOPATH datad combout (119:119:119) (106:106:106))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[26\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1359:1359:1359) (1378:1378:1378))
- (PORT d (67:67:67) (78:78:78))
- (IOPATH (posedge clk) q (180:180:180) (180:180:180))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (144:144:144))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~4)
- (DELAY
- (ABSOLUTE
- (PORT datab (224:224:224) (293:293:293))
- (PORT datac (469:469:469) (551:551:551))
- (PORT datad (439:439:439) (464:464:464))
- (IOPATH datab combout (319:319:319) (324:324:324))
- (IOPATH datac combout (218:218:218) (216:216:216))
- (IOPATH datad combout (119:119:119) (106:106:106))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[27\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1359:1359:1359) (1378:1378:1378))
- (PORT d (67:67:67) (78:78:78))
- (IOPATH (posedge clk) q (180:180:180) (180:180:180))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (144:144:144))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~3)
- (DELAY
- (ABSOLUTE
- (PORT datab (224:224:224) (293:293:293))
- (PORT datac (474:474:474) (553:553:553))
- (PORT datad (434:434:434) (463:463:463))
- (IOPATH datab combout (319:319:319) (324:324:324))
- (IOPATH datac combout (218:218:218) (216:216:216))
- (IOPATH datad combout (119:119:119) (106:106:106))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[28\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1359:1359:1359) (1378:1378:1378))
- (PORT d (67:67:67) (78:78:78))
- (IOPATH (posedge clk) q (180:180:180) (180:180:180))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (144:144:144))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~2)
- (DELAY
- (ABSOLUTE
- (PORT datab (224:224:224) (293:293:293))
- (PORT datac (475:475:475) (554:554:554))
- (PORT datad (433:433:433) (459:459:459))
- (IOPATH datab combout (319:319:319) (324:324:324))
- (IOPATH datac combout (218:218:218) (216:216:216))
- (IOPATH datad combout (119:119:119) (106:106:106))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[29\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1359:1359:1359) (1378:1378:1378))
- (PORT d (67:67:67) (78:78:78))
- (IOPATH (posedge clk) q (180:180:180) (180:180:180))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (144:144:144))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~1)
- (DELAY
- (ABSOLUTE
- (PORT datab (223:223:223) (291:291:291))
- (PORT datac (473:473:473) (557:557:557))
- (PORT datad (435:435:435) (456:456:456))
- (IOPATH datab combout (319:319:319) (324:324:324))
- (IOPATH datac combout (218:218:218) (216:216:216))
- (IOPATH datad combout (119:119:119) (106:106:106))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[30\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1359:1359:1359) (1378:1378:1378))
- (PORT d (67:67:67) (78:78:78))
- (IOPATH (posedge clk) q (180:180:180) (180:180:180))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (144:144:144))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~0)
- (DELAY
- (ABSOLUTE
- (PORT datab (223:223:223) (292:292:292))
- (PORT datac (472:472:472) (557:557:557))
- (PORT datad (434:434:434) (459:459:459))
- (IOPATH datab combout (319:319:319) (324:324:324))
- (IOPATH datac combout (218:218:218) (216:216:216))
- (IOPATH datad combout (119:119:119) (106:106:106))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[31\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1359:1359:1359) (1378:1378:1378))
- (PORT d (67:67:67) (78:78:78))
- (IOPATH (posedge clk) q (180:180:180) (180:180:180))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (144:144:144))
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|qdelayed)
- (DELAY
- (ABSOLUTE
- (PORT clk (1364:1364:1364) (1373:1373:1373))
- (PORT asdata (507:507:507) (570:570:570))
- (IOPATH (posedge clk) q (180:180:180) (180:180:180))
- )
- )
- (TIMINGCHECK
- (HOLD asdata (posedge clk) (144:144:144))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|miso\~0)
- (DELAY
- (ABSOLUTE
- (PORT datab (497:497:497) (571:571:571))
- (PORT datad (439:439:439) (458:458:458))
- (IOPATH datab combout (275:275:275) (275:275:275))
- (IOPATH datac combout (312:312:312) (325:325:325))
- (IOPATH datad combout (119:119:119) (106:106:106))
- )
- )
- )
- (CELL
- (CELLTYPE "cycloneive_io_ibuf")
- (INSTANCE GPIO_0_PI\[10\]\~input)
- (DELAY
- (ABSOLUTE
- (IOPATH i o (499:499:499) (643:643:643))
- )
- )
- )
-)
diff --git a/SPI/simulation/modelsim/SPI_test_6_1200mv_85c_slow.svo b/SPI/simulation/modelsim/SPI_test_6_1200mv_85c_slow.svo
deleted file mode 100644
index b296c1e0bca19b2f8d460fc4e4cf739508fc7cd5..0000000000000000000000000000000000000000
--- a/SPI/simulation/modelsim/SPI_test_6_1200mv_85c_slow.svo
+++ /dev/null
@@ -1,4083 +0,0 @@
-// Copyright (C) 2018 Intel Corporation. All rights reserved.
-// Your use of Intel Corporation's design tools, logic functions
-// and other software and tools, and its AMPP partner logic
-// functions, and any output files from any of the foregoing
-// (including device programming or simulation files), and any
-// associated documentation or information are expressly subject
-// to the terms and conditions of the Intel Program License
-// Subscription Agreement, the Intel Quartus Prime License Agreement,
-// the Intel FPGA IP License Agreement, or other applicable license
-// agreement, including, without limitation, that your use is for
-// the sole purpose of programming logic devices manufactured by
-// Intel and sold by Intel or its authorized distributors. Please
-// refer to the applicable agreement for further details.
-
-// VENDOR "Altera"
-// PROGRAM "Quartus Prime"
-// VERSION "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition"
-
-// DATE "11/16/2022 16:51:48"
-
-//
-// Device: Altera EP4CE22F17C6 Package FBGA256
-//
-
-//
-// This Verilog file should be used for ModelSim-Altera (SystemVerilog) only
-//
-
-`timescale 1 ps/ 1 ps
-
-module MyDE0_Nano (
- CLOCK_50,
- LED,
- KEY,
- GPIO_2,
- GPIO_2_IN,
- GPIO_0_PI,
- GPIO_0_PI_IN,
- GPIO_1,
- GPIO_1_IN);
-input CLOCK_50;
-output [7:0] LED;
-input [1:0] KEY;
-output [12:0] GPIO_2;
-input [2:0] GPIO_2_IN;
-output [33:0] GPIO_0_PI;
-input [1:0] GPIO_0_PI_IN;
-output [33:0] GPIO_1;
-input [1:0] GPIO_1_IN;
-
-// Design Ports Information
-// CLOCK_50 => Location: PIN_R7, I/O Standard: 2.5 V, Current Strength: Default
-// LED[0] => Location: PIN_A15, I/O Standard: 2.5 V, Current Strength: Default
-// LED[1] => Location: PIN_A13, I/O Standard: 2.5 V, Current Strength: Default
-// LED[2] => Location: PIN_B13, I/O Standard: 2.5 V, Current Strength: Default
-// LED[3] => Location: PIN_A11, I/O Standard: 2.5 V, Current Strength: Default
-// LED[4] => Location: PIN_D1, I/O Standard: 2.5 V, Current Strength: Default
-// LED[5] => Location: PIN_F3, I/O Standard: 2.5 V, Current Strength: Default
-// LED[6] => Location: PIN_B1, I/O Standard: 2.5 V, Current Strength: Default
-// LED[7] => Location: PIN_L3, I/O Standard: 2.5 V, Current Strength: Default
-// KEY[0] => Location: PIN_J15, I/O Standard: 2.5 V, Current Strength: Default
-// KEY[1] => Location: PIN_E1, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2_IN[0] => Location: PIN_E16, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2_IN[1] => Location: PIN_E15, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2_IN[2] => Location: PIN_D6, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI_IN[0] => Location: PIN_E6, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI_IN[1] => Location: PIN_C14, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1_IN[0] => Location: PIN_A12, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1_IN[1] => Location: PIN_T10, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[0] => Location: PIN_R4, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[1] => Location: PIN_D12, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[2] => Location: PIN_F2, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[3] => Location: PIN_G5, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[4] => Location: PIN_T4, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[5] => Location: PIN_J2, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[6] => Location: PIN_B3, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[7] => Location: PIN_D3, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[8] => Location: PIN_M7, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[9] => Location: PIN_T2, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[10] => Location: PIN_B12, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[11] => Location: PIN_C8, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[12] => Location: PIN_E8, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[0] => Location: PIN_A10, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[1] => Location: PIN_P2, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[2] => Location: PIN_R1, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[3] => Location: PIN_C6, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[4] => Location: PIN_T5, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[5] => Location: PIN_A5, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[6] => Location: PIN_P15, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[7] => Location: PIN_R5, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[12] => Location: PIN_P1, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[13] => Location: PIN_R16, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[14] => Location: PIN_C3, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[15] => Location: PIN_B10, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[16] => Location: PIN_F9, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[17] => Location: PIN_B6, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[18] => Location: PIN_R3, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[19] => Location: PIN_T12, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[20] => Location: PIN_J1, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[21] => Location: PIN_A14, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[22] => Location: PIN_R6, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[23] => Location: PIN_A7, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[24] => Location: PIN_B14, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[25] => Location: PIN_R13, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[26] => Location: PIN_L8, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[27] => Location: PIN_E10, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[28] => Location: PIN_C11, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[29] => Location: PIN_B11, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[30] => Location: PIN_B7, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[32] => Location: PIN_D8, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[33] => Location: PIN_B16, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[0] => Location: PIN_T6, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[1] => Location: PIN_N3, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[2] => Location: PIN_G16, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[3] => Location: PIN_F1, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[4] => Location: PIN_B4, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[5] => Location: PIN_L15, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[6] => Location: PIN_D14, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[7] => Location: PIN_N5, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[8] => Location: PIN_F15, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[9] => Location: PIN_R11, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[10] => Location: PIN_L1, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[11] => Location: PIN_E11, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[12] => Location: PIN_D15, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[13] => Location: PIN_T13, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[14] => Location: PIN_K16, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[15] => Location: PIN_C15, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[16] => Location: PIN_P8, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[17] => Location: PIN_R10, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[18] => Location: PIN_N1, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[19] => Location: PIN_C16, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[20] => Location: PIN_C2, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[21] => Location: PIN_N12, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[22] => Location: PIN_B5, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[23] => Location: PIN_M8, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[24] => Location: PIN_N6, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[25] => Location: PIN_F13, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[26] => Location: PIN_P3, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[27] => Location: PIN_M6, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[28] => Location: PIN_G1, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[29] => Location: PIN_J16, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[30] => Location: PIN_T14, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[31] => Location: PIN_R14, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[32] => Location: PIN_C9, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[33] => Location: PIN_L4, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[8] => Location: PIN_G2, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[9] => Location: PIN_D5, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[10] => Location: PIN_E7, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[11] => Location: PIN_A6, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[31] => Location: PIN_D11, I/O Standard: 2.5 V, Current Strength: Default
-
-
-wire gnd;
-wire vcc;
-wire unknown;
-
-assign gnd = 1'b0;
-assign vcc = 1'b1;
-assign unknown = 1'bx;
-
-tri1 devclrn;
-tri1 devpor;
-tri1 devoe;
-// synopsys translate_off
-initial $sdf_annotate("SPI_test_6_1200mv_85c_v_slow.sdo");
-// synopsys translate_on
-
-wire \CLOCK_50~input_o ;
-wire \KEY[0]~input_o ;
-wire \KEY[1]~input_o ;
-wire \GPIO_2_IN[0]~input_o ;
-wire \GPIO_2_IN[1]~input_o ;
-wire \GPIO_2_IN[2]~input_o ;
-wire \GPIO_0_PI_IN[0]~input_o ;
-wire \GPIO_0_PI_IN[1]~input_o ;
-wire \GPIO_1_IN[0]~input_o ;
-wire \GPIO_1_IN[1]~input_o ;
-wire \GPIO_2[0]~input_o ;
-wire \GPIO_2[1]~input_o ;
-wire \GPIO_2[2]~input_o ;
-wire \GPIO_2[3]~input_o ;
-wire \GPIO_2[4]~input_o ;
-wire \GPIO_2[5]~input_o ;
-wire \GPIO_2[6]~input_o ;
-wire \GPIO_2[7]~input_o ;
-wire \GPIO_2[8]~input_o ;
-wire \GPIO_2[9]~input_o ;
-wire \GPIO_2[10]~input_o ;
-wire \GPIO_2[11]~input_o ;
-wire \GPIO_2[12]~input_o ;
-wire \GPIO_0_PI[0]~input_o ;
-wire \GPIO_0_PI[1]~input_o ;
-wire \GPIO_0_PI[2]~input_o ;
-wire \GPIO_0_PI[3]~input_o ;
-wire \GPIO_0_PI[4]~input_o ;
-wire \GPIO_0_PI[5]~input_o ;
-wire \GPIO_0_PI[6]~input_o ;
-wire \GPIO_0_PI[7]~input_o ;
-wire \GPIO_0_PI[12]~input_o ;
-wire \GPIO_0_PI[13]~input_o ;
-wire \GPIO_0_PI[14]~input_o ;
-wire \GPIO_0_PI[15]~input_o ;
-wire \GPIO_0_PI[16]~input_o ;
-wire \GPIO_0_PI[17]~input_o ;
-wire \GPIO_0_PI[18]~input_o ;
-wire \GPIO_0_PI[19]~input_o ;
-wire \GPIO_0_PI[20]~input_o ;
-wire \GPIO_0_PI[21]~input_o ;
-wire \GPIO_0_PI[22]~input_o ;
-wire \GPIO_0_PI[23]~input_o ;
-wire \GPIO_0_PI[24]~input_o ;
-wire \GPIO_0_PI[25]~input_o ;
-wire \GPIO_0_PI[26]~input_o ;
-wire \GPIO_0_PI[27]~input_o ;
-wire \GPIO_0_PI[28]~input_o ;
-wire \GPIO_0_PI[29]~input_o ;
-wire \GPIO_0_PI[30]~input_o ;
-wire \GPIO_0_PI[32]~input_o ;
-wire \GPIO_0_PI[33]~input_o ;
-wire \GPIO_1[0]~input_o ;
-wire \GPIO_1[1]~input_o ;
-wire \GPIO_1[2]~input_o ;
-wire \GPIO_1[3]~input_o ;
-wire \GPIO_1[4]~input_o ;
-wire \GPIO_1[5]~input_o ;
-wire \GPIO_1[6]~input_o ;
-wire \GPIO_1[7]~input_o ;
-wire \GPIO_1[8]~input_o ;
-wire \GPIO_1[9]~input_o ;
-wire \GPIO_1[10]~input_o ;
-wire \GPIO_1[11]~input_o ;
-wire \GPIO_1[12]~input_o ;
-wire \GPIO_1[13]~input_o ;
-wire \GPIO_1[14]~input_o ;
-wire \GPIO_1[15]~input_o ;
-wire \GPIO_1[16]~input_o ;
-wire \GPIO_1[17]~input_o ;
-wire \GPIO_1[18]~input_o ;
-wire \GPIO_1[19]~input_o ;
-wire \GPIO_1[20]~input_o ;
-wire \GPIO_1[21]~input_o ;
-wire \GPIO_1[22]~input_o ;
-wire \GPIO_1[23]~input_o ;
-wire \GPIO_1[24]~input_o ;
-wire \GPIO_1[25]~input_o ;
-wire \GPIO_1[26]~input_o ;
-wire \GPIO_1[27]~input_o ;
-wire \GPIO_1[28]~input_o ;
-wire \GPIO_1[29]~input_o ;
-wire \GPIO_1[30]~input_o ;
-wire \GPIO_1[31]~input_o ;
-wire \GPIO_1[32]~input_o ;
-wire \GPIO_1[33]~input_o ;
-wire \GPIO_0_PI[11]~input_o ;
-wire \GPIO_2[0]~output_o ;
-wire \GPIO_2[1]~output_o ;
-wire \GPIO_2[2]~output_o ;
-wire \GPIO_2[3]~output_o ;
-wire \GPIO_2[4]~output_o ;
-wire \GPIO_2[5]~output_o ;
-wire \GPIO_2[6]~output_o ;
-wire \GPIO_2[7]~output_o ;
-wire \GPIO_2[8]~output_o ;
-wire \GPIO_2[9]~output_o ;
-wire \GPIO_2[10]~output_o ;
-wire \GPIO_2[11]~output_o ;
-wire \GPIO_2[12]~output_o ;
-wire \GPIO_0_PI[0]~output_o ;
-wire \GPIO_0_PI[1]~output_o ;
-wire \GPIO_0_PI[2]~output_o ;
-wire \GPIO_0_PI[3]~output_o ;
-wire \GPIO_0_PI[4]~output_o ;
-wire \GPIO_0_PI[5]~output_o ;
-wire \GPIO_0_PI[6]~output_o ;
-wire \GPIO_0_PI[7]~output_o ;
-wire \GPIO_0_PI[12]~output_o ;
-wire \GPIO_0_PI[13]~output_o ;
-wire \GPIO_0_PI[14]~output_o ;
-wire \GPIO_0_PI[15]~output_o ;
-wire \GPIO_0_PI[16]~output_o ;
-wire \GPIO_0_PI[17]~output_o ;
-wire \GPIO_0_PI[18]~output_o ;
-wire \GPIO_0_PI[19]~output_o ;
-wire \GPIO_0_PI[20]~output_o ;
-wire \GPIO_0_PI[21]~output_o ;
-wire \GPIO_0_PI[22]~output_o ;
-wire \GPIO_0_PI[23]~output_o ;
-wire \GPIO_0_PI[24]~output_o ;
-wire \GPIO_0_PI[25]~output_o ;
-wire \GPIO_0_PI[26]~output_o ;
-wire \GPIO_0_PI[27]~output_o ;
-wire \GPIO_0_PI[28]~output_o ;
-wire \GPIO_0_PI[29]~output_o ;
-wire \GPIO_0_PI[30]~output_o ;
-wire \GPIO_0_PI[32]~output_o ;
-wire \GPIO_0_PI[33]~output_o ;
-wire \GPIO_1[0]~output_o ;
-wire \GPIO_1[1]~output_o ;
-wire \GPIO_1[2]~output_o ;
-wire \GPIO_1[3]~output_o ;
-wire \GPIO_1[4]~output_o ;
-wire \GPIO_1[5]~output_o ;
-wire \GPIO_1[6]~output_o ;
-wire \GPIO_1[7]~output_o ;
-wire \GPIO_1[8]~output_o ;
-wire \GPIO_1[9]~output_o ;
-wire \GPIO_1[10]~output_o ;
-wire \GPIO_1[11]~output_o ;
-wire \GPIO_1[12]~output_o ;
-wire \GPIO_1[13]~output_o ;
-wire \GPIO_1[14]~output_o ;
-wire \GPIO_1[15]~output_o ;
-wire \GPIO_1[16]~output_o ;
-wire \GPIO_1[17]~output_o ;
-wire \GPIO_1[18]~output_o ;
-wire \GPIO_1[19]~output_o ;
-wire \GPIO_1[20]~output_o ;
-wire \GPIO_1[21]~output_o ;
-wire \GPIO_1[22]~output_o ;
-wire \GPIO_1[23]~output_o ;
-wire \GPIO_1[24]~output_o ;
-wire \GPIO_1[25]~output_o ;
-wire \GPIO_1[26]~output_o ;
-wire \GPIO_1[27]~output_o ;
-wire \GPIO_1[28]~output_o ;
-wire \GPIO_1[29]~output_o ;
-wire \GPIO_1[30]~output_o ;
-wire \GPIO_1[31]~output_o ;
-wire \GPIO_1[32]~output_o ;
-wire \GPIO_1[33]~output_o ;
-wire \GPIO_0_PI[8]~output_o ;
-wire \GPIO_0_PI[9]~output_o ;
-wire \GPIO_0_PI[10]~output_o ;
-wire \GPIO_0_PI[11]~output_o ;
-wire \GPIO_0_PI[31]~output_o ;
-wire \LED[0]~output_o ;
-wire \LED[1]~output_o ;
-wire \LED[2]~output_o ;
-wire \LED[3]~output_o ;
-wire \LED[4]~output_o ;
-wire \LED[5]~output_o ;
-wire \LED[6]~output_o ;
-wire \LED[7]~output_o ;
-wire \GPIO_0_PI[8]~input_o ;
-wire \GPIO_0_PI[8]~inputclkctrl_outclk ;
-wire \spi_slave_instance|cnt[0]~12_combout ;
-wire \spi_slave_instance|cnt[1]~4_combout ;
-wire \spi_slave_instance|cnt[1]~5 ;
-wire \spi_slave_instance|cnt[2]~6_combout ;
-wire \spi_slave_instance|cnt[2]~7 ;
-wire \spi_slave_instance|cnt[3]~8_combout ;
-wire \spi_slave_instance|cnt[3]~9 ;
-wire \spi_slave_instance|cnt[4]~10_combout ;
-wire \GPIO_0_PI[31]~input_o ;
-wire \GPIO_0_PI[9]~input_o ;
-wire \spi_slave_instance|Equal0~0_combout ;
-wire \spi_slave_instance|q~31_combout ;
-wire \spi_slave_instance|q~30_combout ;
-wire \spi_slave_instance|q~29_combout ;
-wire \spi_slave_instance|q~28_combout ;
-wire \spi_slave_instance|q~27_combout ;
-wire \spi_slave_instance|q~26_combout ;
-wire \spi_slave_instance|q~25_combout ;
-wire \spi_slave_instance|q~24_combout ;
-wire \spi_slave_instance|q~23_combout ;
-wire \spi_slave_instance|q~22_combout ;
-wire \spi_slave_instance|q~21_combout ;
-wire \spi_slave_instance|q~20_combout ;
-wire \spi_slave_instance|q~19_combout ;
-wire \spi_slave_instance|q~18_combout ;
-wire \spi_slave_instance|q~17_combout ;
-wire \spi_slave_instance|q~16_combout ;
-wire \spi_slave_instance|q~15_combout ;
-wire \spi_slave_instance|q~14_combout ;
-wire \spi_slave_instance|q~13_combout ;
-wire \spi_slave_instance|q~12_combout ;
-wire \spi_slave_instance|q~10_combout ;
-wire \spi_slave_instance|q~11_combout ;
-wire \spi_slave_instance|q~9_combout ;
-wire \spi_slave_instance|q~8_combout ;
-wire \spi_slave_instance|q~7_combout ;
-wire \spi_slave_instance|q~6_combout ;
-wire \spi_slave_instance|q~5_combout ;
-wire \spi_slave_instance|q~4_combout ;
-wire \spi_slave_instance|q~3_combout ;
-wire \spi_slave_instance|q~2_combout ;
-wire \spi_slave_instance|q~1_combout ;
-wire \spi_slave_instance|q~0_combout ;
-wire \spi_slave_instance|qdelayed~q ;
-wire \spi_slave_instance|miso~0_combout ;
-wire \GPIO_0_PI[10]~input_o ;
-wire [4:0] \spi_slave_instance|cnt ;
-wire [31:0] \spi_slave_instance|q ;
-
-
-hard_block auto_generated_inst(
- .devpor(devpor),
- .devclrn(devclrn),
- .devoe(devoe));
-
-// Location: IOOBUF_X5_Y0_N23
-cycloneive_io_obuf \GPIO_2[0]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[0]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[0]~output .bus_hold = "false";
-defparam \GPIO_2[0]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X51_Y34_N23
-cycloneive_io_obuf \GPIO_2[1]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[1]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[1]~output .bus_hold = "false";
-defparam \GPIO_2[1]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y24_N23
-cycloneive_io_obuf \GPIO_2[2]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[2]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[2]~output .bus_hold = "false";
-defparam \GPIO_2[2]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y24_N16
-cycloneive_io_obuf \GPIO_2[3]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[3]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[3]~output .bus_hold = "false";
-defparam \GPIO_2[3]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X5_Y0_N16
-cycloneive_io_obuf \GPIO_2[4]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[4]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[4]~output .bus_hold = "false";
-defparam \GPIO_2[4]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y15_N2
-cycloneive_io_obuf \GPIO_2[5]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[5]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[5]~output .bus_hold = "false";
-defparam \GPIO_2[5]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X3_Y34_N2
-cycloneive_io_obuf \GPIO_2[6]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[6]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[6]~output .bus_hold = "false";
-defparam \GPIO_2[6]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X1_Y34_N9
-cycloneive_io_obuf \GPIO_2[7]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[7]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[7]~output .bus_hold = "false";
-defparam \GPIO_2[7]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X11_Y0_N16
-cycloneive_io_obuf \GPIO_2[8]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[8]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[8]~output .bus_hold = "false";
-defparam \GPIO_2[8]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X3_Y0_N2
-cycloneive_io_obuf \GPIO_2[9]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[9]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[9]~output .bus_hold = "false";
-defparam \GPIO_2[9]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X43_Y34_N23
-cycloneive_io_obuf \GPIO_2[10]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[10]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[10]~output .bus_hold = "false";
-defparam \GPIO_2[10]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X23_Y34_N16
-cycloneive_io_obuf \GPIO_2[11]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[11]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[11]~output .bus_hold = "false";
-defparam \GPIO_2[11]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X20_Y34_N9
-cycloneive_io_obuf \GPIO_2[12]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[12]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[12]~output .bus_hold = "false";
-defparam \GPIO_2[12]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X34_Y34_N9
-cycloneive_io_obuf \GPIO_0_PI[0]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[0]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[0]~output .bus_hold = "false";
-defparam \GPIO_0_PI[0]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y4_N16
-cycloneive_io_obuf \GPIO_0_PI[1]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[1]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[1]~output .bus_hold = "false";
-defparam \GPIO_0_PI[1]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y5_N23
-cycloneive_io_obuf \GPIO_0_PI[2]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[2]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[2]~output .bus_hold = "false";
-defparam \GPIO_0_PI[2]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X18_Y34_N23
-cycloneive_io_obuf \GPIO_0_PI[3]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[3]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[3]~output .bus_hold = "false";
-defparam \GPIO_0_PI[3]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X14_Y0_N16
-cycloneive_io_obuf \GPIO_0_PI[4]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[4]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[4]~output .bus_hold = "false";
-defparam \GPIO_0_PI[4]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X14_Y34_N23
-cycloneive_io_obuf \GPIO_0_PI[5]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[5]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[5]~output .bus_hold = "false";
-defparam \GPIO_0_PI[5]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X53_Y6_N16
-cycloneive_io_obuf \GPIO_0_PI[6]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[6]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[6]~output .bus_hold = "false";
-defparam \GPIO_0_PI[6]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X14_Y0_N23
-cycloneive_io_obuf \GPIO_0_PI[7]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[7]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[7]~output .bus_hold = "false";
-defparam \GPIO_0_PI[7]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y4_N23
-cycloneive_io_obuf \GPIO_0_PI[12]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[12]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[12]~output .bus_hold = "false";
-defparam \GPIO_0_PI[12]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X53_Y8_N23
-cycloneive_io_obuf \GPIO_0_PI[13]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[13]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[13]~output .bus_hold = "false";
-defparam \GPIO_0_PI[13]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X1_Y34_N2
-cycloneive_io_obuf \GPIO_0_PI[14]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[14]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[14]~output .bus_hold = "false";
-defparam \GPIO_0_PI[14]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X34_Y34_N16
-cycloneive_io_obuf \GPIO_0_PI[15]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[15]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[15]~output .bus_hold = "false";
-defparam \GPIO_0_PI[15]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X34_Y34_N2
-cycloneive_io_obuf \GPIO_0_PI[16]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[16]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[16]~output .bus_hold = "false";
-defparam \GPIO_0_PI[16]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X16_Y34_N9
-cycloneive_io_obuf \GPIO_0_PI[17]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[17]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[17]~output .bus_hold = "false";
-defparam \GPIO_0_PI[17]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X1_Y0_N9
-cycloneive_io_obuf \GPIO_0_PI[18]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[18]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[18]~output .bus_hold = "false";
-defparam \GPIO_0_PI[18]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X36_Y0_N9
-cycloneive_io_obuf \GPIO_0_PI[19]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[19]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[19]~output .bus_hold = "false";
-defparam \GPIO_0_PI[19]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y15_N9
-cycloneive_io_obuf \GPIO_0_PI[20]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[20]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[20]~output .bus_hold = "false";
-defparam \GPIO_0_PI[20]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X47_Y34_N23
-cycloneive_io_obuf \GPIO_0_PI[21]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[21]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[21]~output .bus_hold = "false";
-defparam \GPIO_0_PI[21]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X14_Y0_N9
-cycloneive_io_obuf \GPIO_0_PI[22]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[22]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[22]~output .bus_hold = "false";
-defparam \GPIO_0_PI[22]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X20_Y34_N23
-cycloneive_io_obuf \GPIO_0_PI[23]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[23]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[23]~output .bus_hold = "false";
-defparam \GPIO_0_PI[23]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X45_Y34_N2
-cycloneive_io_obuf \GPIO_0_PI[24]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[24]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[24]~output .bus_hold = "false";
-defparam \GPIO_0_PI[24]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X40_Y0_N23
-cycloneive_io_obuf \GPIO_0_PI[25]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[25]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[25]~output .bus_hold = "false";
-defparam \GPIO_0_PI[25]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X18_Y0_N9
-cycloneive_io_obuf \GPIO_0_PI[26]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[26]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[26]~output .bus_hold = "false";
-defparam \GPIO_0_PI[26]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X45_Y34_N16
-cycloneive_io_obuf \GPIO_0_PI[27]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[27]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[27]~output .bus_hold = "false";
-defparam \GPIO_0_PI[27]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X38_Y34_N2
-cycloneive_io_obuf \GPIO_0_PI[28]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[28]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[28]~output .bus_hold = "false";
-defparam \GPIO_0_PI[28]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X40_Y34_N9
-cycloneive_io_obuf \GPIO_0_PI[29]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[29]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[29]~output .bus_hold = "false";
-defparam \GPIO_0_PI[29]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X18_Y34_N2
-cycloneive_io_obuf \GPIO_0_PI[30]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[30]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[30]~output .bus_hold = "false";
-defparam \GPIO_0_PI[30]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X23_Y34_N23
-cycloneive_io_obuf \GPIO_0_PI[32]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[32]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[32]~output .bus_hold = "false";
-defparam \GPIO_0_PI[32]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X53_Y22_N2
-cycloneive_io_obuf \GPIO_0_PI[33]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[33]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[33]~output .bus_hold = "false";
-defparam \GPIO_0_PI[33]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X14_Y0_N2
-cycloneive_io_obuf \GPIO_1[0]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[0]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[0]~output .bus_hold = "false";
-defparam \GPIO_1[0]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X1_Y0_N23
-cycloneive_io_obuf \GPIO_1[1]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[1]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[1]~output .bus_hold = "false";
-defparam \GPIO_1[1]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X53_Y20_N23
-cycloneive_io_obuf \GPIO_1[2]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[2]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[2]~output .bus_hold = "false";
-defparam \GPIO_1[2]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y23_N2
-cycloneive_io_obuf \GPIO_1[3]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[3]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[3]~output .bus_hold = "false";
-defparam \GPIO_1[3]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X7_Y34_N2
-cycloneive_io_obuf \GPIO_1[4]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[4]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[4]~output .bus_hold = "false";
-defparam \GPIO_1[4]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X53_Y11_N2
-cycloneive_io_obuf \GPIO_1[5]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[5]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[5]~output .bus_hold = "false";
-defparam \GPIO_1[5]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X51_Y34_N9
-cycloneive_io_obuf \GPIO_1[6]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[6]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[6]~output .bus_hold = "false";
-defparam \GPIO_1[6]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X5_Y0_N9
-cycloneive_io_obuf \GPIO_1[7]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[7]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[7]~output .bus_hold = "false";
-defparam \GPIO_1[7]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X53_Y22_N9
-cycloneive_io_obuf \GPIO_1[8]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[8]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[8]~output .bus_hold = "false";
-defparam \GPIO_1[8]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X34_Y0_N2
-cycloneive_io_obuf \GPIO_1[9]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[9]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[9]~output .bus_hold = "false";
-defparam \GPIO_1[9]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y11_N9
-cycloneive_io_obuf \GPIO_1[10]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[10]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[10]~output .bus_hold = "false";
-defparam \GPIO_1[10]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X45_Y34_N9
-cycloneive_io_obuf \GPIO_1[11]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[11]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[11]~output .bus_hold = "false";
-defparam \GPIO_1[11]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X53_Y26_N23
-cycloneive_io_obuf \GPIO_1[12]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[12]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[12]~output .bus_hold = "false";
-defparam \GPIO_1[12]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X40_Y0_N16
-cycloneive_io_obuf \GPIO_1[13]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[13]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[13]~output .bus_hold = "false";
-defparam \GPIO_1[13]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X53_Y12_N2
-cycloneive_io_obuf \GPIO_1[14]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[14]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[14]~output .bus_hold = "false";
-defparam \GPIO_1[14]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X53_Y30_N2
-cycloneive_io_obuf \GPIO_1[15]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[15]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[15]~output .bus_hold = "false";
-defparam \GPIO_1[15]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X25_Y0_N16
-cycloneive_io_obuf \GPIO_1[16]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[16]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[16]~output .bus_hold = "false";
-defparam \GPIO_1[16]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X34_Y0_N23
-cycloneive_io_obuf \GPIO_1[17]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[17]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[17]~output .bus_hold = "false";
-defparam \GPIO_1[17]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y7_N2
-cycloneive_io_obuf \GPIO_1[18]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[18]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[18]~output .bus_hold = "false";
-defparam \GPIO_1[18]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X53_Y30_N9
-cycloneive_io_obuf \GPIO_1[19]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[19]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[19]~output .bus_hold = "false";
-defparam \GPIO_1[19]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y27_N2
-cycloneive_io_obuf \GPIO_1[20]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[20]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[20]~output .bus_hold = "false";
-defparam \GPIO_1[20]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X47_Y0_N23
-cycloneive_io_obuf \GPIO_1[21]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[21]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[21]~output .bus_hold = "false";
-defparam \GPIO_1[21]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X11_Y34_N2
-cycloneive_io_obuf \GPIO_1[22]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[22]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[22]~output .bus_hold = "false";
-defparam \GPIO_1[22]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X20_Y0_N9
-cycloneive_io_obuf \GPIO_1[23]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[23]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[23]~output .bus_hold = "false";
-defparam \GPIO_1[23]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X5_Y0_N2
-cycloneive_io_obuf \GPIO_1[24]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[24]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[24]~output .bus_hold = "false";
-defparam \GPIO_1[24]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X53_Y21_N23
-cycloneive_io_obuf \GPIO_1[25]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[25]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[25]~output .bus_hold = "false";
-defparam \GPIO_1[25]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X1_Y0_N16
-cycloneive_io_obuf \GPIO_1[26]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[26]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[26]~output .bus_hold = "false";
-defparam \GPIO_1[26]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X7_Y0_N9
-cycloneive_io_obuf \GPIO_1[27]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[27]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[27]~output .bus_hold = "false";
-defparam \GPIO_1[27]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y23_N23
-cycloneive_io_obuf \GPIO_1[28]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[28]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[28]~output .bus_hold = "false";
-defparam \GPIO_1[28]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X53_Y14_N9
-cycloneive_io_obuf \GPIO_1[29]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[29]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[29]~output .bus_hold = "false";
-defparam \GPIO_1[29]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X45_Y0_N23
-cycloneive_io_obuf \GPIO_1[30]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[30]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[30]~output .bus_hold = "false";
-defparam \GPIO_1[30]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X49_Y0_N2
-cycloneive_io_obuf \GPIO_1[31]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[31]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[31]~output .bus_hold = "false";
-defparam \GPIO_1[31]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X31_Y34_N2
-cycloneive_io_obuf \GPIO_1[32]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[32]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[32]~output .bus_hold = "false";
-defparam \GPIO_1[32]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y6_N16
-cycloneive_io_obuf \GPIO_1[33]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[33]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[33]~output .bus_hold = "false";
-defparam \GPIO_1[33]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y23_N16
-cycloneive_io_obuf \GPIO_0_PI[8]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[8]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[8]~output .bus_hold = "false";
-defparam \GPIO_0_PI[8]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X5_Y34_N16
-cycloneive_io_obuf \GPIO_0_PI[9]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[9]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[9]~output .bus_hold = "false";
-defparam \GPIO_0_PI[9]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X16_Y34_N16
-cycloneive_io_obuf \GPIO_0_PI[10]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[10]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[10]~output .bus_hold = "false";
-defparam \GPIO_0_PI[10]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X16_Y34_N2
-cycloneive_io_obuf \GPIO_0_PI[11]~output (
- .i(\spi_slave_instance|miso~0_combout ),
- .oe(!\GPIO_0_PI[10]~input_o ),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[11]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[11]~output .bus_hold = "false";
-defparam \GPIO_0_PI[11]~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X51_Y34_N16
-cycloneive_io_obuf \GPIO_0_PI[31]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[31]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[31]~output .bus_hold = "false";
-defparam \GPIO_0_PI[31]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X38_Y34_N16
-cycloneive_io_obuf \LED[0]~output (
- .i(gnd),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\LED[0]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \LED[0]~output .bus_hold = "false";
-defparam \LED[0]~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X49_Y34_N2
-cycloneive_io_obuf \LED[1]~output (
- .i(gnd),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\LED[1]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \LED[1]~output .bus_hold = "false";
-defparam \LED[1]~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X49_Y34_N9
-cycloneive_io_obuf \LED[2]~output (
- .i(gnd),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\LED[2]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \LED[2]~output .bus_hold = "false";
-defparam \LED[2]~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X40_Y34_N2
-cycloneive_io_obuf \LED[3]~output (
- .i(gnd),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\LED[3]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \LED[3]~output .bus_hold = "false";
-defparam \LED[3]~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y25_N9
-cycloneive_io_obuf \LED[4]~output (
- .i(gnd),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\LED[4]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \LED[4]~output .bus_hold = "false";
-defparam \LED[4]~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y26_N16
-cycloneive_io_obuf \LED[5]~output (
- .i(gnd),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\LED[5]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \LED[5]~output .bus_hold = "false";
-defparam \LED[5]~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y28_N9
-cycloneive_io_obuf \LED[6]~output (
- .i(gnd),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\LED[6]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \LED[6]~output .bus_hold = "false";
-defparam \LED[6]~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y10_N23
-cycloneive_io_obuf \LED[7]~output (
- .i(gnd),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\LED[7]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \LED[7]~output .bus_hold = "false";
-defparam \LED[7]~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y23_N15
-cycloneive_io_ibuf \GPIO_0_PI[8]~input (
- .i(GPIO_0_PI[8]),
- .ibar(gnd),
- .o(\GPIO_0_PI[8]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[8]~input .bus_hold = "false";
-defparam \GPIO_0_PI[8]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: CLKCTRL_G0
-cycloneive_clkctrl \GPIO_0_PI[8]~inputclkctrl (
- .ena(vcc),
- .inclk({vcc,vcc,vcc,\GPIO_0_PI[8]~input_o }),
- .clkselect(2'b00),
- .devclrn(devclrn),
- .devpor(devpor),
- .outclk(\GPIO_0_PI[8]~inputclkctrl_outclk ));
-// synopsys translate_off
-defparam \GPIO_0_PI[8]~inputclkctrl .clock_type = "global clock";
-defparam \GPIO_0_PI[8]~inputclkctrl .ena_register_mode = "none";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N12
-cycloneive_lcell_comb \spi_slave_instance|cnt[0]~12 (
-// Equation(s):
-// \spi_slave_instance|cnt[0]~12_combout = !\spi_slave_instance|cnt [0]
-
- .dataa(gnd),
- .datab(gnd),
- .datac(\spi_slave_instance|cnt [0]),
- .datad(gnd),
- .cin(gnd),
- .combout(\spi_slave_instance|cnt[0]~12_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|cnt[0]~12 .lut_mask = 16'h0F0F;
-defparam \spi_slave_instance|cnt[0]~12 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N13
-dffeas \spi_slave_instance|cnt[0] (
- .clk(!\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|cnt[0]~12_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|cnt [0]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|cnt[0] .is_wysiwyg = "true";
-defparam \spi_slave_instance|cnt[0] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N2
-cycloneive_lcell_comb \spi_slave_instance|cnt[1]~4 (
-// Equation(s):
-// \spi_slave_instance|cnt[1]~4_combout = (\spi_slave_instance|cnt [0] & (\spi_slave_instance|cnt [1] $ (VCC))) # (!\spi_slave_instance|cnt [0] & (\spi_slave_instance|cnt [1] & VCC))
-// \spi_slave_instance|cnt[1]~5 = CARRY((\spi_slave_instance|cnt [0] & \spi_slave_instance|cnt [1]))
-
- .dataa(\spi_slave_instance|cnt [0]),
- .datab(\spi_slave_instance|cnt [1]),
- .datac(gnd),
- .datad(vcc),
- .cin(gnd),
- .combout(\spi_slave_instance|cnt[1]~4_combout ),
- .cout(\spi_slave_instance|cnt[1]~5 ));
-// synopsys translate_off
-defparam \spi_slave_instance|cnt[1]~4 .lut_mask = 16'h6688;
-defparam \spi_slave_instance|cnt[1]~4 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N3
-dffeas \spi_slave_instance|cnt[1] (
- .clk(!\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|cnt[1]~4_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|cnt [1]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|cnt[1] .is_wysiwyg = "true";
-defparam \spi_slave_instance|cnt[1] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N4
-cycloneive_lcell_comb \spi_slave_instance|cnt[2]~6 (
-// Equation(s):
-// \spi_slave_instance|cnt[2]~6_combout = (\spi_slave_instance|cnt [2] & (!\spi_slave_instance|cnt[1]~5 )) # (!\spi_slave_instance|cnt [2] & ((\spi_slave_instance|cnt[1]~5 ) # (GND)))
-// \spi_slave_instance|cnt[2]~7 = CARRY((!\spi_slave_instance|cnt[1]~5 ) # (!\spi_slave_instance|cnt [2]))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|cnt [2]),
- .datac(gnd),
- .datad(vcc),
- .cin(\spi_slave_instance|cnt[1]~5 ),
- .combout(\spi_slave_instance|cnt[2]~6_combout ),
- .cout(\spi_slave_instance|cnt[2]~7 ));
-// synopsys translate_off
-defparam \spi_slave_instance|cnt[2]~6 .lut_mask = 16'h3C3F;
-defparam \spi_slave_instance|cnt[2]~6 .sum_lutc_input = "cin";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N5
-dffeas \spi_slave_instance|cnt[2] (
- .clk(!\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|cnt[2]~6_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|cnt [2]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|cnt[2] .is_wysiwyg = "true";
-defparam \spi_slave_instance|cnt[2] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N6
-cycloneive_lcell_comb \spi_slave_instance|cnt[3]~8 (
-// Equation(s):
-// \spi_slave_instance|cnt[3]~8_combout = (\spi_slave_instance|cnt [3] & (\spi_slave_instance|cnt[2]~7 $ (GND))) # (!\spi_slave_instance|cnt [3] & (!\spi_slave_instance|cnt[2]~7 & VCC))
-// \spi_slave_instance|cnt[3]~9 = CARRY((\spi_slave_instance|cnt [3] & !\spi_slave_instance|cnt[2]~7 ))
-
- .dataa(\spi_slave_instance|cnt [3]),
- .datab(gnd),
- .datac(gnd),
- .datad(vcc),
- .cin(\spi_slave_instance|cnt[2]~7 ),
- .combout(\spi_slave_instance|cnt[3]~8_combout ),
- .cout(\spi_slave_instance|cnt[3]~9 ));
-// synopsys translate_off
-defparam \spi_slave_instance|cnt[3]~8 .lut_mask = 16'hA50A;
-defparam \spi_slave_instance|cnt[3]~8 .sum_lutc_input = "cin";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N7
-dffeas \spi_slave_instance|cnt[3] (
- .clk(!\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|cnt[3]~8_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|cnt [3]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|cnt[3] .is_wysiwyg = "true";
-defparam \spi_slave_instance|cnt[3] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N8
-cycloneive_lcell_comb \spi_slave_instance|cnt[4]~10 (
-// Equation(s):
-// \spi_slave_instance|cnt[4]~10_combout = \spi_slave_instance|cnt [4] $ (\spi_slave_instance|cnt[3]~9 )
-
- .dataa(gnd),
- .datab(\spi_slave_instance|cnt [4]),
- .datac(gnd),
- .datad(gnd),
- .cin(\spi_slave_instance|cnt[3]~9 ),
- .combout(\spi_slave_instance|cnt[4]~10_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|cnt[4]~10 .lut_mask = 16'h3C3C;
-defparam \spi_slave_instance|cnt[4]~10 .sum_lutc_input = "cin";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N9
-dffeas \spi_slave_instance|cnt[4] (
- .clk(!\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|cnt[4]~10_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|cnt [4]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|cnt[4] .is_wysiwyg = "true";
-defparam \spi_slave_instance|cnt[4] .power_up = "low";
-// synopsys translate_on
-
-// Location: IOIBUF_X51_Y34_N15
-cycloneive_io_ibuf \GPIO_0_PI[31]~input (
- .i(GPIO_0_PI[31]),
- .ibar(gnd),
- .o(\GPIO_0_PI[31]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[31]~input .bus_hold = "false";
-defparam \GPIO_0_PI[31]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X5_Y34_N15
-cycloneive_io_ibuf \GPIO_0_PI[9]~input (
- .i(GPIO_0_PI[9]),
- .ibar(gnd),
- .o(\GPIO_0_PI[9]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[9]~input .bus_hold = "false";
-defparam \GPIO_0_PI[9]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: FF_X21_Y31_N5
-dffeas \spi_slave_instance|q[0] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(gnd),
- .asdata(\GPIO_0_PI[9]~input_o ),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(vcc),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [0]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[0] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[0] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N18
-cycloneive_lcell_comb \spi_slave_instance|Equal0~0 (
-// Equation(s):
-// \spi_slave_instance|Equal0~0_combout = (!\spi_slave_instance|cnt [0] & (!\spi_slave_instance|cnt [1] & (!\spi_slave_instance|cnt [2] & !\spi_slave_instance|cnt [3])))
-
- .dataa(\spi_slave_instance|cnt [0]),
- .datab(\spi_slave_instance|cnt [1]),
- .datac(\spi_slave_instance|cnt [2]),
- .datad(\spi_slave_instance|cnt [3]),
- .cin(gnd),
- .combout(\spi_slave_instance|Equal0~0_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|Equal0~0 .lut_mask = 16'h0001;
-defparam \spi_slave_instance|Equal0~0 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: LCCOMB_X21_Y31_N22
-cycloneive_lcell_comb \spi_slave_instance|q~31 (
-// Equation(s):
-// \spi_slave_instance|q~31_combout = (\spi_slave_instance|cnt [4] & (((\spi_slave_instance|q [0])))) # (!\spi_slave_instance|cnt [4] & ((\spi_slave_instance|Equal0~0_combout & (\GPIO_0_PI[31]~input_o )) # (!\spi_slave_instance|Equal0~0_combout &
-// ((\spi_slave_instance|q [0])))))
-
- .dataa(\spi_slave_instance|cnt [4]),
- .datab(\GPIO_0_PI[31]~input_o ),
- .datac(\spi_slave_instance|q [0]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~31_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~31 .lut_mask = 16'hE4F0;
-defparam \spi_slave_instance|q~31 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X21_Y31_N23
-dffeas \spi_slave_instance|q[1] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~31_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [1]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[1] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[1] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X21_Y31_N24
-cycloneive_lcell_comb \spi_slave_instance|q~30 (
-// Equation(s):
-// \spi_slave_instance|q~30_combout = (\spi_slave_instance|q [1] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(\spi_slave_instance|cnt [4]),
- .datab(gnd),
- .datac(\spi_slave_instance|q [1]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~30_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~30 .lut_mask = 16'hA0F0;
-defparam \spi_slave_instance|q~30 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X21_Y31_N25
-dffeas \spi_slave_instance|q[2] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~30_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [2]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[2] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[2] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X21_Y31_N30
-cycloneive_lcell_comb \spi_slave_instance|q~29 (
-// Equation(s):
-// \spi_slave_instance|q~29_combout = (\spi_slave_instance|q [2] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(\spi_slave_instance|cnt [4]),
- .datab(\spi_slave_instance|q [2]),
- .datac(gnd),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~29_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~29 .lut_mask = 16'h88CC;
-defparam \spi_slave_instance|q~29 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X21_Y31_N31
-dffeas \spi_slave_instance|q[3] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~29_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [3]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[3] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[3] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X21_Y31_N8
-cycloneive_lcell_comb \spi_slave_instance|q~28 (
-// Equation(s):
-// \spi_slave_instance|q~28_combout = (\spi_slave_instance|q [3] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(\spi_slave_instance|cnt [4]),
- .datab(gnd),
- .datac(\spi_slave_instance|q [3]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~28_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~28 .lut_mask = 16'hA0F0;
-defparam \spi_slave_instance|q~28 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X21_Y31_N9
-dffeas \spi_slave_instance|q[4] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~28_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [4]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[4] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[4] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X21_Y31_N18
-cycloneive_lcell_comb \spi_slave_instance|q~27 (
-// Equation(s):
-// \spi_slave_instance|q~27_combout = (\spi_slave_instance|q [4] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(\spi_slave_instance|cnt [4]),
- .datab(gnd),
- .datac(\spi_slave_instance|q [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~27_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~27 .lut_mask = 16'hA0F0;
-defparam \spi_slave_instance|q~27 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X21_Y31_N19
-dffeas \spi_slave_instance|q[5] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~27_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [5]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[5] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[5] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X21_Y31_N28
-cycloneive_lcell_comb \spi_slave_instance|q~26 (
-// Equation(s):
-// \spi_slave_instance|q~26_combout = (\spi_slave_instance|q [5] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(\spi_slave_instance|cnt [4]),
- .datab(\spi_slave_instance|q [5]),
- .datac(gnd),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~26_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~26 .lut_mask = 16'h88CC;
-defparam \spi_slave_instance|q~26 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X21_Y31_N29
-dffeas \spi_slave_instance|q[6] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~26_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [6]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[6] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[6] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X21_Y31_N10
-cycloneive_lcell_comb \spi_slave_instance|q~25 (
-// Equation(s):
-// \spi_slave_instance|q~25_combout = (\spi_slave_instance|q [6] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(\spi_slave_instance|cnt [4]),
- .datab(\spi_slave_instance|q [6]),
- .datac(gnd),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~25_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~25 .lut_mask = 16'h88CC;
-defparam \spi_slave_instance|q~25 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X21_Y31_N11
-dffeas \spi_slave_instance|q[7] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~25_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [7]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[7] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[7] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N14
-cycloneive_lcell_comb \spi_slave_instance|q~24 (
-// Equation(s):
-// \spi_slave_instance|q~24_combout = (\spi_slave_instance|q [7] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|cnt [4]),
- .datac(\spi_slave_instance|q [7]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~24_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~24 .lut_mask = 16'hC0F0;
-defparam \spi_slave_instance|q~24 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N15
-dffeas \spi_slave_instance|q[8] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~24_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [8]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[8] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[8] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N28
-cycloneive_lcell_comb \spi_slave_instance|q~23 (
-// Equation(s):
-// \spi_slave_instance|q~23_combout = (\spi_slave_instance|q [8] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|q [8]),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~23_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~23 .lut_mask = 16'hC0CC;
-defparam \spi_slave_instance|q~23 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N29
-dffeas \spi_slave_instance|q[9] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~23_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [9]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[9] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[9] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N30
-cycloneive_lcell_comb \spi_slave_instance|q~22 (
-// Equation(s):
-// \spi_slave_instance|q~22_combout = (\spi_slave_instance|q [9] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|q [9]),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~22_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~22 .lut_mask = 16'hC0CC;
-defparam \spi_slave_instance|q~22 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N31
-dffeas \spi_slave_instance|q[10] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~22_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [10]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[10] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[10] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N24
-cycloneive_lcell_comb \spi_slave_instance|q~21 (
-// Equation(s):
-// \spi_slave_instance|q~21_combout = (\spi_slave_instance|q [10] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|cnt [4]),
- .datac(\spi_slave_instance|q [10]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~21_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~21 .lut_mask = 16'hC0F0;
-defparam \spi_slave_instance|q~21 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N25
-dffeas \spi_slave_instance|q[11] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~21_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [11]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[11] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[11] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N26
-cycloneive_lcell_comb \spi_slave_instance|q~20 (
-// Equation(s):
-// \spi_slave_instance|q~20_combout = (\spi_slave_instance|q [11] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|q [11]),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~20_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~20 .lut_mask = 16'hC0CC;
-defparam \spi_slave_instance|q~20 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N27
-dffeas \spi_slave_instance|q[12] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~20_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [12]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[12] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[12] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X21_Y31_N20
-cycloneive_lcell_comb \spi_slave_instance|q~19 (
-// Equation(s):
-// \spi_slave_instance|q~19_combout = (\spi_slave_instance|q [12] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(\spi_slave_instance|cnt [4]),
- .datab(gnd),
- .datac(\spi_slave_instance|q [12]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~19_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~19 .lut_mask = 16'hA0F0;
-defparam \spi_slave_instance|q~19 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X21_Y31_N21
-dffeas \spi_slave_instance|q[13] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~19_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [13]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[13] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[13] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N16
-cycloneive_lcell_comb \spi_slave_instance|q~18 (
-// Equation(s):
-// \spi_slave_instance|q~18_combout = (\spi_slave_instance|q [13] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|cnt [4]),
- .datac(\spi_slave_instance|q [13]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~18_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~18 .lut_mask = 16'hC0F0;
-defparam \spi_slave_instance|q~18 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N17
-dffeas \spi_slave_instance|q[14] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~18_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [14]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[14] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[14] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N10
-cycloneive_lcell_comb \spi_slave_instance|q~17 (
-// Equation(s):
-// \spi_slave_instance|q~17_combout = (\spi_slave_instance|q [14] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|q [14]),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~17_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~17 .lut_mask = 16'hC0CC;
-defparam \spi_slave_instance|q~17 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N11
-dffeas \spi_slave_instance|q[15] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~17_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [15]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[15] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[15] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N20
-cycloneive_lcell_comb \spi_slave_instance|q~16 (
-// Equation(s):
-// \spi_slave_instance|q~16_combout = (\spi_slave_instance|q [15] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|cnt [4]),
- .datac(\spi_slave_instance|q [15]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~16_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~16 .lut_mask = 16'hC0F0;
-defparam \spi_slave_instance|q~16 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N21
-dffeas \spi_slave_instance|q[16] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~16_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [16]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[16] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[16] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N22
-cycloneive_lcell_comb \spi_slave_instance|q~15 (
-// Equation(s):
-// \spi_slave_instance|q~15_combout = (\spi_slave_instance|q [16] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|q [16]),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~15_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~15 .lut_mask = 16'hC0CC;
-defparam \spi_slave_instance|q~15 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N23
-dffeas \spi_slave_instance|q[17] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~15_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [17]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[17] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[17] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N0
-cycloneive_lcell_comb \spi_slave_instance|q~14 (
-// Equation(s):
-// \spi_slave_instance|q~14_combout = (\spi_slave_instance|q [17] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|cnt [4]),
- .datac(\spi_slave_instance|q [17]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~14_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~14 .lut_mask = 16'hC0F0;
-defparam \spi_slave_instance|q~14 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N1
-dffeas \spi_slave_instance|q[18] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~14_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [18]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[18] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[18] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N28
-cycloneive_lcell_comb \spi_slave_instance|q~13 (
-// Equation(s):
-// \spi_slave_instance|q~13_combout = (\spi_slave_instance|q [18] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|cnt [4]),
- .datac(\spi_slave_instance|q [18]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~13_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~13 .lut_mask = 16'hC0F0;
-defparam \spi_slave_instance|q~13 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N29
-dffeas \spi_slave_instance|q[19] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~13_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [19]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[19] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[19] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N8
-cycloneive_lcell_comb \spi_slave_instance|q~12 (
-// Equation(s):
-// \spi_slave_instance|q~12_combout = (\spi_slave_instance|q [19] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|q [19]),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~12_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~12 .lut_mask = 16'hC0CC;
-defparam \spi_slave_instance|q~12 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N9
-dffeas \spi_slave_instance|q[20] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~12_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [20]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[20] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[20] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N10
-cycloneive_lcell_comb \spi_slave_instance|q~10 (
-// Equation(s):
-// \spi_slave_instance|q~10_combout = (\spi_slave_instance|cnt [1]) # ((\spi_slave_instance|cnt [4]) # (\spi_slave_instance|cnt [3]))
-
- .dataa(\spi_slave_instance|cnt [1]),
- .datab(gnd),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|cnt [3]),
- .cin(gnd),
- .combout(\spi_slave_instance|q~10_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~10 .lut_mask = 16'hFFFA;
-defparam \spi_slave_instance|q~10 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N26
-cycloneive_lcell_comb \spi_slave_instance|q~11 (
-// Equation(s):
-// \spi_slave_instance|q~11_combout = (\spi_slave_instance|q [20] & ((\spi_slave_instance|cnt [2]) # ((\spi_slave_instance|cnt [0]) # (\spi_slave_instance|q~10_combout ))))
-
- .dataa(\spi_slave_instance|cnt [2]),
- .datab(\spi_slave_instance|q [20]),
- .datac(\spi_slave_instance|cnt [0]),
- .datad(\spi_slave_instance|q~10_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~11_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~11 .lut_mask = 16'hCCC8;
-defparam \spi_slave_instance|q~11 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N27
-dffeas \spi_slave_instance|q[21] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~11_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [21]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[21] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[21] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N12
-cycloneive_lcell_comb \spi_slave_instance|q~9 (
-// Equation(s):
-// \spi_slave_instance|q~9_combout = (\spi_slave_instance|q [21] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(\spi_slave_instance|q [21]),
- .datab(gnd),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~9_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~9 .lut_mask = 16'hA0AA;
-defparam \spi_slave_instance|q~9 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N13
-dffeas \spi_slave_instance|q[22] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~9_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [22]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[22] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[22] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N6
-cycloneive_lcell_comb \spi_slave_instance|q~8 (
-// Equation(s):
-// \spi_slave_instance|q~8_combout = (\spi_slave_instance|q [22] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(\spi_slave_instance|q [22]),
- .datab(gnd),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~8_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~8 .lut_mask = 16'hA0AA;
-defparam \spi_slave_instance|q~8 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N7
-dffeas \spi_slave_instance|q[23] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~8_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [23]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[23] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[23] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N4
-cycloneive_lcell_comb \spi_slave_instance|q~7 (
-// Equation(s):
-// \spi_slave_instance|q~7_combout = (\spi_slave_instance|q [23] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(\spi_slave_instance|q [23]),
- .datab(gnd),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~7_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~7 .lut_mask = 16'hA0AA;
-defparam \spi_slave_instance|q~7 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N5
-dffeas \spi_slave_instance|q[24] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~7_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [24]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[24] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[24] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N30
-cycloneive_lcell_comb \spi_slave_instance|q~6 (
-// Equation(s):
-// \spi_slave_instance|q~6_combout = (\spi_slave_instance|q [24] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|q [24]),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~6_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~6 .lut_mask = 16'hC0CC;
-defparam \spi_slave_instance|q~6 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N31
-dffeas \spi_slave_instance|q[25] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~6_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [25]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[25] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[25] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N20
-cycloneive_lcell_comb \spi_slave_instance|q~5 (
-// Equation(s):
-// \spi_slave_instance|q~5_combout = (\spi_slave_instance|q [25] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(\spi_slave_instance|q [25]),
- .datab(gnd),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~5_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~5 .lut_mask = 16'hA0AA;
-defparam \spi_slave_instance|q~5 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N21
-dffeas \spi_slave_instance|q[26] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~5_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [26]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[26] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[26] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N14
-cycloneive_lcell_comb \spi_slave_instance|q~4 (
-// Equation(s):
-// \spi_slave_instance|q~4_combout = (\spi_slave_instance|q [26] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|q [26]),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~4_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~4 .lut_mask = 16'hC0CC;
-defparam \spi_slave_instance|q~4 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N15
-dffeas \spi_slave_instance|q[27] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~4_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [27]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[27] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[27] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N16
-cycloneive_lcell_comb \spi_slave_instance|q~3 (
-// Equation(s):
-// \spi_slave_instance|q~3_combout = (\spi_slave_instance|q [27] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|q [27]),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~3_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~3 .lut_mask = 16'hC0CC;
-defparam \spi_slave_instance|q~3 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N17
-dffeas \spi_slave_instance|q[28] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~3_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [28]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[28] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[28] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N18
-cycloneive_lcell_comb \spi_slave_instance|q~2 (
-// Equation(s):
-// \spi_slave_instance|q~2_combout = (\spi_slave_instance|q [28] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|q [28]),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~2_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~2 .lut_mask = 16'hC0CC;
-defparam \spi_slave_instance|q~2 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N19
-dffeas \spi_slave_instance|q[29] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~2_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [29]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[29] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[29] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N24
-cycloneive_lcell_comb \spi_slave_instance|q~1 (
-// Equation(s):
-// \spi_slave_instance|q~1_combout = (\spi_slave_instance|q [29] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|q [29]),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~1_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~1 .lut_mask = 16'hC0CC;
-defparam \spi_slave_instance|q~1 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N25
-dffeas \spi_slave_instance|q[30] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~1_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [30]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[30] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[30] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N22
-cycloneive_lcell_comb \spi_slave_instance|q~0 (
-// Equation(s):
-// \spi_slave_instance|q~0_combout = (\spi_slave_instance|q [30] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|q [30]),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~0_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~0 .lut_mask = 16'hC0CC;
-defparam \spi_slave_instance|q~0 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N23
-dffeas \spi_slave_instance|q[31] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~0_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [31]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[31] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[31] .power_up = "low";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N1
-dffeas \spi_slave_instance|qdelayed (
- .clk(!\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(gnd),
- .asdata(\spi_slave_instance|q [31]),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(vcc),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|qdelayed~q ),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|qdelayed .is_wysiwyg = "true";
-defparam \spi_slave_instance|qdelayed .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N0
-cycloneive_lcell_comb \spi_slave_instance|miso~0 (
-// Equation(s):
-// \spi_slave_instance|miso~0_combout = (\spi_slave_instance|qdelayed~q & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|cnt [4]),
- .datac(\spi_slave_instance|qdelayed~q ),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|miso~0_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|miso~0 .lut_mask = 16'hC0F0;
-defparam \spi_slave_instance|miso~0 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: IOIBUF_X16_Y34_N15
-cycloneive_io_ibuf \GPIO_0_PI[10]~input (
- .i(GPIO_0_PI[10]),
- .ibar(gnd),
- .o(\GPIO_0_PI[10]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[10]~input .bus_hold = "false";
-defparam \GPIO_0_PI[10]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X16_Y0_N15
-cycloneive_io_ibuf \CLOCK_50~input (
- .i(CLOCK_50),
- .ibar(gnd),
- .o(\CLOCK_50~input_o ));
-// synopsys translate_off
-defparam \CLOCK_50~input .bus_hold = "false";
-defparam \CLOCK_50~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y14_N1
-cycloneive_io_ibuf \KEY[0]~input (
- .i(KEY[0]),
- .ibar(gnd),
- .o(\KEY[0]~input_o ));
-// synopsys translate_off
-defparam \KEY[0]~input .bus_hold = "false";
-defparam \KEY[0]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y16_N8
-cycloneive_io_ibuf \KEY[1]~input (
- .i(KEY[1]),
- .ibar(gnd),
- .o(\KEY[1]~input_o ));
-// synopsys translate_off
-defparam \KEY[1]~input .bus_hold = "false";
-defparam \KEY[1]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y17_N8
-cycloneive_io_ibuf \GPIO_2_IN[0]~input (
- .i(GPIO_2_IN[0]),
- .ibar(gnd),
- .o(\GPIO_2_IN[0]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2_IN[0]~input .bus_hold = "false";
-defparam \GPIO_2_IN[0]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y17_N1
-cycloneive_io_ibuf \GPIO_2_IN[1]~input (
- .i(GPIO_2_IN[1]),
- .ibar(gnd),
- .o(\GPIO_2_IN[1]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2_IN[1]~input .bus_hold = "false";
-defparam \GPIO_2_IN[1]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X9_Y34_N8
-cycloneive_io_ibuf \GPIO_2_IN[2]~input (
- .i(GPIO_2_IN[2]),
- .ibar(gnd),
- .o(\GPIO_2_IN[2]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2_IN[2]~input .bus_hold = "false";
-defparam \GPIO_2_IN[2]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X14_Y34_N15
-cycloneive_io_ibuf \GPIO_0_PI_IN[0]~input (
- .i(GPIO_0_PI_IN[0]),
- .ibar(gnd),
- .o(\GPIO_0_PI_IN[0]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI_IN[0]~input .bus_hold = "false";
-defparam \GPIO_0_PI_IN[0]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X51_Y34_N1
-cycloneive_io_ibuf \GPIO_0_PI_IN[1]~input (
- .i(GPIO_0_PI_IN[1]),
- .ibar(gnd),
- .o(\GPIO_0_PI_IN[1]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI_IN[1]~input .bus_hold = "false";
-defparam \GPIO_0_PI_IN[1]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X43_Y34_N15
-cycloneive_io_ibuf \GPIO_1_IN[0]~input (
- .i(GPIO_1_IN[0]),
- .ibar(gnd),
- .o(\GPIO_1_IN[0]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1_IN[0]~input .bus_hold = "false";
-defparam \GPIO_1_IN[0]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X34_Y0_N15
-cycloneive_io_ibuf \GPIO_1_IN[1]~input (
- .i(GPIO_1_IN[1]),
- .ibar(gnd),
- .o(\GPIO_1_IN[1]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1_IN[1]~input .bus_hold = "false";
-defparam \GPIO_1_IN[1]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X5_Y0_N22
-cycloneive_io_ibuf \GPIO_2[0]~input (
- .i(GPIO_2[0]),
- .ibar(gnd),
- .o(\GPIO_2[0]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[0]~input .bus_hold = "false";
-defparam \GPIO_2[0]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X51_Y34_N22
-cycloneive_io_ibuf \GPIO_2[1]~input (
- .i(GPIO_2[1]),
- .ibar(gnd),
- .o(\GPIO_2[1]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[1]~input .bus_hold = "false";
-defparam \GPIO_2[1]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y24_N22
-cycloneive_io_ibuf \GPIO_2[2]~input (
- .i(GPIO_2[2]),
- .ibar(gnd),
- .o(\GPIO_2[2]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[2]~input .bus_hold = "false";
-defparam \GPIO_2[2]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y24_N15
-cycloneive_io_ibuf \GPIO_2[3]~input (
- .i(GPIO_2[3]),
- .ibar(gnd),
- .o(\GPIO_2[3]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[3]~input .bus_hold = "false";
-defparam \GPIO_2[3]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X5_Y0_N15
-cycloneive_io_ibuf \GPIO_2[4]~input (
- .i(GPIO_2[4]),
- .ibar(gnd),
- .o(\GPIO_2[4]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[4]~input .bus_hold = "false";
-defparam \GPIO_2[4]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y15_N1
-cycloneive_io_ibuf \GPIO_2[5]~input (
- .i(GPIO_2[5]),
- .ibar(gnd),
- .o(\GPIO_2[5]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[5]~input .bus_hold = "false";
-defparam \GPIO_2[5]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X3_Y34_N1
-cycloneive_io_ibuf \GPIO_2[6]~input (
- .i(GPIO_2[6]),
- .ibar(gnd),
- .o(\GPIO_2[6]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[6]~input .bus_hold = "false";
-defparam \GPIO_2[6]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X1_Y34_N8
-cycloneive_io_ibuf \GPIO_2[7]~input (
- .i(GPIO_2[7]),
- .ibar(gnd),
- .o(\GPIO_2[7]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[7]~input .bus_hold = "false";
-defparam \GPIO_2[7]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X11_Y0_N15
-cycloneive_io_ibuf \GPIO_2[8]~input (
- .i(GPIO_2[8]),
- .ibar(gnd),
- .o(\GPIO_2[8]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[8]~input .bus_hold = "false";
-defparam \GPIO_2[8]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X3_Y0_N1
-cycloneive_io_ibuf \GPIO_2[9]~input (
- .i(GPIO_2[9]),
- .ibar(gnd),
- .o(\GPIO_2[9]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[9]~input .bus_hold = "false";
-defparam \GPIO_2[9]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X43_Y34_N22
-cycloneive_io_ibuf \GPIO_2[10]~input (
- .i(GPIO_2[10]),
- .ibar(gnd),
- .o(\GPIO_2[10]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[10]~input .bus_hold = "false";
-defparam \GPIO_2[10]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X23_Y34_N15
-cycloneive_io_ibuf \GPIO_2[11]~input (
- .i(GPIO_2[11]),
- .ibar(gnd),
- .o(\GPIO_2[11]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[11]~input .bus_hold = "false";
-defparam \GPIO_2[11]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X20_Y34_N8
-cycloneive_io_ibuf \GPIO_2[12]~input (
- .i(GPIO_2[12]),
- .ibar(gnd),
- .o(\GPIO_2[12]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[12]~input .bus_hold = "false";
-defparam \GPIO_2[12]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X34_Y34_N8
-cycloneive_io_ibuf \GPIO_0_PI[0]~input (
- .i(GPIO_0_PI[0]),
- .ibar(gnd),
- .o(\GPIO_0_PI[0]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[0]~input .bus_hold = "false";
-defparam \GPIO_0_PI[0]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y4_N15
-cycloneive_io_ibuf \GPIO_0_PI[1]~input (
- .i(GPIO_0_PI[1]),
- .ibar(gnd),
- .o(\GPIO_0_PI[1]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[1]~input .bus_hold = "false";
-defparam \GPIO_0_PI[1]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y5_N22
-cycloneive_io_ibuf \GPIO_0_PI[2]~input (
- .i(GPIO_0_PI[2]),
- .ibar(gnd),
- .o(\GPIO_0_PI[2]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[2]~input .bus_hold = "false";
-defparam \GPIO_0_PI[2]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X18_Y34_N22
-cycloneive_io_ibuf \GPIO_0_PI[3]~input (
- .i(GPIO_0_PI[3]),
- .ibar(gnd),
- .o(\GPIO_0_PI[3]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[3]~input .bus_hold = "false";
-defparam \GPIO_0_PI[3]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X14_Y0_N15
-cycloneive_io_ibuf \GPIO_0_PI[4]~input (
- .i(GPIO_0_PI[4]),
- .ibar(gnd),
- .o(\GPIO_0_PI[4]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[4]~input .bus_hold = "false";
-defparam \GPIO_0_PI[4]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X14_Y34_N22
-cycloneive_io_ibuf \GPIO_0_PI[5]~input (
- .i(GPIO_0_PI[5]),
- .ibar(gnd),
- .o(\GPIO_0_PI[5]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[5]~input .bus_hold = "false";
-defparam \GPIO_0_PI[5]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y6_N15
-cycloneive_io_ibuf \GPIO_0_PI[6]~input (
- .i(GPIO_0_PI[6]),
- .ibar(gnd),
- .o(\GPIO_0_PI[6]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[6]~input .bus_hold = "false";
-defparam \GPIO_0_PI[6]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X14_Y0_N22
-cycloneive_io_ibuf \GPIO_0_PI[7]~input (
- .i(GPIO_0_PI[7]),
- .ibar(gnd),
- .o(\GPIO_0_PI[7]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[7]~input .bus_hold = "false";
-defparam \GPIO_0_PI[7]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y4_N22
-cycloneive_io_ibuf \GPIO_0_PI[12]~input (
- .i(GPIO_0_PI[12]),
- .ibar(gnd),
- .o(\GPIO_0_PI[12]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[12]~input .bus_hold = "false";
-defparam \GPIO_0_PI[12]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y8_N22
-cycloneive_io_ibuf \GPIO_0_PI[13]~input (
- .i(GPIO_0_PI[13]),
- .ibar(gnd),
- .o(\GPIO_0_PI[13]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[13]~input .bus_hold = "false";
-defparam \GPIO_0_PI[13]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X1_Y34_N1
-cycloneive_io_ibuf \GPIO_0_PI[14]~input (
- .i(GPIO_0_PI[14]),
- .ibar(gnd),
- .o(\GPIO_0_PI[14]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[14]~input .bus_hold = "false";
-defparam \GPIO_0_PI[14]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X34_Y34_N15
-cycloneive_io_ibuf \GPIO_0_PI[15]~input (
- .i(GPIO_0_PI[15]),
- .ibar(gnd),
- .o(\GPIO_0_PI[15]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[15]~input .bus_hold = "false";
-defparam \GPIO_0_PI[15]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X34_Y34_N1
-cycloneive_io_ibuf \GPIO_0_PI[16]~input (
- .i(GPIO_0_PI[16]),
- .ibar(gnd),
- .o(\GPIO_0_PI[16]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[16]~input .bus_hold = "false";
-defparam \GPIO_0_PI[16]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X16_Y34_N8
-cycloneive_io_ibuf \GPIO_0_PI[17]~input (
- .i(GPIO_0_PI[17]),
- .ibar(gnd),
- .o(\GPIO_0_PI[17]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[17]~input .bus_hold = "false";
-defparam \GPIO_0_PI[17]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X1_Y0_N8
-cycloneive_io_ibuf \GPIO_0_PI[18]~input (
- .i(GPIO_0_PI[18]),
- .ibar(gnd),
- .o(\GPIO_0_PI[18]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[18]~input .bus_hold = "false";
-defparam \GPIO_0_PI[18]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X36_Y0_N8
-cycloneive_io_ibuf \GPIO_0_PI[19]~input (
- .i(GPIO_0_PI[19]),
- .ibar(gnd),
- .o(\GPIO_0_PI[19]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[19]~input .bus_hold = "false";
-defparam \GPIO_0_PI[19]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y15_N8
-cycloneive_io_ibuf \GPIO_0_PI[20]~input (
- .i(GPIO_0_PI[20]),
- .ibar(gnd),
- .o(\GPIO_0_PI[20]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[20]~input .bus_hold = "false";
-defparam \GPIO_0_PI[20]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X47_Y34_N22
-cycloneive_io_ibuf \GPIO_0_PI[21]~input (
- .i(GPIO_0_PI[21]),
- .ibar(gnd),
- .o(\GPIO_0_PI[21]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[21]~input .bus_hold = "false";
-defparam \GPIO_0_PI[21]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X14_Y0_N8
-cycloneive_io_ibuf \GPIO_0_PI[22]~input (
- .i(GPIO_0_PI[22]),
- .ibar(gnd),
- .o(\GPIO_0_PI[22]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[22]~input .bus_hold = "false";
-defparam \GPIO_0_PI[22]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X20_Y34_N22
-cycloneive_io_ibuf \GPIO_0_PI[23]~input (
- .i(GPIO_0_PI[23]),
- .ibar(gnd),
- .o(\GPIO_0_PI[23]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[23]~input .bus_hold = "false";
-defparam \GPIO_0_PI[23]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X45_Y34_N1
-cycloneive_io_ibuf \GPIO_0_PI[24]~input (
- .i(GPIO_0_PI[24]),
- .ibar(gnd),
- .o(\GPIO_0_PI[24]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[24]~input .bus_hold = "false";
-defparam \GPIO_0_PI[24]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X40_Y0_N22
-cycloneive_io_ibuf \GPIO_0_PI[25]~input (
- .i(GPIO_0_PI[25]),
- .ibar(gnd),
- .o(\GPIO_0_PI[25]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[25]~input .bus_hold = "false";
-defparam \GPIO_0_PI[25]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X18_Y0_N8
-cycloneive_io_ibuf \GPIO_0_PI[26]~input (
- .i(GPIO_0_PI[26]),
- .ibar(gnd),
- .o(\GPIO_0_PI[26]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[26]~input .bus_hold = "false";
-defparam \GPIO_0_PI[26]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X45_Y34_N15
-cycloneive_io_ibuf \GPIO_0_PI[27]~input (
- .i(GPIO_0_PI[27]),
- .ibar(gnd),
- .o(\GPIO_0_PI[27]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[27]~input .bus_hold = "false";
-defparam \GPIO_0_PI[27]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X38_Y34_N1
-cycloneive_io_ibuf \GPIO_0_PI[28]~input (
- .i(GPIO_0_PI[28]),
- .ibar(gnd),
- .o(\GPIO_0_PI[28]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[28]~input .bus_hold = "false";
-defparam \GPIO_0_PI[28]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X40_Y34_N8
-cycloneive_io_ibuf \GPIO_0_PI[29]~input (
- .i(GPIO_0_PI[29]),
- .ibar(gnd),
- .o(\GPIO_0_PI[29]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[29]~input .bus_hold = "false";
-defparam \GPIO_0_PI[29]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X18_Y34_N1
-cycloneive_io_ibuf \GPIO_0_PI[30]~input (
- .i(GPIO_0_PI[30]),
- .ibar(gnd),
- .o(\GPIO_0_PI[30]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[30]~input .bus_hold = "false";
-defparam \GPIO_0_PI[30]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X23_Y34_N22
-cycloneive_io_ibuf \GPIO_0_PI[32]~input (
- .i(GPIO_0_PI[32]),
- .ibar(gnd),
- .o(\GPIO_0_PI[32]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[32]~input .bus_hold = "false";
-defparam \GPIO_0_PI[32]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y22_N1
-cycloneive_io_ibuf \GPIO_0_PI[33]~input (
- .i(GPIO_0_PI[33]),
- .ibar(gnd),
- .o(\GPIO_0_PI[33]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[33]~input .bus_hold = "false";
-defparam \GPIO_0_PI[33]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X14_Y0_N1
-cycloneive_io_ibuf \GPIO_1[0]~input (
- .i(GPIO_1[0]),
- .ibar(gnd),
- .o(\GPIO_1[0]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[0]~input .bus_hold = "false";
-defparam \GPIO_1[0]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X1_Y0_N22
-cycloneive_io_ibuf \GPIO_1[1]~input (
- .i(GPIO_1[1]),
- .ibar(gnd),
- .o(\GPIO_1[1]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[1]~input .bus_hold = "false";
-defparam \GPIO_1[1]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y20_N22
-cycloneive_io_ibuf \GPIO_1[2]~input (
- .i(GPIO_1[2]),
- .ibar(gnd),
- .o(\GPIO_1[2]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[2]~input .bus_hold = "false";
-defparam \GPIO_1[2]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y23_N1
-cycloneive_io_ibuf \GPIO_1[3]~input (
- .i(GPIO_1[3]),
- .ibar(gnd),
- .o(\GPIO_1[3]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[3]~input .bus_hold = "false";
-defparam \GPIO_1[3]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X7_Y34_N1
-cycloneive_io_ibuf \GPIO_1[4]~input (
- .i(GPIO_1[4]),
- .ibar(gnd),
- .o(\GPIO_1[4]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[4]~input .bus_hold = "false";
-defparam \GPIO_1[4]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y11_N1
-cycloneive_io_ibuf \GPIO_1[5]~input (
- .i(GPIO_1[5]),
- .ibar(gnd),
- .o(\GPIO_1[5]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[5]~input .bus_hold = "false";
-defparam \GPIO_1[5]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X51_Y34_N8
-cycloneive_io_ibuf \GPIO_1[6]~input (
- .i(GPIO_1[6]),
- .ibar(gnd),
- .o(\GPIO_1[6]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[6]~input .bus_hold = "false";
-defparam \GPIO_1[6]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X5_Y0_N8
-cycloneive_io_ibuf \GPIO_1[7]~input (
- .i(GPIO_1[7]),
- .ibar(gnd),
- .o(\GPIO_1[7]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[7]~input .bus_hold = "false";
-defparam \GPIO_1[7]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y22_N8
-cycloneive_io_ibuf \GPIO_1[8]~input (
- .i(GPIO_1[8]),
- .ibar(gnd),
- .o(\GPIO_1[8]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[8]~input .bus_hold = "false";
-defparam \GPIO_1[8]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X34_Y0_N1
-cycloneive_io_ibuf \GPIO_1[9]~input (
- .i(GPIO_1[9]),
- .ibar(gnd),
- .o(\GPIO_1[9]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[9]~input .bus_hold = "false";
-defparam \GPIO_1[9]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y11_N8
-cycloneive_io_ibuf \GPIO_1[10]~input (
- .i(GPIO_1[10]),
- .ibar(gnd),
- .o(\GPIO_1[10]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[10]~input .bus_hold = "false";
-defparam \GPIO_1[10]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X45_Y34_N8
-cycloneive_io_ibuf \GPIO_1[11]~input (
- .i(GPIO_1[11]),
- .ibar(gnd),
- .o(\GPIO_1[11]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[11]~input .bus_hold = "false";
-defparam \GPIO_1[11]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y26_N22
-cycloneive_io_ibuf \GPIO_1[12]~input (
- .i(GPIO_1[12]),
- .ibar(gnd),
- .o(\GPIO_1[12]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[12]~input .bus_hold = "false";
-defparam \GPIO_1[12]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X40_Y0_N15
-cycloneive_io_ibuf \GPIO_1[13]~input (
- .i(GPIO_1[13]),
- .ibar(gnd),
- .o(\GPIO_1[13]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[13]~input .bus_hold = "false";
-defparam \GPIO_1[13]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y12_N1
-cycloneive_io_ibuf \GPIO_1[14]~input (
- .i(GPIO_1[14]),
- .ibar(gnd),
- .o(\GPIO_1[14]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[14]~input .bus_hold = "false";
-defparam \GPIO_1[14]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y30_N1
-cycloneive_io_ibuf \GPIO_1[15]~input (
- .i(GPIO_1[15]),
- .ibar(gnd),
- .o(\GPIO_1[15]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[15]~input .bus_hold = "false";
-defparam \GPIO_1[15]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X25_Y0_N15
-cycloneive_io_ibuf \GPIO_1[16]~input (
- .i(GPIO_1[16]),
- .ibar(gnd),
- .o(\GPIO_1[16]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[16]~input .bus_hold = "false";
-defparam \GPIO_1[16]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X34_Y0_N22
-cycloneive_io_ibuf \GPIO_1[17]~input (
- .i(GPIO_1[17]),
- .ibar(gnd),
- .o(\GPIO_1[17]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[17]~input .bus_hold = "false";
-defparam \GPIO_1[17]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y7_N1
-cycloneive_io_ibuf \GPIO_1[18]~input (
- .i(GPIO_1[18]),
- .ibar(gnd),
- .o(\GPIO_1[18]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[18]~input .bus_hold = "false";
-defparam \GPIO_1[18]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y30_N8
-cycloneive_io_ibuf \GPIO_1[19]~input (
- .i(GPIO_1[19]),
- .ibar(gnd),
- .o(\GPIO_1[19]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[19]~input .bus_hold = "false";
-defparam \GPIO_1[19]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y27_N1
-cycloneive_io_ibuf \GPIO_1[20]~input (
- .i(GPIO_1[20]),
- .ibar(gnd),
- .o(\GPIO_1[20]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[20]~input .bus_hold = "false";
-defparam \GPIO_1[20]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X47_Y0_N22
-cycloneive_io_ibuf \GPIO_1[21]~input (
- .i(GPIO_1[21]),
- .ibar(gnd),
- .o(\GPIO_1[21]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[21]~input .bus_hold = "false";
-defparam \GPIO_1[21]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X11_Y34_N1
-cycloneive_io_ibuf \GPIO_1[22]~input (
- .i(GPIO_1[22]),
- .ibar(gnd),
- .o(\GPIO_1[22]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[22]~input .bus_hold = "false";
-defparam \GPIO_1[22]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X20_Y0_N8
-cycloneive_io_ibuf \GPIO_1[23]~input (
- .i(GPIO_1[23]),
- .ibar(gnd),
- .o(\GPIO_1[23]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[23]~input .bus_hold = "false";
-defparam \GPIO_1[23]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X5_Y0_N1
-cycloneive_io_ibuf \GPIO_1[24]~input (
- .i(GPIO_1[24]),
- .ibar(gnd),
- .o(\GPIO_1[24]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[24]~input .bus_hold = "false";
-defparam \GPIO_1[24]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y21_N22
-cycloneive_io_ibuf \GPIO_1[25]~input (
- .i(GPIO_1[25]),
- .ibar(gnd),
- .o(\GPIO_1[25]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[25]~input .bus_hold = "false";
-defparam \GPIO_1[25]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X1_Y0_N15
-cycloneive_io_ibuf \GPIO_1[26]~input (
- .i(GPIO_1[26]),
- .ibar(gnd),
- .o(\GPIO_1[26]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[26]~input .bus_hold = "false";
-defparam \GPIO_1[26]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X7_Y0_N8
-cycloneive_io_ibuf \GPIO_1[27]~input (
- .i(GPIO_1[27]),
- .ibar(gnd),
- .o(\GPIO_1[27]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[27]~input .bus_hold = "false";
-defparam \GPIO_1[27]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y23_N22
-cycloneive_io_ibuf \GPIO_1[28]~input (
- .i(GPIO_1[28]),
- .ibar(gnd),
- .o(\GPIO_1[28]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[28]~input .bus_hold = "false";
-defparam \GPIO_1[28]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y14_N8
-cycloneive_io_ibuf \GPIO_1[29]~input (
- .i(GPIO_1[29]),
- .ibar(gnd),
- .o(\GPIO_1[29]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[29]~input .bus_hold = "false";
-defparam \GPIO_1[29]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X45_Y0_N22
-cycloneive_io_ibuf \GPIO_1[30]~input (
- .i(GPIO_1[30]),
- .ibar(gnd),
- .o(\GPIO_1[30]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[30]~input .bus_hold = "false";
-defparam \GPIO_1[30]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X49_Y0_N1
-cycloneive_io_ibuf \GPIO_1[31]~input (
- .i(GPIO_1[31]),
- .ibar(gnd),
- .o(\GPIO_1[31]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[31]~input .bus_hold = "false";
-defparam \GPIO_1[31]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X31_Y34_N1
-cycloneive_io_ibuf \GPIO_1[32]~input (
- .i(GPIO_1[32]),
- .ibar(gnd),
- .o(\GPIO_1[32]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[32]~input .bus_hold = "false";
-defparam \GPIO_1[32]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y6_N15
-cycloneive_io_ibuf \GPIO_1[33]~input (
- .i(GPIO_1[33]),
- .ibar(gnd),
- .o(\GPIO_1[33]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[33]~input .bus_hold = "false";
-defparam \GPIO_1[33]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X16_Y34_N1
-cycloneive_io_ibuf \GPIO_0_PI[11]~input (
- .i(GPIO_0_PI[11]),
- .ibar(gnd),
- .o(\GPIO_0_PI[11]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[11]~input .bus_hold = "false";
-defparam \GPIO_0_PI[11]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-assign LED[0] = \LED[0]~output_o ;
-
-assign LED[1] = \LED[1]~output_o ;
-
-assign LED[2] = \LED[2]~output_o ;
-
-assign LED[3] = \LED[3]~output_o ;
-
-assign LED[4] = \LED[4]~output_o ;
-
-assign LED[5] = \LED[5]~output_o ;
-
-assign LED[6] = \LED[6]~output_o ;
-
-assign LED[7] = \LED[7]~output_o ;
-
-assign GPIO_2[0] = \GPIO_2[0]~output_o ;
-
-assign GPIO_2[1] = \GPIO_2[1]~output_o ;
-
-assign GPIO_2[2] = \GPIO_2[2]~output_o ;
-
-assign GPIO_2[3] = \GPIO_2[3]~output_o ;
-
-assign GPIO_2[4] = \GPIO_2[4]~output_o ;
-
-assign GPIO_2[5] = \GPIO_2[5]~output_o ;
-
-assign GPIO_2[6] = \GPIO_2[6]~output_o ;
-
-assign GPIO_2[7] = \GPIO_2[7]~output_o ;
-
-assign GPIO_2[8] = \GPIO_2[8]~output_o ;
-
-assign GPIO_2[9] = \GPIO_2[9]~output_o ;
-
-assign GPIO_2[10] = \GPIO_2[10]~output_o ;
-
-assign GPIO_2[11] = \GPIO_2[11]~output_o ;
-
-assign GPIO_2[12] = \GPIO_2[12]~output_o ;
-
-assign GPIO_0_PI[0] = \GPIO_0_PI[0]~output_o ;
-
-assign GPIO_0_PI[1] = \GPIO_0_PI[1]~output_o ;
-
-assign GPIO_0_PI[2] = \GPIO_0_PI[2]~output_o ;
-
-assign GPIO_0_PI[3] = \GPIO_0_PI[3]~output_o ;
-
-assign GPIO_0_PI[4] = \GPIO_0_PI[4]~output_o ;
-
-assign GPIO_0_PI[5] = \GPIO_0_PI[5]~output_o ;
-
-assign GPIO_0_PI[6] = \GPIO_0_PI[6]~output_o ;
-
-assign GPIO_0_PI[7] = \GPIO_0_PI[7]~output_o ;
-
-assign GPIO_0_PI[12] = \GPIO_0_PI[12]~output_o ;
-
-assign GPIO_0_PI[13] = \GPIO_0_PI[13]~output_o ;
-
-assign GPIO_0_PI[14] = \GPIO_0_PI[14]~output_o ;
-
-assign GPIO_0_PI[15] = \GPIO_0_PI[15]~output_o ;
-
-assign GPIO_0_PI[16] = \GPIO_0_PI[16]~output_o ;
-
-assign GPIO_0_PI[17] = \GPIO_0_PI[17]~output_o ;
-
-assign GPIO_0_PI[18] = \GPIO_0_PI[18]~output_o ;
-
-assign GPIO_0_PI[19] = \GPIO_0_PI[19]~output_o ;
-
-assign GPIO_0_PI[20] = \GPIO_0_PI[20]~output_o ;
-
-assign GPIO_0_PI[21] = \GPIO_0_PI[21]~output_o ;
-
-assign GPIO_0_PI[22] = \GPIO_0_PI[22]~output_o ;
-
-assign GPIO_0_PI[23] = \GPIO_0_PI[23]~output_o ;
-
-assign GPIO_0_PI[24] = \GPIO_0_PI[24]~output_o ;
-
-assign GPIO_0_PI[25] = \GPIO_0_PI[25]~output_o ;
-
-assign GPIO_0_PI[26] = \GPIO_0_PI[26]~output_o ;
-
-assign GPIO_0_PI[27] = \GPIO_0_PI[27]~output_o ;
-
-assign GPIO_0_PI[28] = \GPIO_0_PI[28]~output_o ;
-
-assign GPIO_0_PI[29] = \GPIO_0_PI[29]~output_o ;
-
-assign GPIO_0_PI[30] = \GPIO_0_PI[30]~output_o ;
-
-assign GPIO_0_PI[32] = \GPIO_0_PI[32]~output_o ;
-
-assign GPIO_0_PI[33] = \GPIO_0_PI[33]~output_o ;
-
-assign GPIO_1[0] = \GPIO_1[0]~output_o ;
-
-assign GPIO_1[1] = \GPIO_1[1]~output_o ;
-
-assign GPIO_1[2] = \GPIO_1[2]~output_o ;
-
-assign GPIO_1[3] = \GPIO_1[3]~output_o ;
-
-assign GPIO_1[4] = \GPIO_1[4]~output_o ;
-
-assign GPIO_1[5] = \GPIO_1[5]~output_o ;
-
-assign GPIO_1[6] = \GPIO_1[6]~output_o ;
-
-assign GPIO_1[7] = \GPIO_1[7]~output_o ;
-
-assign GPIO_1[8] = \GPIO_1[8]~output_o ;
-
-assign GPIO_1[9] = \GPIO_1[9]~output_o ;
-
-assign GPIO_1[10] = \GPIO_1[10]~output_o ;
-
-assign GPIO_1[11] = \GPIO_1[11]~output_o ;
-
-assign GPIO_1[12] = \GPIO_1[12]~output_o ;
-
-assign GPIO_1[13] = \GPIO_1[13]~output_o ;
-
-assign GPIO_1[14] = \GPIO_1[14]~output_o ;
-
-assign GPIO_1[15] = \GPIO_1[15]~output_o ;
-
-assign GPIO_1[16] = \GPIO_1[16]~output_o ;
-
-assign GPIO_1[17] = \GPIO_1[17]~output_o ;
-
-assign GPIO_1[18] = \GPIO_1[18]~output_o ;
-
-assign GPIO_1[19] = \GPIO_1[19]~output_o ;
-
-assign GPIO_1[20] = \GPIO_1[20]~output_o ;
-
-assign GPIO_1[21] = \GPIO_1[21]~output_o ;
-
-assign GPIO_1[22] = \GPIO_1[22]~output_o ;
-
-assign GPIO_1[23] = \GPIO_1[23]~output_o ;
-
-assign GPIO_1[24] = \GPIO_1[24]~output_o ;
-
-assign GPIO_1[25] = \GPIO_1[25]~output_o ;
-
-assign GPIO_1[26] = \GPIO_1[26]~output_o ;
-
-assign GPIO_1[27] = \GPIO_1[27]~output_o ;
-
-assign GPIO_1[28] = \GPIO_1[28]~output_o ;
-
-assign GPIO_1[29] = \GPIO_1[29]~output_o ;
-
-assign GPIO_1[30] = \GPIO_1[30]~output_o ;
-
-assign GPIO_1[31] = \GPIO_1[31]~output_o ;
-
-assign GPIO_1[32] = \GPIO_1[32]~output_o ;
-
-assign GPIO_1[33] = \GPIO_1[33]~output_o ;
-
-assign GPIO_0_PI[8] = \GPIO_0_PI[8]~output_o ;
-
-assign GPIO_0_PI[9] = \GPIO_0_PI[9]~output_o ;
-
-assign GPIO_0_PI[10] = \GPIO_0_PI[10]~output_o ;
-
-assign GPIO_0_PI[11] = \GPIO_0_PI[11]~output_o ;
-
-assign GPIO_0_PI[31] = \GPIO_0_PI[31]~output_o ;
-
-endmodule
-
-module hard_block (
-
- devpor,
- devclrn,
- devoe);
-
-// Design Ports Information
-// ~ALTERA_ASDO_DATA1~ => Location: PIN_C1, I/O Standard: 2.5 V, Current Strength: Default
-// ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_D2, I/O Standard: 2.5 V, Current Strength: Default
-// ~ALTERA_DCLK~ => Location: PIN_H1, I/O Standard: 2.5 V, Current Strength: Default
-// ~ALTERA_DATA0~ => Location: PIN_H2, I/O Standard: 2.5 V, Current Strength: Default
-// ~ALTERA_nCEO~ => Location: PIN_F16, I/O Standard: 2.5 V, Current Strength: 8mA
-
-input devpor;
-input devclrn;
-input devoe;
-
-wire gnd;
-wire vcc;
-wire unknown;
-
-assign gnd = 1'b0;
-assign vcc = 1'b1;
-assign unknown = 1'bx;
-
-wire \~ALTERA_ASDO_DATA1~~padout ;
-wire \~ALTERA_FLASH_nCE_nCSO~~padout ;
-wire \~ALTERA_DATA0~~padout ;
-wire \~ALTERA_ASDO_DATA1~~ibuf_o ;
-wire \~ALTERA_FLASH_nCE_nCSO~~ibuf_o ;
-wire \~ALTERA_DATA0~~ibuf_o ;
-
-
-endmodule
diff --git a/SPI/simulation/modelsim/SPI_test_6_1200mv_85c_v_slow.sdo b/SPI/simulation/modelsim/SPI_test_6_1200mv_85c_v_slow.sdo
deleted file mode 100644
index 1d05890a89b84c463240dcc0e93718077dae1a55..0000000000000000000000000000000000000000
--- a/SPI/simulation/modelsim/SPI_test_6_1200mv_85c_v_slow.sdo
+++ /dev/null
@@ -1,1172 +0,0 @@
-// Copyright (C) 2018 Intel Corporation. All rights reserved.
-// Your use of Intel Corporation's design tools, logic functions
-// and other software and tools, and its AMPP partner logic
-// functions, and any output files from any of the foregoing
-// (including device programming or simulation files), and any
-// associated documentation or information are expressly subject
-// to the terms and conditions of the Intel Program License
-// Subscription Agreement, the Intel Quartus Prime License Agreement,
-// the Intel FPGA IP License Agreement, or other applicable license
-// agreement, including, without limitation, that your use is for
-// the sole purpose of programming logic devices manufactured by
-// Intel and sold by Intel or its authorized distributors. Please
-// refer to the applicable agreement for further details.
-
-
-//
-// Device: Altera EP4CE22F17C6 Package FBGA256
-//
-
-//
-// This file contains Slow Corner delays for the design using part EP4CE22F17C6,
-// with speed grade 6, core voltage 1.2VmV, and temperature 85 Celsius
-//
-
-//
-// This SDF file should be used for ModelSim-Altera (SystemVerilog) only
-//
-
-(DELAYFILE
- (SDFVERSION "2.1")
- (DESIGN "MyDE0_Nano")
- (DATE "11/16/2022 16:51:48")
- (VENDOR "Altera")
- (PROGRAM "Quartus Prime")
- (VERSION "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition")
- (DIVIDER .)
- (TIMESCALE 1 ps)
-
- (CELL
- (CELLTYPE "cycloneive_io_obuf")
- (INSTANCE GPIO_0_PI\[11\]\~output)
- (DELAY
- (ABSOLUTE
- (PORT i (699:699:699) (676:676:676))
- (PORT oe (3075:3075:3075) (2835:2835:2835))
- (IOPATH i o (2593:2593:2593) (2562:2562:2562))
- (IOPATH oe o (2615:2615:2615) (2536:2536:2536))
- )
- )
- )
- (CELL
- (CELLTYPE "cycloneive_io_ibuf")
- (INSTANCE GPIO_0_PI\[8\]\~input)
- (DELAY
- (ABSOLUTE
- (IOPATH i o (516:516:516) (681:681:681))
- )
- )
- )
- (CELL
- (CELLTYPE "cycloneive_clkctrl")
- (INSTANCE GPIO_0_PI\[8\]\~inputclkctrl)
- (DELAY
- (ABSOLUTE
- (IOPATH inclk outclk (206:206:206) (195:195:195))
- )
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|cnt\[0\]\~12)
- (DELAY
- (ABSOLUTE
- (IOPATH datac combout (353:353:353) (369:369:369))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|cnt\[0\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1549:1549:1549) (1551:1551:1551))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|cnt\[1\]\~4)
- (DELAY
- (ABSOLUTE
- (PORT dataa (274:274:274) (364:364:364))
- (PORT datab (270:270:270) (355:355:355))
- (IOPATH dataa combout (339:339:339) (367:367:367))
- (IOPATH dataa cout (436:436:436) (315:315:315))
- (IOPATH datab combout (344:344:344) (369:369:369))
- (IOPATH datab cout (446:446:446) (318:318:318))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|cnt\[1\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1549:1549:1549) (1551:1551:1551))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|cnt\[2\]\~6)
- (DELAY
- (ABSOLUTE
- (PORT datab (409:409:409) (483:483:483))
- (IOPATH datab combout (365:365:365) (373:373:373))
- (IOPATH datab cout (446:446:446) (318:318:318))
- (IOPATH datad combout (130:130:130) (120:120:120))
- (IOPATH cin combout (455:455:455) (437:437:437))
- (IOPATH cin cout (58:58:58) (58:58:58))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|cnt\[2\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1549:1549:1549) (1551:1551:1551))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|cnt\[3\]\~8)
- (DELAY
- (ABSOLUTE
- (PORT dataa (272:272:272) (361:361:361))
- (IOPATH dataa combout (354:354:354) (367:367:367))
- (IOPATH dataa cout (436:436:436) (315:315:315))
- (IOPATH datad combout (130:130:130) (120:120:120))
- (IOPATH cin combout (455:455:455) (437:437:437))
- (IOPATH cin cout (58:58:58) (58:58:58))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|cnt\[3\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1549:1549:1549) (1551:1551:1551))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|cnt\[4\]\~10)
- (DELAY
- (ABSOLUTE
- (PORT datab (367:367:367) (478:478:478))
- (IOPATH datab combout (365:365:365) (373:373:373))
- (IOPATH cin combout (455:455:455) (437:437:437))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|cnt\[4\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1549:1549:1549) (1551:1551:1551))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_io_ibuf")
- (INSTANCE GPIO_0_PI\[31\]\~input)
- (DELAY
- (ABSOLUTE
- (IOPATH i o (514:514:514) (679:679:679))
- )
- )
- )
- (CELL
- (CELLTYPE "cycloneive_io_ibuf")
- (INSTANCE GPIO_0_PI\[9\]\~input)
- (DELAY
- (ABSOLUTE
- (IOPATH i o (514:514:514) (679:679:679))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[0\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1543:1543:1543) (1559:1559:1559))
- (PORT asdata (3670:3670:3670) (3988:3988:3988))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD asdata (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|Equal0\~0)
- (DELAY
- (ABSOLUTE
- (PORT dataa (273:273:273) (364:364:364))
- (PORT datab (272:272:272) (357:357:357))
- (PORT datac (237:237:237) (313:313:313))
- (PORT datad (246:246:246) (319:319:319))
- (IOPATH dataa combout (350:350:350) (366:366:366))
- (IOPATH datab combout (350:350:350) (368:368:368))
- (IOPATH datac combout (241:241:241) (241:241:241))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~31)
- (DELAY
- (ABSOLUTE
- (PORT dataa (491:491:491) (582:582:582))
- (PORT datab (3612:3612:3612) (3959:3959:3959))
- (PORT datac (218:218:218) (295:295:295))
- (PORT datad (406:406:406) (430:430:430))
- (IOPATH dataa combout (325:325:325) (320:320:320))
- (IOPATH datab combout (306:306:306) (308:308:308))
- (IOPATH datac combout (243:243:243) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[1\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1543:1543:1543) (1559:1559:1559))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~30)
- (DELAY
- (ABSOLUTE
- (PORT dataa (492:492:492) (583:583:583))
- (PORT datac (217:217:217) (293:293:293))
- (PORT datad (407:407:407) (429:429:429))
- (IOPATH dataa combout (304:304:304) (307:307:307))
- (IOPATH datac combout (243:243:243) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[2\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1543:1543:1543) (1559:1559:1559))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~29)
- (DELAY
- (ABSOLUTE
- (PORT dataa (494:494:494) (582:582:582))
- (PORT datab (244:244:244) (327:327:327))
- (PORT datad (410:410:410) (429:429:429))
- (IOPATH dataa combout (300:300:300) (308:308:308))
- (IOPATH datab combout (355:355:355) (369:369:369))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[3\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1543:1543:1543) (1559:1559:1559))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~28)
- (DELAY
- (ABSOLUTE
- (PORT dataa (482:482:482) (574:574:574))
- (PORT datac (219:219:219) (296:296:296))
- (PORT datad (410:410:410) (430:430:430))
- (IOPATH dataa combout (304:304:304) (307:307:307))
- (IOPATH datac combout (243:243:243) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[4\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1543:1543:1543) (1559:1559:1559))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~27)
- (DELAY
- (ABSOLUTE
- (PORT dataa (492:492:492) (581:581:581))
- (PORT datac (218:218:218) (296:296:296))
- (PORT datad (405:405:405) (428:428:428))
- (IOPATH dataa combout (304:304:304) (307:307:307))
- (IOPATH datac combout (243:243:243) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[5\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1543:1543:1543) (1559:1559:1559))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~26)
- (DELAY
- (ABSOLUTE
- (PORT dataa (493:493:493) (582:582:582))
- (PORT datab (245:245:245) (327:327:327))
- (PORT datad (409:409:409) (428:428:428))
- (IOPATH dataa combout (300:300:300) (308:308:308))
- (IOPATH datab combout (355:355:355) (369:369:369))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[6\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1543:1543:1543) (1559:1559:1559))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~25)
- (DELAY
- (ABSOLUTE
- (PORT dataa (483:483:483) (576:576:576))
- (PORT datab (246:246:246) (330:330:330))
- (PORT datad (410:410:410) (433:433:433))
- (IOPATH dataa combout (300:300:300) (308:308:308))
- (IOPATH datab combout (355:355:355) (369:369:369))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[7\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1543:1543:1543) (1559:1559:1559))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~24)
- (DELAY
- (ABSOLUTE
- (PORT datab (369:369:369) (483:483:483))
- (PORT datac (361:361:361) (431:431:431))
- (PORT datad (281:281:281) (328:328:328))
- (IOPATH datab combout (306:306:306) (308:308:308))
- (IOPATH datac combout (243:243:243) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[8\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1542:1542:1542) (1558:1558:1558))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~23)
- (DELAY
- (ABSOLUTE
- (PORT datab (246:246:246) (329:329:329))
- (PORT datac (338:338:338) (447:447:447))
- (PORT datad (279:279:279) (326:326:326))
- (IOPATH datab combout (355:355:355) (369:369:369))
- (IOPATH datac combout (241:241:241) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[9\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1542:1542:1542) (1558:1558:1558))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~22)
- (DELAY
- (ABSOLUTE
- (PORT datab (244:244:244) (326:326:326))
- (PORT datac (338:338:338) (448:448:448))
- (PORT datad (280:280:280) (326:326:326))
- (IOPATH datab combout (355:355:355) (369:369:369))
- (IOPATH datac combout (241:241:241) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[10\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1542:1542:1542) (1558:1558:1558))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~21)
- (DELAY
- (ABSOLUTE
- (PORT datab (368:368:368) (485:485:485))
- (PORT datac (216:216:216) (293:293:293))
- (PORT datad (280:280:280) (325:325:325))
- (IOPATH datab combout (306:306:306) (308:308:308))
- (IOPATH datac combout (243:243:243) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[11\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1542:1542:1542) (1558:1558:1558))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~20)
- (DELAY
- (ABSOLUTE
- (PORT datab (244:244:244) (326:326:326))
- (PORT datac (337:337:337) (446:446:446))
- (PORT datad (279:279:279) (325:325:325))
- (IOPATH datab combout (355:355:355) (369:369:369))
- (IOPATH datac combout (241:241:241) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[12\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1542:1542:1542) (1558:1558:1558))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~19)
- (DELAY
- (ABSOLUTE
- (PORT dataa (493:493:493) (582:582:582))
- (PORT datac (382:382:382) (442:442:442))
- (PORT datad (405:405:405) (429:429:429))
- (IOPATH dataa combout (304:304:304) (307:307:307))
- (IOPATH datac combout (243:243:243) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[13\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1543:1543:1543) (1559:1559:1559))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~18)
- (DELAY
- (ABSOLUTE
- (PORT datab (366:366:366) (485:485:485))
- (PORT datac (360:360:360) (431:431:431))
- (PORT datad (281:281:281) (331:331:331))
- (IOPATH datab combout (306:306:306) (308:308:308))
- (IOPATH datac combout (243:243:243) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[14\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1542:1542:1542) (1558:1558:1558))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~17)
- (DELAY
- (ABSOLUTE
- (PORT datab (246:246:246) (329:329:329))
- (PORT datac (332:332:332) (442:442:442))
- (PORT datad (281:281:281) (331:331:331))
- (IOPATH datab combout (355:355:355) (369:369:369))
- (IOPATH datac combout (241:241:241) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[15\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1542:1542:1542) (1558:1558:1558))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~16)
- (DELAY
- (ABSOLUTE
- (PORT datab (372:372:372) (486:486:486))
- (PORT datac (364:364:364) (424:424:424))
- (PORT datad (281:281:281) (328:328:328))
- (IOPATH datab combout (306:306:306) (308:308:308))
- (IOPATH datac combout (243:243:243) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[16\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1542:1542:1542) (1558:1558:1558))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~15)
- (DELAY
- (ABSOLUTE
- (PORT datab (245:245:245) (327:327:327))
- (PORT datac (335:335:335) (444:444:444))
- (PORT datad (281:281:281) (327:327:327))
- (IOPATH datab combout (355:355:355) (369:369:369))
- (IOPATH datac combout (241:241:241) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[17\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1542:1542:1542) (1558:1558:1558))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~14)
- (DELAY
- (ABSOLUTE
- (PORT datab (360:360:360) (475:475:475))
- (PORT datac (219:219:219) (296:296:296))
- (PORT datad (280:280:280) (328:328:328))
- (IOPATH datab combout (306:306:306) (308:308:308))
- (IOPATH datac combout (243:243:243) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[18\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1542:1542:1542) (1558:1558:1558))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~13)
- (DELAY
- (ABSOLUTE
- (PORT datab (570:570:570) (668:668:668))
- (PORT datac (396:396:396) (461:461:461))
- (PORT datad (464:464:464) (508:508:508))
- (IOPATH datab combout (306:306:306) (308:308:308))
- (IOPATH datac combout (243:243:243) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[19\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1541:1541:1541) (1557:1557:1557))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~12)
- (DELAY
- (ABSOLUTE
- (PORT datab (246:246:246) (329:329:329))
- (PORT datac (517:517:517) (627:627:627))
- (PORT datad (465:465:465) (514:514:514))
- (IOPATH datab combout (355:355:355) (369:369:369))
- (IOPATH datac combout (241:241:241) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[20\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1541:1541:1541) (1557:1557:1557))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~10)
- (DELAY
- (ABSOLUTE
- (PORT dataa (412:412:412) (491:491:491))
- (PORT datac (519:519:519) (627:627:627))
- (PORT datad (383:383:383) (444:444:444))
- (IOPATH dataa combout (354:354:354) (367:367:367))
- (IOPATH datac combout (243:243:243) (241:241:241))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~11)
- (DELAY
- (ABSOLUTE
- (PORT dataa (460:460:460) (530:530:530))
- (PORT datab (246:246:246) (330:330:330))
- (PORT datac (412:412:412) (477:477:477))
- (PORT datad (176:176:176) (202:202:202))
- (IOPATH dataa combout (339:339:339) (367:367:367))
- (IOPATH datab combout (344:344:344) (369:369:369))
- (IOPATH datac combout (243:243:243) (241:241:241))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[21\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1541:1541:1541) (1557:1557:1557))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~9)
- (DELAY
- (ABSOLUTE
- (PORT dataa (248:248:248) (336:336:336))
- (PORT datac (522:522:522) (627:627:627))
- (PORT datad (464:464:464) (513:513:513))
- (IOPATH dataa combout (354:354:354) (367:367:367))
- (IOPATH datac combout (241:241:241) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[22\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1541:1541:1541) (1557:1557:1557))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~8)
- (DELAY
- (ABSOLUTE
- (PORT dataa (246:246:246) (333:333:333))
- (PORT datac (519:519:519) (624:624:624))
- (PORT datad (465:465:465) (515:515:515))
- (IOPATH dataa combout (354:354:354) (367:367:367))
- (IOPATH datac combout (241:241:241) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[23\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1541:1541:1541) (1557:1557:1557))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~7)
- (DELAY
- (ABSOLUTE
- (PORT dataa (246:246:246) (333:333:333))
- (PORT datac (520:520:520) (621:621:621))
- (PORT datad (467:467:467) (515:515:515))
- (IOPATH dataa combout (354:354:354) (367:367:367))
- (IOPATH datac combout (241:241:241) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[24\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1541:1541:1541) (1557:1557:1557))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~6)
- (DELAY
- (ABSOLUTE
- (PORT datab (247:247:247) (331:331:331))
- (PORT datac (532:532:532) (632:632:632))
- (PORT datad (465:465:465) (508:508:508))
- (IOPATH datab combout (355:355:355) (369:369:369))
- (IOPATH datac combout (241:241:241) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[25\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1541:1541:1541) (1557:1557:1557))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~5)
- (DELAY
- (ABSOLUTE
- (PORT dataa (246:246:246) (335:335:335))
- (PORT datac (533:533:533) (633:633:633))
- (PORT datad (460:460:460) (510:510:510))
- (IOPATH dataa combout (354:354:354) (367:367:367))
- (IOPATH datac combout (241:241:241) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[26\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1541:1541:1541) (1557:1557:1557))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~4)
- (DELAY
- (ABSOLUTE
- (PORT datab (245:245:245) (329:329:329))
- (PORT datac (524:524:524) (631:631:631))
- (PORT datad (464:464:464) (513:513:513))
- (IOPATH datab combout (355:355:355) (369:369:369))
- (IOPATH datac combout (241:241:241) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[27\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1541:1541:1541) (1557:1557:1557))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~3)
- (DELAY
- (ABSOLUTE
- (PORT datab (245:245:245) (329:329:329))
- (PORT datac (531:531:531) (632:632:632))
- (PORT datad (462:462:462) (514:514:514))
- (IOPATH datab combout (355:355:355) (369:369:369))
- (IOPATH datac combout (241:241:241) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[28\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1541:1541:1541) (1557:1557:1557))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~2)
- (DELAY
- (ABSOLUTE
- (PORT datab (245:245:245) (329:329:329))
- (PORT datac (532:532:532) (632:632:632))
- (PORT datad (459:459:459) (509:509:509))
- (IOPATH datab combout (355:355:355) (369:369:369))
- (IOPATH datac combout (241:241:241) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[29\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1541:1541:1541) (1557:1557:1557))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~1)
- (DELAY
- (ABSOLUTE
- (PORT datab (245:245:245) (326:326:326))
- (PORT datac (529:529:529) (635:635:635))
- (PORT datad (462:462:462) (500:500:500))
- (IOPATH datab combout (355:355:355) (369:369:369))
- (IOPATH datac combout (241:241:241) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[30\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1541:1541:1541) (1557:1557:1557))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~0)
- (DELAY
- (ABSOLUTE
- (PORT datab (245:245:245) (327:327:327))
- (PORT datac (528:528:528) (635:635:635))
- (PORT datad (461:461:461) (503:503:503))
- (IOPATH datab combout (355:355:355) (369:369:369))
- (IOPATH datac combout (241:241:241) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[31\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1541:1541:1541) (1557:1557:1557))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|qdelayed)
- (DELAY
- (ABSOLUTE
- (PORT clk (1548:1548:1548) (1550:1550:1550))
- (PORT asdata (561:561:561) (635:635:635))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD asdata (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|miso\~0)
- (DELAY
- (ABSOLUTE
- (PORT datab (558:558:558) (655:655:655))
- (PORT datad (465:465:465) (501:501:501))
- (IOPATH datab combout (306:306:306) (308:308:308))
- (IOPATH datac combout (353:353:353) (369:369:369))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "cycloneive_io_ibuf")
- (INSTANCE GPIO_0_PI\[10\]\~input)
- (DELAY
- (ABSOLUTE
- (IOPATH i o (514:514:514) (679:679:679))
- )
- )
- )
-)
diff --git a/SPI/simulation/modelsim/SPI_test_min_1200mv_0c_fast.svo b/SPI/simulation/modelsim/SPI_test_min_1200mv_0c_fast.svo
deleted file mode 100644
index b3851c92df0463189740a1f100fbd18fb161e054..0000000000000000000000000000000000000000
--- a/SPI/simulation/modelsim/SPI_test_min_1200mv_0c_fast.svo
+++ /dev/null
@@ -1,4083 +0,0 @@
-// Copyright (C) 2018 Intel Corporation. All rights reserved.
-// Your use of Intel Corporation's design tools, logic functions
-// and other software and tools, and its AMPP partner logic
-// functions, and any output files from any of the foregoing
-// (including device programming or simulation files), and any
-// associated documentation or information are expressly subject
-// to the terms and conditions of the Intel Program License
-// Subscription Agreement, the Intel Quartus Prime License Agreement,
-// the Intel FPGA IP License Agreement, or other applicable license
-// agreement, including, without limitation, that your use is for
-// the sole purpose of programming logic devices manufactured by
-// Intel and sold by Intel or its authorized distributors. Please
-// refer to the applicable agreement for further details.
-
-// VENDOR "Altera"
-// PROGRAM "Quartus Prime"
-// VERSION "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition"
-
-// DATE "11/16/2022 16:51:48"
-
-//
-// Device: Altera EP4CE22F17C6 Package FBGA256
-//
-
-//
-// This Verilog file should be used for ModelSim-Altera (SystemVerilog) only
-//
-
-`timescale 1 ps/ 1 ps
-
-module MyDE0_Nano (
- CLOCK_50,
- LED,
- KEY,
- GPIO_2,
- GPIO_2_IN,
- GPIO_0_PI,
- GPIO_0_PI_IN,
- GPIO_1,
- GPIO_1_IN);
-input CLOCK_50;
-output [7:0] LED;
-input [1:0] KEY;
-output [12:0] GPIO_2;
-input [2:0] GPIO_2_IN;
-output [33:0] GPIO_0_PI;
-input [1:0] GPIO_0_PI_IN;
-output [33:0] GPIO_1;
-input [1:0] GPIO_1_IN;
-
-// Design Ports Information
-// CLOCK_50 => Location: PIN_R7, I/O Standard: 2.5 V, Current Strength: Default
-// LED[0] => Location: PIN_A15, I/O Standard: 2.5 V, Current Strength: Default
-// LED[1] => Location: PIN_A13, I/O Standard: 2.5 V, Current Strength: Default
-// LED[2] => Location: PIN_B13, I/O Standard: 2.5 V, Current Strength: Default
-// LED[3] => Location: PIN_A11, I/O Standard: 2.5 V, Current Strength: Default
-// LED[4] => Location: PIN_D1, I/O Standard: 2.5 V, Current Strength: Default
-// LED[5] => Location: PIN_F3, I/O Standard: 2.5 V, Current Strength: Default
-// LED[6] => Location: PIN_B1, I/O Standard: 2.5 V, Current Strength: Default
-// LED[7] => Location: PIN_L3, I/O Standard: 2.5 V, Current Strength: Default
-// KEY[0] => Location: PIN_J15, I/O Standard: 2.5 V, Current Strength: Default
-// KEY[1] => Location: PIN_E1, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2_IN[0] => Location: PIN_E16, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2_IN[1] => Location: PIN_E15, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2_IN[2] => Location: PIN_D6, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI_IN[0] => Location: PIN_E6, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI_IN[1] => Location: PIN_C14, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1_IN[0] => Location: PIN_A12, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1_IN[1] => Location: PIN_T10, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[0] => Location: PIN_R4, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[1] => Location: PIN_D12, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[2] => Location: PIN_F2, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[3] => Location: PIN_G5, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[4] => Location: PIN_T4, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[5] => Location: PIN_J2, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[6] => Location: PIN_B3, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[7] => Location: PIN_D3, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[8] => Location: PIN_M7, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[9] => Location: PIN_T2, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[10] => Location: PIN_B12, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[11] => Location: PIN_C8, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_2[12] => Location: PIN_E8, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[0] => Location: PIN_A10, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[1] => Location: PIN_P2, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[2] => Location: PIN_R1, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[3] => Location: PIN_C6, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[4] => Location: PIN_T5, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[5] => Location: PIN_A5, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[6] => Location: PIN_P15, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[7] => Location: PIN_R5, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[12] => Location: PIN_P1, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[13] => Location: PIN_R16, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[14] => Location: PIN_C3, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[15] => Location: PIN_B10, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[16] => Location: PIN_F9, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[17] => Location: PIN_B6, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[18] => Location: PIN_R3, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[19] => Location: PIN_T12, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[20] => Location: PIN_J1, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[21] => Location: PIN_A14, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[22] => Location: PIN_R6, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[23] => Location: PIN_A7, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[24] => Location: PIN_B14, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[25] => Location: PIN_R13, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[26] => Location: PIN_L8, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[27] => Location: PIN_E10, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[28] => Location: PIN_C11, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[29] => Location: PIN_B11, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[30] => Location: PIN_B7, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[32] => Location: PIN_D8, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[33] => Location: PIN_B16, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[0] => Location: PIN_T6, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[1] => Location: PIN_N3, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[2] => Location: PIN_G16, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[3] => Location: PIN_F1, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[4] => Location: PIN_B4, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[5] => Location: PIN_L15, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[6] => Location: PIN_D14, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[7] => Location: PIN_N5, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[8] => Location: PIN_F15, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[9] => Location: PIN_R11, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[10] => Location: PIN_L1, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[11] => Location: PIN_E11, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[12] => Location: PIN_D15, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[13] => Location: PIN_T13, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[14] => Location: PIN_K16, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[15] => Location: PIN_C15, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[16] => Location: PIN_P8, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[17] => Location: PIN_R10, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[18] => Location: PIN_N1, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[19] => Location: PIN_C16, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[20] => Location: PIN_C2, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[21] => Location: PIN_N12, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[22] => Location: PIN_B5, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[23] => Location: PIN_M8, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[24] => Location: PIN_N6, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[25] => Location: PIN_F13, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[26] => Location: PIN_P3, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[27] => Location: PIN_M6, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[28] => Location: PIN_G1, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[29] => Location: PIN_J16, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[30] => Location: PIN_T14, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[31] => Location: PIN_R14, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[32] => Location: PIN_C9, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_1[33] => Location: PIN_L4, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[8] => Location: PIN_G2, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[9] => Location: PIN_D5, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[10] => Location: PIN_E7, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[11] => Location: PIN_A6, I/O Standard: 2.5 V, Current Strength: Default
-// GPIO_0_PI[31] => Location: PIN_D11, I/O Standard: 2.5 V, Current Strength: Default
-
-
-wire gnd;
-wire vcc;
-wire unknown;
-
-assign gnd = 1'b0;
-assign vcc = 1'b1;
-assign unknown = 1'bx;
-
-tri1 devclrn;
-tri1 devpor;
-tri1 devoe;
-// synopsys translate_off
-initial $sdf_annotate("SPI_test_min_1200mv_0c_v_fast.sdo");
-// synopsys translate_on
-
-wire \CLOCK_50~input_o ;
-wire \KEY[0]~input_o ;
-wire \KEY[1]~input_o ;
-wire \GPIO_2_IN[0]~input_o ;
-wire \GPIO_2_IN[1]~input_o ;
-wire \GPIO_2_IN[2]~input_o ;
-wire \GPIO_0_PI_IN[0]~input_o ;
-wire \GPIO_0_PI_IN[1]~input_o ;
-wire \GPIO_1_IN[0]~input_o ;
-wire \GPIO_1_IN[1]~input_o ;
-wire \GPIO_2[0]~input_o ;
-wire \GPIO_2[1]~input_o ;
-wire \GPIO_2[2]~input_o ;
-wire \GPIO_2[3]~input_o ;
-wire \GPIO_2[4]~input_o ;
-wire \GPIO_2[5]~input_o ;
-wire \GPIO_2[6]~input_o ;
-wire \GPIO_2[7]~input_o ;
-wire \GPIO_2[8]~input_o ;
-wire \GPIO_2[9]~input_o ;
-wire \GPIO_2[10]~input_o ;
-wire \GPIO_2[11]~input_o ;
-wire \GPIO_2[12]~input_o ;
-wire \GPIO_0_PI[0]~input_o ;
-wire \GPIO_0_PI[1]~input_o ;
-wire \GPIO_0_PI[2]~input_o ;
-wire \GPIO_0_PI[3]~input_o ;
-wire \GPIO_0_PI[4]~input_o ;
-wire \GPIO_0_PI[5]~input_o ;
-wire \GPIO_0_PI[6]~input_o ;
-wire \GPIO_0_PI[7]~input_o ;
-wire \GPIO_0_PI[12]~input_o ;
-wire \GPIO_0_PI[13]~input_o ;
-wire \GPIO_0_PI[14]~input_o ;
-wire \GPIO_0_PI[15]~input_o ;
-wire \GPIO_0_PI[16]~input_o ;
-wire \GPIO_0_PI[17]~input_o ;
-wire \GPIO_0_PI[18]~input_o ;
-wire \GPIO_0_PI[19]~input_o ;
-wire \GPIO_0_PI[20]~input_o ;
-wire \GPIO_0_PI[21]~input_o ;
-wire \GPIO_0_PI[22]~input_o ;
-wire \GPIO_0_PI[23]~input_o ;
-wire \GPIO_0_PI[24]~input_o ;
-wire \GPIO_0_PI[25]~input_o ;
-wire \GPIO_0_PI[26]~input_o ;
-wire \GPIO_0_PI[27]~input_o ;
-wire \GPIO_0_PI[28]~input_o ;
-wire \GPIO_0_PI[29]~input_o ;
-wire \GPIO_0_PI[30]~input_o ;
-wire \GPIO_0_PI[32]~input_o ;
-wire \GPIO_0_PI[33]~input_o ;
-wire \GPIO_1[0]~input_o ;
-wire \GPIO_1[1]~input_o ;
-wire \GPIO_1[2]~input_o ;
-wire \GPIO_1[3]~input_o ;
-wire \GPIO_1[4]~input_o ;
-wire \GPIO_1[5]~input_o ;
-wire \GPIO_1[6]~input_o ;
-wire \GPIO_1[7]~input_o ;
-wire \GPIO_1[8]~input_o ;
-wire \GPIO_1[9]~input_o ;
-wire \GPIO_1[10]~input_o ;
-wire \GPIO_1[11]~input_o ;
-wire \GPIO_1[12]~input_o ;
-wire \GPIO_1[13]~input_o ;
-wire \GPIO_1[14]~input_o ;
-wire \GPIO_1[15]~input_o ;
-wire \GPIO_1[16]~input_o ;
-wire \GPIO_1[17]~input_o ;
-wire \GPIO_1[18]~input_o ;
-wire \GPIO_1[19]~input_o ;
-wire \GPIO_1[20]~input_o ;
-wire \GPIO_1[21]~input_o ;
-wire \GPIO_1[22]~input_o ;
-wire \GPIO_1[23]~input_o ;
-wire \GPIO_1[24]~input_o ;
-wire \GPIO_1[25]~input_o ;
-wire \GPIO_1[26]~input_o ;
-wire \GPIO_1[27]~input_o ;
-wire \GPIO_1[28]~input_o ;
-wire \GPIO_1[29]~input_o ;
-wire \GPIO_1[30]~input_o ;
-wire \GPIO_1[31]~input_o ;
-wire \GPIO_1[32]~input_o ;
-wire \GPIO_1[33]~input_o ;
-wire \GPIO_0_PI[11]~input_o ;
-wire \GPIO_2[0]~output_o ;
-wire \GPIO_2[1]~output_o ;
-wire \GPIO_2[2]~output_o ;
-wire \GPIO_2[3]~output_o ;
-wire \GPIO_2[4]~output_o ;
-wire \GPIO_2[5]~output_o ;
-wire \GPIO_2[6]~output_o ;
-wire \GPIO_2[7]~output_o ;
-wire \GPIO_2[8]~output_o ;
-wire \GPIO_2[9]~output_o ;
-wire \GPIO_2[10]~output_o ;
-wire \GPIO_2[11]~output_o ;
-wire \GPIO_2[12]~output_o ;
-wire \GPIO_0_PI[0]~output_o ;
-wire \GPIO_0_PI[1]~output_o ;
-wire \GPIO_0_PI[2]~output_o ;
-wire \GPIO_0_PI[3]~output_o ;
-wire \GPIO_0_PI[4]~output_o ;
-wire \GPIO_0_PI[5]~output_o ;
-wire \GPIO_0_PI[6]~output_o ;
-wire \GPIO_0_PI[7]~output_o ;
-wire \GPIO_0_PI[12]~output_o ;
-wire \GPIO_0_PI[13]~output_o ;
-wire \GPIO_0_PI[14]~output_o ;
-wire \GPIO_0_PI[15]~output_o ;
-wire \GPIO_0_PI[16]~output_o ;
-wire \GPIO_0_PI[17]~output_o ;
-wire \GPIO_0_PI[18]~output_o ;
-wire \GPIO_0_PI[19]~output_o ;
-wire \GPIO_0_PI[20]~output_o ;
-wire \GPIO_0_PI[21]~output_o ;
-wire \GPIO_0_PI[22]~output_o ;
-wire \GPIO_0_PI[23]~output_o ;
-wire \GPIO_0_PI[24]~output_o ;
-wire \GPIO_0_PI[25]~output_o ;
-wire \GPIO_0_PI[26]~output_o ;
-wire \GPIO_0_PI[27]~output_o ;
-wire \GPIO_0_PI[28]~output_o ;
-wire \GPIO_0_PI[29]~output_o ;
-wire \GPIO_0_PI[30]~output_o ;
-wire \GPIO_0_PI[32]~output_o ;
-wire \GPIO_0_PI[33]~output_o ;
-wire \GPIO_1[0]~output_o ;
-wire \GPIO_1[1]~output_o ;
-wire \GPIO_1[2]~output_o ;
-wire \GPIO_1[3]~output_o ;
-wire \GPIO_1[4]~output_o ;
-wire \GPIO_1[5]~output_o ;
-wire \GPIO_1[6]~output_o ;
-wire \GPIO_1[7]~output_o ;
-wire \GPIO_1[8]~output_o ;
-wire \GPIO_1[9]~output_o ;
-wire \GPIO_1[10]~output_o ;
-wire \GPIO_1[11]~output_o ;
-wire \GPIO_1[12]~output_o ;
-wire \GPIO_1[13]~output_o ;
-wire \GPIO_1[14]~output_o ;
-wire \GPIO_1[15]~output_o ;
-wire \GPIO_1[16]~output_o ;
-wire \GPIO_1[17]~output_o ;
-wire \GPIO_1[18]~output_o ;
-wire \GPIO_1[19]~output_o ;
-wire \GPIO_1[20]~output_o ;
-wire \GPIO_1[21]~output_o ;
-wire \GPIO_1[22]~output_o ;
-wire \GPIO_1[23]~output_o ;
-wire \GPIO_1[24]~output_o ;
-wire \GPIO_1[25]~output_o ;
-wire \GPIO_1[26]~output_o ;
-wire \GPIO_1[27]~output_o ;
-wire \GPIO_1[28]~output_o ;
-wire \GPIO_1[29]~output_o ;
-wire \GPIO_1[30]~output_o ;
-wire \GPIO_1[31]~output_o ;
-wire \GPIO_1[32]~output_o ;
-wire \GPIO_1[33]~output_o ;
-wire \GPIO_0_PI[8]~output_o ;
-wire \GPIO_0_PI[9]~output_o ;
-wire \GPIO_0_PI[10]~output_o ;
-wire \GPIO_0_PI[11]~output_o ;
-wire \GPIO_0_PI[31]~output_o ;
-wire \LED[0]~output_o ;
-wire \LED[1]~output_o ;
-wire \LED[2]~output_o ;
-wire \LED[3]~output_o ;
-wire \LED[4]~output_o ;
-wire \LED[5]~output_o ;
-wire \LED[6]~output_o ;
-wire \LED[7]~output_o ;
-wire \GPIO_0_PI[8]~input_o ;
-wire \GPIO_0_PI[8]~inputclkctrl_outclk ;
-wire \spi_slave_instance|cnt[0]~12_combout ;
-wire \spi_slave_instance|cnt[1]~4_combout ;
-wire \spi_slave_instance|cnt[1]~5 ;
-wire \spi_slave_instance|cnt[2]~6_combout ;
-wire \spi_slave_instance|cnt[2]~7 ;
-wire \spi_slave_instance|cnt[3]~8_combout ;
-wire \spi_slave_instance|cnt[3]~9 ;
-wire \spi_slave_instance|cnt[4]~10_combout ;
-wire \GPIO_0_PI[31]~input_o ;
-wire \GPIO_0_PI[9]~input_o ;
-wire \spi_slave_instance|Equal0~0_combout ;
-wire \spi_slave_instance|q~31_combout ;
-wire \spi_slave_instance|q~30_combout ;
-wire \spi_slave_instance|q~29_combout ;
-wire \spi_slave_instance|q~28_combout ;
-wire \spi_slave_instance|q~27_combout ;
-wire \spi_slave_instance|q~26_combout ;
-wire \spi_slave_instance|q~25_combout ;
-wire \spi_slave_instance|q~24_combout ;
-wire \spi_slave_instance|q~23_combout ;
-wire \spi_slave_instance|q~22_combout ;
-wire \spi_slave_instance|q~21_combout ;
-wire \spi_slave_instance|q~20_combout ;
-wire \spi_slave_instance|q~19_combout ;
-wire \spi_slave_instance|q~18_combout ;
-wire \spi_slave_instance|q~17_combout ;
-wire \spi_slave_instance|q~16_combout ;
-wire \spi_slave_instance|q~15_combout ;
-wire \spi_slave_instance|q~14_combout ;
-wire \spi_slave_instance|q~13_combout ;
-wire \spi_slave_instance|q~12_combout ;
-wire \spi_slave_instance|q~10_combout ;
-wire \spi_slave_instance|q~11_combout ;
-wire \spi_slave_instance|q~9_combout ;
-wire \spi_slave_instance|q~8_combout ;
-wire \spi_slave_instance|q~7_combout ;
-wire \spi_slave_instance|q~6_combout ;
-wire \spi_slave_instance|q~5_combout ;
-wire \spi_slave_instance|q~4_combout ;
-wire \spi_slave_instance|q~3_combout ;
-wire \spi_slave_instance|q~2_combout ;
-wire \spi_slave_instance|q~1_combout ;
-wire \spi_slave_instance|q~0_combout ;
-wire \spi_slave_instance|qdelayed~q ;
-wire \spi_slave_instance|miso~0_combout ;
-wire \GPIO_0_PI[10]~input_o ;
-wire [4:0] \spi_slave_instance|cnt ;
-wire [31:0] \spi_slave_instance|q ;
-
-
-hard_block auto_generated_inst(
- .devpor(devpor),
- .devclrn(devclrn),
- .devoe(devoe));
-
-// Location: IOOBUF_X5_Y0_N23
-cycloneive_io_obuf \GPIO_2[0]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[0]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[0]~output .bus_hold = "false";
-defparam \GPIO_2[0]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X51_Y34_N23
-cycloneive_io_obuf \GPIO_2[1]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[1]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[1]~output .bus_hold = "false";
-defparam \GPIO_2[1]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y24_N23
-cycloneive_io_obuf \GPIO_2[2]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[2]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[2]~output .bus_hold = "false";
-defparam \GPIO_2[2]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y24_N16
-cycloneive_io_obuf \GPIO_2[3]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[3]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[3]~output .bus_hold = "false";
-defparam \GPIO_2[3]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X5_Y0_N16
-cycloneive_io_obuf \GPIO_2[4]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[4]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[4]~output .bus_hold = "false";
-defparam \GPIO_2[4]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y15_N2
-cycloneive_io_obuf \GPIO_2[5]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[5]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[5]~output .bus_hold = "false";
-defparam \GPIO_2[5]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X3_Y34_N2
-cycloneive_io_obuf \GPIO_2[6]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[6]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[6]~output .bus_hold = "false";
-defparam \GPIO_2[6]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X1_Y34_N9
-cycloneive_io_obuf \GPIO_2[7]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[7]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[7]~output .bus_hold = "false";
-defparam \GPIO_2[7]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X11_Y0_N16
-cycloneive_io_obuf \GPIO_2[8]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[8]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[8]~output .bus_hold = "false";
-defparam \GPIO_2[8]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X3_Y0_N2
-cycloneive_io_obuf \GPIO_2[9]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[9]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[9]~output .bus_hold = "false";
-defparam \GPIO_2[9]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X43_Y34_N23
-cycloneive_io_obuf \GPIO_2[10]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[10]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[10]~output .bus_hold = "false";
-defparam \GPIO_2[10]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X23_Y34_N16
-cycloneive_io_obuf \GPIO_2[11]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[11]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[11]~output .bus_hold = "false";
-defparam \GPIO_2[11]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X20_Y34_N9
-cycloneive_io_obuf \GPIO_2[12]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_2[12]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_2[12]~output .bus_hold = "false";
-defparam \GPIO_2[12]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X34_Y34_N9
-cycloneive_io_obuf \GPIO_0_PI[0]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[0]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[0]~output .bus_hold = "false";
-defparam \GPIO_0_PI[0]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y4_N16
-cycloneive_io_obuf \GPIO_0_PI[1]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[1]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[1]~output .bus_hold = "false";
-defparam \GPIO_0_PI[1]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y5_N23
-cycloneive_io_obuf \GPIO_0_PI[2]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[2]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[2]~output .bus_hold = "false";
-defparam \GPIO_0_PI[2]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X18_Y34_N23
-cycloneive_io_obuf \GPIO_0_PI[3]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[3]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[3]~output .bus_hold = "false";
-defparam \GPIO_0_PI[3]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X14_Y0_N16
-cycloneive_io_obuf \GPIO_0_PI[4]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[4]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[4]~output .bus_hold = "false";
-defparam \GPIO_0_PI[4]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X14_Y34_N23
-cycloneive_io_obuf \GPIO_0_PI[5]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[5]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[5]~output .bus_hold = "false";
-defparam \GPIO_0_PI[5]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X53_Y6_N16
-cycloneive_io_obuf \GPIO_0_PI[6]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[6]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[6]~output .bus_hold = "false";
-defparam \GPIO_0_PI[6]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X14_Y0_N23
-cycloneive_io_obuf \GPIO_0_PI[7]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[7]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[7]~output .bus_hold = "false";
-defparam \GPIO_0_PI[7]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y4_N23
-cycloneive_io_obuf \GPIO_0_PI[12]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[12]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[12]~output .bus_hold = "false";
-defparam \GPIO_0_PI[12]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X53_Y8_N23
-cycloneive_io_obuf \GPIO_0_PI[13]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[13]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[13]~output .bus_hold = "false";
-defparam \GPIO_0_PI[13]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X1_Y34_N2
-cycloneive_io_obuf \GPIO_0_PI[14]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[14]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[14]~output .bus_hold = "false";
-defparam \GPIO_0_PI[14]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X34_Y34_N16
-cycloneive_io_obuf \GPIO_0_PI[15]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[15]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[15]~output .bus_hold = "false";
-defparam \GPIO_0_PI[15]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X34_Y34_N2
-cycloneive_io_obuf \GPIO_0_PI[16]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[16]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[16]~output .bus_hold = "false";
-defparam \GPIO_0_PI[16]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X16_Y34_N9
-cycloneive_io_obuf \GPIO_0_PI[17]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[17]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[17]~output .bus_hold = "false";
-defparam \GPIO_0_PI[17]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X1_Y0_N9
-cycloneive_io_obuf \GPIO_0_PI[18]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[18]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[18]~output .bus_hold = "false";
-defparam \GPIO_0_PI[18]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X36_Y0_N9
-cycloneive_io_obuf \GPIO_0_PI[19]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[19]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[19]~output .bus_hold = "false";
-defparam \GPIO_0_PI[19]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y15_N9
-cycloneive_io_obuf \GPIO_0_PI[20]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[20]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[20]~output .bus_hold = "false";
-defparam \GPIO_0_PI[20]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X47_Y34_N23
-cycloneive_io_obuf \GPIO_0_PI[21]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[21]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[21]~output .bus_hold = "false";
-defparam \GPIO_0_PI[21]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X14_Y0_N9
-cycloneive_io_obuf \GPIO_0_PI[22]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[22]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[22]~output .bus_hold = "false";
-defparam \GPIO_0_PI[22]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X20_Y34_N23
-cycloneive_io_obuf \GPIO_0_PI[23]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[23]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[23]~output .bus_hold = "false";
-defparam \GPIO_0_PI[23]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X45_Y34_N2
-cycloneive_io_obuf \GPIO_0_PI[24]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[24]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[24]~output .bus_hold = "false";
-defparam \GPIO_0_PI[24]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X40_Y0_N23
-cycloneive_io_obuf \GPIO_0_PI[25]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[25]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[25]~output .bus_hold = "false";
-defparam \GPIO_0_PI[25]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X18_Y0_N9
-cycloneive_io_obuf \GPIO_0_PI[26]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[26]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[26]~output .bus_hold = "false";
-defparam \GPIO_0_PI[26]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X45_Y34_N16
-cycloneive_io_obuf \GPIO_0_PI[27]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[27]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[27]~output .bus_hold = "false";
-defparam \GPIO_0_PI[27]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X38_Y34_N2
-cycloneive_io_obuf \GPIO_0_PI[28]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[28]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[28]~output .bus_hold = "false";
-defparam \GPIO_0_PI[28]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X40_Y34_N9
-cycloneive_io_obuf \GPIO_0_PI[29]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[29]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[29]~output .bus_hold = "false";
-defparam \GPIO_0_PI[29]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X18_Y34_N2
-cycloneive_io_obuf \GPIO_0_PI[30]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[30]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[30]~output .bus_hold = "false";
-defparam \GPIO_0_PI[30]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X23_Y34_N23
-cycloneive_io_obuf \GPIO_0_PI[32]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[32]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[32]~output .bus_hold = "false";
-defparam \GPIO_0_PI[32]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X53_Y22_N2
-cycloneive_io_obuf \GPIO_0_PI[33]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[33]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[33]~output .bus_hold = "false";
-defparam \GPIO_0_PI[33]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X14_Y0_N2
-cycloneive_io_obuf \GPIO_1[0]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[0]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[0]~output .bus_hold = "false";
-defparam \GPIO_1[0]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X1_Y0_N23
-cycloneive_io_obuf \GPIO_1[1]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[1]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[1]~output .bus_hold = "false";
-defparam \GPIO_1[1]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X53_Y20_N23
-cycloneive_io_obuf \GPIO_1[2]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[2]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[2]~output .bus_hold = "false";
-defparam \GPIO_1[2]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y23_N2
-cycloneive_io_obuf \GPIO_1[3]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[3]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[3]~output .bus_hold = "false";
-defparam \GPIO_1[3]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X7_Y34_N2
-cycloneive_io_obuf \GPIO_1[4]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[4]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[4]~output .bus_hold = "false";
-defparam \GPIO_1[4]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X53_Y11_N2
-cycloneive_io_obuf \GPIO_1[5]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[5]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[5]~output .bus_hold = "false";
-defparam \GPIO_1[5]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X51_Y34_N9
-cycloneive_io_obuf \GPIO_1[6]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[6]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[6]~output .bus_hold = "false";
-defparam \GPIO_1[6]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X5_Y0_N9
-cycloneive_io_obuf \GPIO_1[7]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[7]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[7]~output .bus_hold = "false";
-defparam \GPIO_1[7]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X53_Y22_N9
-cycloneive_io_obuf \GPIO_1[8]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[8]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[8]~output .bus_hold = "false";
-defparam \GPIO_1[8]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X34_Y0_N2
-cycloneive_io_obuf \GPIO_1[9]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[9]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[9]~output .bus_hold = "false";
-defparam \GPIO_1[9]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y11_N9
-cycloneive_io_obuf \GPIO_1[10]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[10]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[10]~output .bus_hold = "false";
-defparam \GPIO_1[10]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X45_Y34_N9
-cycloneive_io_obuf \GPIO_1[11]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[11]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[11]~output .bus_hold = "false";
-defparam \GPIO_1[11]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X53_Y26_N23
-cycloneive_io_obuf \GPIO_1[12]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[12]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[12]~output .bus_hold = "false";
-defparam \GPIO_1[12]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X40_Y0_N16
-cycloneive_io_obuf \GPIO_1[13]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[13]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[13]~output .bus_hold = "false";
-defparam \GPIO_1[13]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X53_Y12_N2
-cycloneive_io_obuf \GPIO_1[14]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[14]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[14]~output .bus_hold = "false";
-defparam \GPIO_1[14]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X53_Y30_N2
-cycloneive_io_obuf \GPIO_1[15]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[15]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[15]~output .bus_hold = "false";
-defparam \GPIO_1[15]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X25_Y0_N16
-cycloneive_io_obuf \GPIO_1[16]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[16]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[16]~output .bus_hold = "false";
-defparam \GPIO_1[16]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X34_Y0_N23
-cycloneive_io_obuf \GPIO_1[17]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[17]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[17]~output .bus_hold = "false";
-defparam \GPIO_1[17]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y7_N2
-cycloneive_io_obuf \GPIO_1[18]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[18]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[18]~output .bus_hold = "false";
-defparam \GPIO_1[18]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X53_Y30_N9
-cycloneive_io_obuf \GPIO_1[19]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[19]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[19]~output .bus_hold = "false";
-defparam \GPIO_1[19]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y27_N2
-cycloneive_io_obuf \GPIO_1[20]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[20]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[20]~output .bus_hold = "false";
-defparam \GPIO_1[20]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X47_Y0_N23
-cycloneive_io_obuf \GPIO_1[21]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[21]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[21]~output .bus_hold = "false";
-defparam \GPIO_1[21]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X11_Y34_N2
-cycloneive_io_obuf \GPIO_1[22]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[22]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[22]~output .bus_hold = "false";
-defparam \GPIO_1[22]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X20_Y0_N9
-cycloneive_io_obuf \GPIO_1[23]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[23]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[23]~output .bus_hold = "false";
-defparam \GPIO_1[23]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X5_Y0_N2
-cycloneive_io_obuf \GPIO_1[24]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[24]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[24]~output .bus_hold = "false";
-defparam \GPIO_1[24]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X53_Y21_N23
-cycloneive_io_obuf \GPIO_1[25]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[25]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[25]~output .bus_hold = "false";
-defparam \GPIO_1[25]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X1_Y0_N16
-cycloneive_io_obuf \GPIO_1[26]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[26]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[26]~output .bus_hold = "false";
-defparam \GPIO_1[26]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X7_Y0_N9
-cycloneive_io_obuf \GPIO_1[27]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[27]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[27]~output .bus_hold = "false";
-defparam \GPIO_1[27]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y23_N23
-cycloneive_io_obuf \GPIO_1[28]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[28]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[28]~output .bus_hold = "false";
-defparam \GPIO_1[28]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X53_Y14_N9
-cycloneive_io_obuf \GPIO_1[29]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[29]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[29]~output .bus_hold = "false";
-defparam \GPIO_1[29]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X45_Y0_N23
-cycloneive_io_obuf \GPIO_1[30]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[30]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[30]~output .bus_hold = "false";
-defparam \GPIO_1[30]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X49_Y0_N2
-cycloneive_io_obuf \GPIO_1[31]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[31]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[31]~output .bus_hold = "false";
-defparam \GPIO_1[31]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X31_Y34_N2
-cycloneive_io_obuf \GPIO_1[32]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[32]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[32]~output .bus_hold = "false";
-defparam \GPIO_1[32]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y6_N16
-cycloneive_io_obuf \GPIO_1[33]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_1[33]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_1[33]~output .bus_hold = "false";
-defparam \GPIO_1[33]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y23_N16
-cycloneive_io_obuf \GPIO_0_PI[8]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[8]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[8]~output .bus_hold = "false";
-defparam \GPIO_0_PI[8]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X5_Y34_N16
-cycloneive_io_obuf \GPIO_0_PI[9]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[9]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[9]~output .bus_hold = "false";
-defparam \GPIO_0_PI[9]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X16_Y34_N16
-cycloneive_io_obuf \GPIO_0_PI[10]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[10]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[10]~output .bus_hold = "false";
-defparam \GPIO_0_PI[10]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X16_Y34_N2
-cycloneive_io_obuf \GPIO_0_PI[11]~output (
- .i(\spi_slave_instance|miso~0_combout ),
- .oe(!\GPIO_0_PI[10]~input_o ),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[11]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[11]~output .bus_hold = "false";
-defparam \GPIO_0_PI[11]~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X51_Y34_N16
-cycloneive_io_obuf \GPIO_0_PI[31]~output (
- .i(vcc),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\GPIO_0_PI[31]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \GPIO_0_PI[31]~output .bus_hold = "false";
-defparam \GPIO_0_PI[31]~output .open_drain_output = "true";
-// synopsys translate_on
-
-// Location: IOOBUF_X38_Y34_N16
-cycloneive_io_obuf \LED[0]~output (
- .i(gnd),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\LED[0]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \LED[0]~output .bus_hold = "false";
-defparam \LED[0]~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X49_Y34_N2
-cycloneive_io_obuf \LED[1]~output (
- .i(gnd),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\LED[1]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \LED[1]~output .bus_hold = "false";
-defparam \LED[1]~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X49_Y34_N9
-cycloneive_io_obuf \LED[2]~output (
- .i(gnd),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\LED[2]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \LED[2]~output .bus_hold = "false";
-defparam \LED[2]~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X40_Y34_N2
-cycloneive_io_obuf \LED[3]~output (
- .i(gnd),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\LED[3]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \LED[3]~output .bus_hold = "false";
-defparam \LED[3]~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y25_N9
-cycloneive_io_obuf \LED[4]~output (
- .i(gnd),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\LED[4]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \LED[4]~output .bus_hold = "false";
-defparam \LED[4]~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y26_N16
-cycloneive_io_obuf \LED[5]~output (
- .i(gnd),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\LED[5]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \LED[5]~output .bus_hold = "false";
-defparam \LED[5]~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y28_N9
-cycloneive_io_obuf \LED[6]~output (
- .i(gnd),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\LED[6]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \LED[6]~output .bus_hold = "false";
-defparam \LED[6]~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOOBUF_X0_Y10_N23
-cycloneive_io_obuf \LED[7]~output (
- .i(gnd),
- .oe(vcc),
- .seriesterminationcontrol(16'b0000000000000000),
- .devoe(devoe),
- .o(\LED[7]~output_o ),
- .obar());
-// synopsys translate_off
-defparam \LED[7]~output .bus_hold = "false";
-defparam \LED[7]~output .open_drain_output = "false";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y23_N15
-cycloneive_io_ibuf \GPIO_0_PI[8]~input (
- .i(GPIO_0_PI[8]),
- .ibar(gnd),
- .o(\GPIO_0_PI[8]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[8]~input .bus_hold = "false";
-defparam \GPIO_0_PI[8]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: CLKCTRL_G0
-cycloneive_clkctrl \GPIO_0_PI[8]~inputclkctrl (
- .ena(vcc),
- .inclk({vcc,vcc,vcc,\GPIO_0_PI[8]~input_o }),
- .clkselect(2'b00),
- .devclrn(devclrn),
- .devpor(devpor),
- .outclk(\GPIO_0_PI[8]~inputclkctrl_outclk ));
-// synopsys translate_off
-defparam \GPIO_0_PI[8]~inputclkctrl .clock_type = "global clock";
-defparam \GPIO_0_PI[8]~inputclkctrl .ena_register_mode = "none";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N12
-cycloneive_lcell_comb \spi_slave_instance|cnt[0]~12 (
-// Equation(s):
-// \spi_slave_instance|cnt[0]~12_combout = !\spi_slave_instance|cnt [0]
-
- .dataa(gnd),
- .datab(gnd),
- .datac(\spi_slave_instance|cnt [0]),
- .datad(gnd),
- .cin(gnd),
- .combout(\spi_slave_instance|cnt[0]~12_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|cnt[0]~12 .lut_mask = 16'h0F0F;
-defparam \spi_slave_instance|cnt[0]~12 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N13
-dffeas \spi_slave_instance|cnt[0] (
- .clk(!\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|cnt[0]~12_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|cnt [0]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|cnt[0] .is_wysiwyg = "true";
-defparam \spi_slave_instance|cnt[0] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N2
-cycloneive_lcell_comb \spi_slave_instance|cnt[1]~4 (
-// Equation(s):
-// \spi_slave_instance|cnt[1]~4_combout = (\spi_slave_instance|cnt [0] & (\spi_slave_instance|cnt [1] $ (VCC))) # (!\spi_slave_instance|cnt [0] & (\spi_slave_instance|cnt [1] & VCC))
-// \spi_slave_instance|cnt[1]~5 = CARRY((\spi_slave_instance|cnt [0] & \spi_slave_instance|cnt [1]))
-
- .dataa(\spi_slave_instance|cnt [0]),
- .datab(\spi_slave_instance|cnt [1]),
- .datac(gnd),
- .datad(vcc),
- .cin(gnd),
- .combout(\spi_slave_instance|cnt[1]~4_combout ),
- .cout(\spi_slave_instance|cnt[1]~5 ));
-// synopsys translate_off
-defparam \spi_slave_instance|cnt[1]~4 .lut_mask = 16'h6688;
-defparam \spi_slave_instance|cnt[1]~4 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N3
-dffeas \spi_slave_instance|cnt[1] (
- .clk(!\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|cnt[1]~4_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|cnt [1]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|cnt[1] .is_wysiwyg = "true";
-defparam \spi_slave_instance|cnt[1] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N4
-cycloneive_lcell_comb \spi_slave_instance|cnt[2]~6 (
-// Equation(s):
-// \spi_slave_instance|cnt[2]~6_combout = (\spi_slave_instance|cnt [2] & (!\spi_slave_instance|cnt[1]~5 )) # (!\spi_slave_instance|cnt [2] & ((\spi_slave_instance|cnt[1]~5 ) # (GND)))
-// \spi_slave_instance|cnt[2]~7 = CARRY((!\spi_slave_instance|cnt[1]~5 ) # (!\spi_slave_instance|cnt [2]))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|cnt [2]),
- .datac(gnd),
- .datad(vcc),
- .cin(\spi_slave_instance|cnt[1]~5 ),
- .combout(\spi_slave_instance|cnt[2]~6_combout ),
- .cout(\spi_slave_instance|cnt[2]~7 ));
-// synopsys translate_off
-defparam \spi_slave_instance|cnt[2]~6 .lut_mask = 16'h3C3F;
-defparam \spi_slave_instance|cnt[2]~6 .sum_lutc_input = "cin";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N5
-dffeas \spi_slave_instance|cnt[2] (
- .clk(!\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|cnt[2]~6_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|cnt [2]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|cnt[2] .is_wysiwyg = "true";
-defparam \spi_slave_instance|cnt[2] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N6
-cycloneive_lcell_comb \spi_slave_instance|cnt[3]~8 (
-// Equation(s):
-// \spi_slave_instance|cnt[3]~8_combout = (\spi_slave_instance|cnt [3] & (\spi_slave_instance|cnt[2]~7 $ (GND))) # (!\spi_slave_instance|cnt [3] & (!\spi_slave_instance|cnt[2]~7 & VCC))
-// \spi_slave_instance|cnt[3]~9 = CARRY((\spi_slave_instance|cnt [3] & !\spi_slave_instance|cnt[2]~7 ))
-
- .dataa(\spi_slave_instance|cnt [3]),
- .datab(gnd),
- .datac(gnd),
- .datad(vcc),
- .cin(\spi_slave_instance|cnt[2]~7 ),
- .combout(\spi_slave_instance|cnt[3]~8_combout ),
- .cout(\spi_slave_instance|cnt[3]~9 ));
-// synopsys translate_off
-defparam \spi_slave_instance|cnt[3]~8 .lut_mask = 16'hA50A;
-defparam \spi_slave_instance|cnt[3]~8 .sum_lutc_input = "cin";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N7
-dffeas \spi_slave_instance|cnt[3] (
- .clk(!\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|cnt[3]~8_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|cnt [3]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|cnt[3] .is_wysiwyg = "true";
-defparam \spi_slave_instance|cnt[3] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N8
-cycloneive_lcell_comb \spi_slave_instance|cnt[4]~10 (
-// Equation(s):
-// \spi_slave_instance|cnt[4]~10_combout = \spi_slave_instance|cnt [4] $ (\spi_slave_instance|cnt[3]~9 )
-
- .dataa(gnd),
- .datab(\spi_slave_instance|cnt [4]),
- .datac(gnd),
- .datad(gnd),
- .cin(\spi_slave_instance|cnt[3]~9 ),
- .combout(\spi_slave_instance|cnt[4]~10_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|cnt[4]~10 .lut_mask = 16'h3C3C;
-defparam \spi_slave_instance|cnt[4]~10 .sum_lutc_input = "cin";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N9
-dffeas \spi_slave_instance|cnt[4] (
- .clk(!\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|cnt[4]~10_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|cnt [4]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|cnt[4] .is_wysiwyg = "true";
-defparam \spi_slave_instance|cnt[4] .power_up = "low";
-// synopsys translate_on
-
-// Location: IOIBUF_X51_Y34_N15
-cycloneive_io_ibuf \GPIO_0_PI[31]~input (
- .i(GPIO_0_PI[31]),
- .ibar(gnd),
- .o(\GPIO_0_PI[31]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[31]~input .bus_hold = "false";
-defparam \GPIO_0_PI[31]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X5_Y34_N15
-cycloneive_io_ibuf \GPIO_0_PI[9]~input (
- .i(GPIO_0_PI[9]),
- .ibar(gnd),
- .o(\GPIO_0_PI[9]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[9]~input .bus_hold = "false";
-defparam \GPIO_0_PI[9]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: FF_X21_Y31_N5
-dffeas \spi_slave_instance|q[0] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(gnd),
- .asdata(\GPIO_0_PI[9]~input_o ),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(vcc),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [0]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[0] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[0] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N18
-cycloneive_lcell_comb \spi_slave_instance|Equal0~0 (
-// Equation(s):
-// \spi_slave_instance|Equal0~0_combout = (!\spi_slave_instance|cnt [0] & (!\spi_slave_instance|cnt [1] & (!\spi_slave_instance|cnt [2] & !\spi_slave_instance|cnt [3])))
-
- .dataa(\spi_slave_instance|cnt [0]),
- .datab(\spi_slave_instance|cnt [1]),
- .datac(\spi_slave_instance|cnt [2]),
- .datad(\spi_slave_instance|cnt [3]),
- .cin(gnd),
- .combout(\spi_slave_instance|Equal0~0_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|Equal0~0 .lut_mask = 16'h0001;
-defparam \spi_slave_instance|Equal0~0 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: LCCOMB_X21_Y31_N22
-cycloneive_lcell_comb \spi_slave_instance|q~31 (
-// Equation(s):
-// \spi_slave_instance|q~31_combout = (\spi_slave_instance|cnt [4] & (((\spi_slave_instance|q [0])))) # (!\spi_slave_instance|cnt [4] & ((\spi_slave_instance|Equal0~0_combout & (\GPIO_0_PI[31]~input_o )) # (!\spi_slave_instance|Equal0~0_combout &
-// ((\spi_slave_instance|q [0])))))
-
- .dataa(\spi_slave_instance|cnt [4]),
- .datab(\GPIO_0_PI[31]~input_o ),
- .datac(\spi_slave_instance|q [0]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~31_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~31 .lut_mask = 16'hE4F0;
-defparam \spi_slave_instance|q~31 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X21_Y31_N23
-dffeas \spi_slave_instance|q[1] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~31_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [1]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[1] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[1] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X21_Y31_N24
-cycloneive_lcell_comb \spi_slave_instance|q~30 (
-// Equation(s):
-// \spi_slave_instance|q~30_combout = (\spi_slave_instance|q [1] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(\spi_slave_instance|cnt [4]),
- .datab(gnd),
- .datac(\spi_slave_instance|q [1]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~30_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~30 .lut_mask = 16'hA0F0;
-defparam \spi_slave_instance|q~30 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X21_Y31_N25
-dffeas \spi_slave_instance|q[2] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~30_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [2]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[2] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[2] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X21_Y31_N30
-cycloneive_lcell_comb \spi_slave_instance|q~29 (
-// Equation(s):
-// \spi_slave_instance|q~29_combout = (\spi_slave_instance|q [2] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(\spi_slave_instance|cnt [4]),
- .datab(\spi_slave_instance|q [2]),
- .datac(gnd),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~29_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~29 .lut_mask = 16'h88CC;
-defparam \spi_slave_instance|q~29 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X21_Y31_N31
-dffeas \spi_slave_instance|q[3] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~29_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [3]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[3] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[3] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X21_Y31_N8
-cycloneive_lcell_comb \spi_slave_instance|q~28 (
-// Equation(s):
-// \spi_slave_instance|q~28_combout = (\spi_slave_instance|q [3] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(\spi_slave_instance|cnt [4]),
- .datab(gnd),
- .datac(\spi_slave_instance|q [3]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~28_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~28 .lut_mask = 16'hA0F0;
-defparam \spi_slave_instance|q~28 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X21_Y31_N9
-dffeas \spi_slave_instance|q[4] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~28_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [4]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[4] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[4] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X21_Y31_N18
-cycloneive_lcell_comb \spi_slave_instance|q~27 (
-// Equation(s):
-// \spi_slave_instance|q~27_combout = (\spi_slave_instance|q [4] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(\spi_slave_instance|cnt [4]),
- .datab(gnd),
- .datac(\spi_slave_instance|q [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~27_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~27 .lut_mask = 16'hA0F0;
-defparam \spi_slave_instance|q~27 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X21_Y31_N19
-dffeas \spi_slave_instance|q[5] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~27_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [5]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[5] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[5] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X21_Y31_N28
-cycloneive_lcell_comb \spi_slave_instance|q~26 (
-// Equation(s):
-// \spi_slave_instance|q~26_combout = (\spi_slave_instance|q [5] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(\spi_slave_instance|cnt [4]),
- .datab(\spi_slave_instance|q [5]),
- .datac(gnd),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~26_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~26 .lut_mask = 16'h88CC;
-defparam \spi_slave_instance|q~26 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X21_Y31_N29
-dffeas \spi_slave_instance|q[6] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~26_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [6]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[6] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[6] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X21_Y31_N10
-cycloneive_lcell_comb \spi_slave_instance|q~25 (
-// Equation(s):
-// \spi_slave_instance|q~25_combout = (\spi_slave_instance|q [6] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(\spi_slave_instance|cnt [4]),
- .datab(\spi_slave_instance|q [6]),
- .datac(gnd),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~25_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~25 .lut_mask = 16'h88CC;
-defparam \spi_slave_instance|q~25 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X21_Y31_N11
-dffeas \spi_slave_instance|q[7] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~25_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [7]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[7] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[7] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N14
-cycloneive_lcell_comb \spi_slave_instance|q~24 (
-// Equation(s):
-// \spi_slave_instance|q~24_combout = (\spi_slave_instance|q [7] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|cnt [4]),
- .datac(\spi_slave_instance|q [7]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~24_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~24 .lut_mask = 16'hC0F0;
-defparam \spi_slave_instance|q~24 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N15
-dffeas \spi_slave_instance|q[8] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~24_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [8]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[8] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[8] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N28
-cycloneive_lcell_comb \spi_slave_instance|q~23 (
-// Equation(s):
-// \spi_slave_instance|q~23_combout = (\spi_slave_instance|q [8] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|q [8]),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~23_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~23 .lut_mask = 16'hC0CC;
-defparam \spi_slave_instance|q~23 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N29
-dffeas \spi_slave_instance|q[9] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~23_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [9]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[9] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[9] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N30
-cycloneive_lcell_comb \spi_slave_instance|q~22 (
-// Equation(s):
-// \spi_slave_instance|q~22_combout = (\spi_slave_instance|q [9] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|q [9]),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~22_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~22 .lut_mask = 16'hC0CC;
-defparam \spi_slave_instance|q~22 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N31
-dffeas \spi_slave_instance|q[10] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~22_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [10]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[10] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[10] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N24
-cycloneive_lcell_comb \spi_slave_instance|q~21 (
-// Equation(s):
-// \spi_slave_instance|q~21_combout = (\spi_slave_instance|q [10] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|cnt [4]),
- .datac(\spi_slave_instance|q [10]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~21_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~21 .lut_mask = 16'hC0F0;
-defparam \spi_slave_instance|q~21 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N25
-dffeas \spi_slave_instance|q[11] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~21_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [11]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[11] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[11] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N26
-cycloneive_lcell_comb \spi_slave_instance|q~20 (
-// Equation(s):
-// \spi_slave_instance|q~20_combout = (\spi_slave_instance|q [11] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|q [11]),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~20_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~20 .lut_mask = 16'hC0CC;
-defparam \spi_slave_instance|q~20 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N27
-dffeas \spi_slave_instance|q[12] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~20_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [12]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[12] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[12] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X21_Y31_N20
-cycloneive_lcell_comb \spi_slave_instance|q~19 (
-// Equation(s):
-// \spi_slave_instance|q~19_combout = (\spi_slave_instance|q [12] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(\spi_slave_instance|cnt [4]),
- .datab(gnd),
- .datac(\spi_slave_instance|q [12]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~19_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~19 .lut_mask = 16'hA0F0;
-defparam \spi_slave_instance|q~19 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X21_Y31_N21
-dffeas \spi_slave_instance|q[13] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~19_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [13]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[13] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[13] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N16
-cycloneive_lcell_comb \spi_slave_instance|q~18 (
-// Equation(s):
-// \spi_slave_instance|q~18_combout = (\spi_slave_instance|q [13] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|cnt [4]),
- .datac(\spi_slave_instance|q [13]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~18_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~18 .lut_mask = 16'hC0F0;
-defparam \spi_slave_instance|q~18 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N17
-dffeas \spi_slave_instance|q[14] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~18_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [14]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[14] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[14] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N10
-cycloneive_lcell_comb \spi_slave_instance|q~17 (
-// Equation(s):
-// \spi_slave_instance|q~17_combout = (\spi_slave_instance|q [14] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|q [14]),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~17_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~17 .lut_mask = 16'hC0CC;
-defparam \spi_slave_instance|q~17 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N11
-dffeas \spi_slave_instance|q[15] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~17_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [15]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[15] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[15] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N20
-cycloneive_lcell_comb \spi_slave_instance|q~16 (
-// Equation(s):
-// \spi_slave_instance|q~16_combout = (\spi_slave_instance|q [15] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|cnt [4]),
- .datac(\spi_slave_instance|q [15]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~16_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~16 .lut_mask = 16'hC0F0;
-defparam \spi_slave_instance|q~16 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N21
-dffeas \spi_slave_instance|q[16] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~16_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [16]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[16] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[16] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N22
-cycloneive_lcell_comb \spi_slave_instance|q~15 (
-// Equation(s):
-// \spi_slave_instance|q~15_combout = (\spi_slave_instance|q [16] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|q [16]),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~15_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~15 .lut_mask = 16'hC0CC;
-defparam \spi_slave_instance|q~15 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N23
-dffeas \spi_slave_instance|q[17] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~15_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [17]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[17] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[17] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X20_Y31_N0
-cycloneive_lcell_comb \spi_slave_instance|q~14 (
-// Equation(s):
-// \spi_slave_instance|q~14_combout = (\spi_slave_instance|q [17] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|cnt [4]),
- .datac(\spi_slave_instance|q [17]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~14_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~14 .lut_mask = 16'hC0F0;
-defparam \spi_slave_instance|q~14 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X20_Y31_N1
-dffeas \spi_slave_instance|q[18] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~14_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [18]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[18] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[18] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N28
-cycloneive_lcell_comb \spi_slave_instance|q~13 (
-// Equation(s):
-// \spi_slave_instance|q~13_combout = (\spi_slave_instance|q [18] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|cnt [4]),
- .datac(\spi_slave_instance|q [18]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~13_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~13 .lut_mask = 16'hC0F0;
-defparam \spi_slave_instance|q~13 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N29
-dffeas \spi_slave_instance|q[19] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~13_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [19]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[19] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[19] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N8
-cycloneive_lcell_comb \spi_slave_instance|q~12 (
-// Equation(s):
-// \spi_slave_instance|q~12_combout = (\spi_slave_instance|q [19] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|q [19]),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~12_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~12 .lut_mask = 16'hC0CC;
-defparam \spi_slave_instance|q~12 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N9
-dffeas \spi_slave_instance|q[20] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~12_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [20]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[20] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[20] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N10
-cycloneive_lcell_comb \spi_slave_instance|q~10 (
-// Equation(s):
-// \spi_slave_instance|q~10_combout = (\spi_slave_instance|cnt [1]) # ((\spi_slave_instance|cnt [4]) # (\spi_slave_instance|cnt [3]))
-
- .dataa(\spi_slave_instance|cnt [1]),
- .datab(gnd),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|cnt [3]),
- .cin(gnd),
- .combout(\spi_slave_instance|q~10_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~10 .lut_mask = 16'hFFFA;
-defparam \spi_slave_instance|q~10 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N26
-cycloneive_lcell_comb \spi_slave_instance|q~11 (
-// Equation(s):
-// \spi_slave_instance|q~11_combout = (\spi_slave_instance|q [20] & ((\spi_slave_instance|cnt [2]) # ((\spi_slave_instance|cnt [0]) # (\spi_slave_instance|q~10_combout ))))
-
- .dataa(\spi_slave_instance|cnt [2]),
- .datab(\spi_slave_instance|q [20]),
- .datac(\spi_slave_instance|cnt [0]),
- .datad(\spi_slave_instance|q~10_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~11_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~11 .lut_mask = 16'hCCC8;
-defparam \spi_slave_instance|q~11 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N27
-dffeas \spi_slave_instance|q[21] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~11_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [21]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[21] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[21] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N12
-cycloneive_lcell_comb \spi_slave_instance|q~9 (
-// Equation(s):
-// \spi_slave_instance|q~9_combout = (\spi_slave_instance|q [21] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(\spi_slave_instance|q [21]),
- .datab(gnd),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~9_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~9 .lut_mask = 16'hA0AA;
-defparam \spi_slave_instance|q~9 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N13
-dffeas \spi_slave_instance|q[22] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~9_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [22]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[22] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[22] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N6
-cycloneive_lcell_comb \spi_slave_instance|q~8 (
-// Equation(s):
-// \spi_slave_instance|q~8_combout = (\spi_slave_instance|q [22] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(\spi_slave_instance|q [22]),
- .datab(gnd),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~8_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~8 .lut_mask = 16'hA0AA;
-defparam \spi_slave_instance|q~8 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N7
-dffeas \spi_slave_instance|q[23] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~8_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [23]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[23] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[23] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N4
-cycloneive_lcell_comb \spi_slave_instance|q~7 (
-// Equation(s):
-// \spi_slave_instance|q~7_combout = (\spi_slave_instance|q [23] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(\spi_slave_instance|q [23]),
- .datab(gnd),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~7_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~7 .lut_mask = 16'hA0AA;
-defparam \spi_slave_instance|q~7 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N5
-dffeas \spi_slave_instance|q[24] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~7_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [24]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[24] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[24] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N30
-cycloneive_lcell_comb \spi_slave_instance|q~6 (
-// Equation(s):
-// \spi_slave_instance|q~6_combout = (\spi_slave_instance|q [24] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|q [24]),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~6_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~6 .lut_mask = 16'hC0CC;
-defparam \spi_slave_instance|q~6 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N31
-dffeas \spi_slave_instance|q[25] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~6_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [25]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[25] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[25] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N20
-cycloneive_lcell_comb \spi_slave_instance|q~5 (
-// Equation(s):
-// \spi_slave_instance|q~5_combout = (\spi_slave_instance|q [25] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(\spi_slave_instance|q [25]),
- .datab(gnd),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~5_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~5 .lut_mask = 16'hA0AA;
-defparam \spi_slave_instance|q~5 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N21
-dffeas \spi_slave_instance|q[26] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~5_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [26]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[26] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[26] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N14
-cycloneive_lcell_comb \spi_slave_instance|q~4 (
-// Equation(s):
-// \spi_slave_instance|q~4_combout = (\spi_slave_instance|q [26] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|q [26]),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~4_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~4 .lut_mask = 16'hC0CC;
-defparam \spi_slave_instance|q~4 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N15
-dffeas \spi_slave_instance|q[27] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~4_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [27]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[27] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[27] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N16
-cycloneive_lcell_comb \spi_slave_instance|q~3 (
-// Equation(s):
-// \spi_slave_instance|q~3_combout = (\spi_slave_instance|q [27] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|q [27]),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~3_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~3 .lut_mask = 16'hC0CC;
-defparam \spi_slave_instance|q~3 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N17
-dffeas \spi_slave_instance|q[28] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~3_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [28]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[28] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[28] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N18
-cycloneive_lcell_comb \spi_slave_instance|q~2 (
-// Equation(s):
-// \spi_slave_instance|q~2_combout = (\spi_slave_instance|q [28] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|q [28]),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~2_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~2 .lut_mask = 16'hC0CC;
-defparam \spi_slave_instance|q~2 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N19
-dffeas \spi_slave_instance|q[29] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~2_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [29]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[29] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[29] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N24
-cycloneive_lcell_comb \spi_slave_instance|q~1 (
-// Equation(s):
-// \spi_slave_instance|q~1_combout = (\spi_slave_instance|q [29] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|q [29]),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~1_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~1 .lut_mask = 16'hC0CC;
-defparam \spi_slave_instance|q~1 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N25
-dffeas \spi_slave_instance|q[30] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~1_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [30]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[30] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[30] .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N22
-cycloneive_lcell_comb \spi_slave_instance|q~0 (
-// Equation(s):
-// \spi_slave_instance|q~0_combout = (\spi_slave_instance|q [30] & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|q [30]),
- .datac(\spi_slave_instance|cnt [4]),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|q~0_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|q~0 .lut_mask = 16'hC0CC;
-defparam \spi_slave_instance|q~0 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N23
-dffeas \spi_slave_instance|q[31] (
- .clk(\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(\spi_slave_instance|q~0_combout ),
- .asdata(vcc),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(gnd),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|q [31]),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|q[31] .is_wysiwyg = "true";
-defparam \spi_slave_instance|q[31] .power_up = "low";
-// synopsys translate_on
-
-// Location: FF_X19_Y31_N1
-dffeas \spi_slave_instance|qdelayed (
- .clk(!\GPIO_0_PI[8]~inputclkctrl_outclk ),
- .d(gnd),
- .asdata(\spi_slave_instance|q [31]),
- .clrn(vcc),
- .aload(gnd),
- .sclr(gnd),
- .sload(vcc),
- .ena(vcc),
- .devclrn(devclrn),
- .devpor(devpor),
- .q(\spi_slave_instance|qdelayed~q ),
- .prn(vcc));
-// synopsys translate_off
-defparam \spi_slave_instance|qdelayed .is_wysiwyg = "true";
-defparam \spi_slave_instance|qdelayed .power_up = "low";
-// synopsys translate_on
-
-// Location: LCCOMB_X19_Y31_N0
-cycloneive_lcell_comb \spi_slave_instance|miso~0 (
-// Equation(s):
-// \spi_slave_instance|miso~0_combout = (\spi_slave_instance|qdelayed~q & ((\spi_slave_instance|cnt [4]) # (!\spi_slave_instance|Equal0~0_combout )))
-
- .dataa(gnd),
- .datab(\spi_slave_instance|cnt [4]),
- .datac(\spi_slave_instance|qdelayed~q ),
- .datad(\spi_slave_instance|Equal0~0_combout ),
- .cin(gnd),
- .combout(\spi_slave_instance|miso~0_combout ),
- .cout());
-// synopsys translate_off
-defparam \spi_slave_instance|miso~0 .lut_mask = 16'hC0F0;
-defparam \spi_slave_instance|miso~0 .sum_lutc_input = "datac";
-// synopsys translate_on
-
-// Location: IOIBUF_X16_Y34_N15
-cycloneive_io_ibuf \GPIO_0_PI[10]~input (
- .i(GPIO_0_PI[10]),
- .ibar(gnd),
- .o(\GPIO_0_PI[10]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[10]~input .bus_hold = "false";
-defparam \GPIO_0_PI[10]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X16_Y0_N15
-cycloneive_io_ibuf \CLOCK_50~input (
- .i(CLOCK_50),
- .ibar(gnd),
- .o(\CLOCK_50~input_o ));
-// synopsys translate_off
-defparam \CLOCK_50~input .bus_hold = "false";
-defparam \CLOCK_50~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y14_N1
-cycloneive_io_ibuf \KEY[0]~input (
- .i(KEY[0]),
- .ibar(gnd),
- .o(\KEY[0]~input_o ));
-// synopsys translate_off
-defparam \KEY[0]~input .bus_hold = "false";
-defparam \KEY[0]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y16_N8
-cycloneive_io_ibuf \KEY[1]~input (
- .i(KEY[1]),
- .ibar(gnd),
- .o(\KEY[1]~input_o ));
-// synopsys translate_off
-defparam \KEY[1]~input .bus_hold = "false";
-defparam \KEY[1]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y17_N8
-cycloneive_io_ibuf \GPIO_2_IN[0]~input (
- .i(GPIO_2_IN[0]),
- .ibar(gnd),
- .o(\GPIO_2_IN[0]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2_IN[0]~input .bus_hold = "false";
-defparam \GPIO_2_IN[0]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y17_N1
-cycloneive_io_ibuf \GPIO_2_IN[1]~input (
- .i(GPIO_2_IN[1]),
- .ibar(gnd),
- .o(\GPIO_2_IN[1]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2_IN[1]~input .bus_hold = "false";
-defparam \GPIO_2_IN[1]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X9_Y34_N8
-cycloneive_io_ibuf \GPIO_2_IN[2]~input (
- .i(GPIO_2_IN[2]),
- .ibar(gnd),
- .o(\GPIO_2_IN[2]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2_IN[2]~input .bus_hold = "false";
-defparam \GPIO_2_IN[2]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X14_Y34_N15
-cycloneive_io_ibuf \GPIO_0_PI_IN[0]~input (
- .i(GPIO_0_PI_IN[0]),
- .ibar(gnd),
- .o(\GPIO_0_PI_IN[0]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI_IN[0]~input .bus_hold = "false";
-defparam \GPIO_0_PI_IN[0]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X51_Y34_N1
-cycloneive_io_ibuf \GPIO_0_PI_IN[1]~input (
- .i(GPIO_0_PI_IN[1]),
- .ibar(gnd),
- .o(\GPIO_0_PI_IN[1]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI_IN[1]~input .bus_hold = "false";
-defparam \GPIO_0_PI_IN[1]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X43_Y34_N15
-cycloneive_io_ibuf \GPIO_1_IN[0]~input (
- .i(GPIO_1_IN[0]),
- .ibar(gnd),
- .o(\GPIO_1_IN[0]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1_IN[0]~input .bus_hold = "false";
-defparam \GPIO_1_IN[0]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X34_Y0_N15
-cycloneive_io_ibuf \GPIO_1_IN[1]~input (
- .i(GPIO_1_IN[1]),
- .ibar(gnd),
- .o(\GPIO_1_IN[1]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1_IN[1]~input .bus_hold = "false";
-defparam \GPIO_1_IN[1]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X5_Y0_N22
-cycloneive_io_ibuf \GPIO_2[0]~input (
- .i(GPIO_2[0]),
- .ibar(gnd),
- .o(\GPIO_2[0]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[0]~input .bus_hold = "false";
-defparam \GPIO_2[0]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X51_Y34_N22
-cycloneive_io_ibuf \GPIO_2[1]~input (
- .i(GPIO_2[1]),
- .ibar(gnd),
- .o(\GPIO_2[1]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[1]~input .bus_hold = "false";
-defparam \GPIO_2[1]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y24_N22
-cycloneive_io_ibuf \GPIO_2[2]~input (
- .i(GPIO_2[2]),
- .ibar(gnd),
- .o(\GPIO_2[2]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[2]~input .bus_hold = "false";
-defparam \GPIO_2[2]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y24_N15
-cycloneive_io_ibuf \GPIO_2[3]~input (
- .i(GPIO_2[3]),
- .ibar(gnd),
- .o(\GPIO_2[3]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[3]~input .bus_hold = "false";
-defparam \GPIO_2[3]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X5_Y0_N15
-cycloneive_io_ibuf \GPIO_2[4]~input (
- .i(GPIO_2[4]),
- .ibar(gnd),
- .o(\GPIO_2[4]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[4]~input .bus_hold = "false";
-defparam \GPIO_2[4]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y15_N1
-cycloneive_io_ibuf \GPIO_2[5]~input (
- .i(GPIO_2[5]),
- .ibar(gnd),
- .o(\GPIO_2[5]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[5]~input .bus_hold = "false";
-defparam \GPIO_2[5]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X3_Y34_N1
-cycloneive_io_ibuf \GPIO_2[6]~input (
- .i(GPIO_2[6]),
- .ibar(gnd),
- .o(\GPIO_2[6]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[6]~input .bus_hold = "false";
-defparam \GPIO_2[6]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X1_Y34_N8
-cycloneive_io_ibuf \GPIO_2[7]~input (
- .i(GPIO_2[7]),
- .ibar(gnd),
- .o(\GPIO_2[7]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[7]~input .bus_hold = "false";
-defparam \GPIO_2[7]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X11_Y0_N15
-cycloneive_io_ibuf \GPIO_2[8]~input (
- .i(GPIO_2[8]),
- .ibar(gnd),
- .o(\GPIO_2[8]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[8]~input .bus_hold = "false";
-defparam \GPIO_2[8]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X3_Y0_N1
-cycloneive_io_ibuf \GPIO_2[9]~input (
- .i(GPIO_2[9]),
- .ibar(gnd),
- .o(\GPIO_2[9]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[9]~input .bus_hold = "false";
-defparam \GPIO_2[9]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X43_Y34_N22
-cycloneive_io_ibuf \GPIO_2[10]~input (
- .i(GPIO_2[10]),
- .ibar(gnd),
- .o(\GPIO_2[10]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[10]~input .bus_hold = "false";
-defparam \GPIO_2[10]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X23_Y34_N15
-cycloneive_io_ibuf \GPIO_2[11]~input (
- .i(GPIO_2[11]),
- .ibar(gnd),
- .o(\GPIO_2[11]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[11]~input .bus_hold = "false";
-defparam \GPIO_2[11]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X20_Y34_N8
-cycloneive_io_ibuf \GPIO_2[12]~input (
- .i(GPIO_2[12]),
- .ibar(gnd),
- .o(\GPIO_2[12]~input_o ));
-// synopsys translate_off
-defparam \GPIO_2[12]~input .bus_hold = "false";
-defparam \GPIO_2[12]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X34_Y34_N8
-cycloneive_io_ibuf \GPIO_0_PI[0]~input (
- .i(GPIO_0_PI[0]),
- .ibar(gnd),
- .o(\GPIO_0_PI[0]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[0]~input .bus_hold = "false";
-defparam \GPIO_0_PI[0]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y4_N15
-cycloneive_io_ibuf \GPIO_0_PI[1]~input (
- .i(GPIO_0_PI[1]),
- .ibar(gnd),
- .o(\GPIO_0_PI[1]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[1]~input .bus_hold = "false";
-defparam \GPIO_0_PI[1]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y5_N22
-cycloneive_io_ibuf \GPIO_0_PI[2]~input (
- .i(GPIO_0_PI[2]),
- .ibar(gnd),
- .o(\GPIO_0_PI[2]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[2]~input .bus_hold = "false";
-defparam \GPIO_0_PI[2]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X18_Y34_N22
-cycloneive_io_ibuf \GPIO_0_PI[3]~input (
- .i(GPIO_0_PI[3]),
- .ibar(gnd),
- .o(\GPIO_0_PI[3]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[3]~input .bus_hold = "false";
-defparam \GPIO_0_PI[3]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X14_Y0_N15
-cycloneive_io_ibuf \GPIO_0_PI[4]~input (
- .i(GPIO_0_PI[4]),
- .ibar(gnd),
- .o(\GPIO_0_PI[4]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[4]~input .bus_hold = "false";
-defparam \GPIO_0_PI[4]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X14_Y34_N22
-cycloneive_io_ibuf \GPIO_0_PI[5]~input (
- .i(GPIO_0_PI[5]),
- .ibar(gnd),
- .o(\GPIO_0_PI[5]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[5]~input .bus_hold = "false";
-defparam \GPIO_0_PI[5]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y6_N15
-cycloneive_io_ibuf \GPIO_0_PI[6]~input (
- .i(GPIO_0_PI[6]),
- .ibar(gnd),
- .o(\GPIO_0_PI[6]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[6]~input .bus_hold = "false";
-defparam \GPIO_0_PI[6]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X14_Y0_N22
-cycloneive_io_ibuf \GPIO_0_PI[7]~input (
- .i(GPIO_0_PI[7]),
- .ibar(gnd),
- .o(\GPIO_0_PI[7]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[7]~input .bus_hold = "false";
-defparam \GPIO_0_PI[7]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y4_N22
-cycloneive_io_ibuf \GPIO_0_PI[12]~input (
- .i(GPIO_0_PI[12]),
- .ibar(gnd),
- .o(\GPIO_0_PI[12]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[12]~input .bus_hold = "false";
-defparam \GPIO_0_PI[12]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y8_N22
-cycloneive_io_ibuf \GPIO_0_PI[13]~input (
- .i(GPIO_0_PI[13]),
- .ibar(gnd),
- .o(\GPIO_0_PI[13]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[13]~input .bus_hold = "false";
-defparam \GPIO_0_PI[13]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X1_Y34_N1
-cycloneive_io_ibuf \GPIO_0_PI[14]~input (
- .i(GPIO_0_PI[14]),
- .ibar(gnd),
- .o(\GPIO_0_PI[14]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[14]~input .bus_hold = "false";
-defparam \GPIO_0_PI[14]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X34_Y34_N15
-cycloneive_io_ibuf \GPIO_0_PI[15]~input (
- .i(GPIO_0_PI[15]),
- .ibar(gnd),
- .o(\GPIO_0_PI[15]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[15]~input .bus_hold = "false";
-defparam \GPIO_0_PI[15]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X34_Y34_N1
-cycloneive_io_ibuf \GPIO_0_PI[16]~input (
- .i(GPIO_0_PI[16]),
- .ibar(gnd),
- .o(\GPIO_0_PI[16]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[16]~input .bus_hold = "false";
-defparam \GPIO_0_PI[16]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X16_Y34_N8
-cycloneive_io_ibuf \GPIO_0_PI[17]~input (
- .i(GPIO_0_PI[17]),
- .ibar(gnd),
- .o(\GPIO_0_PI[17]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[17]~input .bus_hold = "false";
-defparam \GPIO_0_PI[17]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X1_Y0_N8
-cycloneive_io_ibuf \GPIO_0_PI[18]~input (
- .i(GPIO_0_PI[18]),
- .ibar(gnd),
- .o(\GPIO_0_PI[18]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[18]~input .bus_hold = "false";
-defparam \GPIO_0_PI[18]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X36_Y0_N8
-cycloneive_io_ibuf \GPIO_0_PI[19]~input (
- .i(GPIO_0_PI[19]),
- .ibar(gnd),
- .o(\GPIO_0_PI[19]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[19]~input .bus_hold = "false";
-defparam \GPIO_0_PI[19]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y15_N8
-cycloneive_io_ibuf \GPIO_0_PI[20]~input (
- .i(GPIO_0_PI[20]),
- .ibar(gnd),
- .o(\GPIO_0_PI[20]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[20]~input .bus_hold = "false";
-defparam \GPIO_0_PI[20]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X47_Y34_N22
-cycloneive_io_ibuf \GPIO_0_PI[21]~input (
- .i(GPIO_0_PI[21]),
- .ibar(gnd),
- .o(\GPIO_0_PI[21]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[21]~input .bus_hold = "false";
-defparam \GPIO_0_PI[21]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X14_Y0_N8
-cycloneive_io_ibuf \GPIO_0_PI[22]~input (
- .i(GPIO_0_PI[22]),
- .ibar(gnd),
- .o(\GPIO_0_PI[22]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[22]~input .bus_hold = "false";
-defparam \GPIO_0_PI[22]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X20_Y34_N22
-cycloneive_io_ibuf \GPIO_0_PI[23]~input (
- .i(GPIO_0_PI[23]),
- .ibar(gnd),
- .o(\GPIO_0_PI[23]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[23]~input .bus_hold = "false";
-defparam \GPIO_0_PI[23]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X45_Y34_N1
-cycloneive_io_ibuf \GPIO_0_PI[24]~input (
- .i(GPIO_0_PI[24]),
- .ibar(gnd),
- .o(\GPIO_0_PI[24]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[24]~input .bus_hold = "false";
-defparam \GPIO_0_PI[24]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X40_Y0_N22
-cycloneive_io_ibuf \GPIO_0_PI[25]~input (
- .i(GPIO_0_PI[25]),
- .ibar(gnd),
- .o(\GPIO_0_PI[25]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[25]~input .bus_hold = "false";
-defparam \GPIO_0_PI[25]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X18_Y0_N8
-cycloneive_io_ibuf \GPIO_0_PI[26]~input (
- .i(GPIO_0_PI[26]),
- .ibar(gnd),
- .o(\GPIO_0_PI[26]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[26]~input .bus_hold = "false";
-defparam \GPIO_0_PI[26]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X45_Y34_N15
-cycloneive_io_ibuf \GPIO_0_PI[27]~input (
- .i(GPIO_0_PI[27]),
- .ibar(gnd),
- .o(\GPIO_0_PI[27]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[27]~input .bus_hold = "false";
-defparam \GPIO_0_PI[27]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X38_Y34_N1
-cycloneive_io_ibuf \GPIO_0_PI[28]~input (
- .i(GPIO_0_PI[28]),
- .ibar(gnd),
- .o(\GPIO_0_PI[28]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[28]~input .bus_hold = "false";
-defparam \GPIO_0_PI[28]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X40_Y34_N8
-cycloneive_io_ibuf \GPIO_0_PI[29]~input (
- .i(GPIO_0_PI[29]),
- .ibar(gnd),
- .o(\GPIO_0_PI[29]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[29]~input .bus_hold = "false";
-defparam \GPIO_0_PI[29]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X18_Y34_N1
-cycloneive_io_ibuf \GPIO_0_PI[30]~input (
- .i(GPIO_0_PI[30]),
- .ibar(gnd),
- .o(\GPIO_0_PI[30]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[30]~input .bus_hold = "false";
-defparam \GPIO_0_PI[30]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X23_Y34_N22
-cycloneive_io_ibuf \GPIO_0_PI[32]~input (
- .i(GPIO_0_PI[32]),
- .ibar(gnd),
- .o(\GPIO_0_PI[32]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[32]~input .bus_hold = "false";
-defparam \GPIO_0_PI[32]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y22_N1
-cycloneive_io_ibuf \GPIO_0_PI[33]~input (
- .i(GPIO_0_PI[33]),
- .ibar(gnd),
- .o(\GPIO_0_PI[33]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[33]~input .bus_hold = "false";
-defparam \GPIO_0_PI[33]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X14_Y0_N1
-cycloneive_io_ibuf \GPIO_1[0]~input (
- .i(GPIO_1[0]),
- .ibar(gnd),
- .o(\GPIO_1[0]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[0]~input .bus_hold = "false";
-defparam \GPIO_1[0]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X1_Y0_N22
-cycloneive_io_ibuf \GPIO_1[1]~input (
- .i(GPIO_1[1]),
- .ibar(gnd),
- .o(\GPIO_1[1]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[1]~input .bus_hold = "false";
-defparam \GPIO_1[1]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y20_N22
-cycloneive_io_ibuf \GPIO_1[2]~input (
- .i(GPIO_1[2]),
- .ibar(gnd),
- .o(\GPIO_1[2]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[2]~input .bus_hold = "false";
-defparam \GPIO_1[2]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y23_N1
-cycloneive_io_ibuf \GPIO_1[3]~input (
- .i(GPIO_1[3]),
- .ibar(gnd),
- .o(\GPIO_1[3]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[3]~input .bus_hold = "false";
-defparam \GPIO_1[3]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X7_Y34_N1
-cycloneive_io_ibuf \GPIO_1[4]~input (
- .i(GPIO_1[4]),
- .ibar(gnd),
- .o(\GPIO_1[4]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[4]~input .bus_hold = "false";
-defparam \GPIO_1[4]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y11_N1
-cycloneive_io_ibuf \GPIO_1[5]~input (
- .i(GPIO_1[5]),
- .ibar(gnd),
- .o(\GPIO_1[5]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[5]~input .bus_hold = "false";
-defparam \GPIO_1[5]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X51_Y34_N8
-cycloneive_io_ibuf \GPIO_1[6]~input (
- .i(GPIO_1[6]),
- .ibar(gnd),
- .o(\GPIO_1[6]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[6]~input .bus_hold = "false";
-defparam \GPIO_1[6]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X5_Y0_N8
-cycloneive_io_ibuf \GPIO_1[7]~input (
- .i(GPIO_1[7]),
- .ibar(gnd),
- .o(\GPIO_1[7]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[7]~input .bus_hold = "false";
-defparam \GPIO_1[7]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y22_N8
-cycloneive_io_ibuf \GPIO_1[8]~input (
- .i(GPIO_1[8]),
- .ibar(gnd),
- .o(\GPIO_1[8]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[8]~input .bus_hold = "false";
-defparam \GPIO_1[8]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X34_Y0_N1
-cycloneive_io_ibuf \GPIO_1[9]~input (
- .i(GPIO_1[9]),
- .ibar(gnd),
- .o(\GPIO_1[9]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[9]~input .bus_hold = "false";
-defparam \GPIO_1[9]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y11_N8
-cycloneive_io_ibuf \GPIO_1[10]~input (
- .i(GPIO_1[10]),
- .ibar(gnd),
- .o(\GPIO_1[10]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[10]~input .bus_hold = "false";
-defparam \GPIO_1[10]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X45_Y34_N8
-cycloneive_io_ibuf \GPIO_1[11]~input (
- .i(GPIO_1[11]),
- .ibar(gnd),
- .o(\GPIO_1[11]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[11]~input .bus_hold = "false";
-defparam \GPIO_1[11]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y26_N22
-cycloneive_io_ibuf \GPIO_1[12]~input (
- .i(GPIO_1[12]),
- .ibar(gnd),
- .o(\GPIO_1[12]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[12]~input .bus_hold = "false";
-defparam \GPIO_1[12]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X40_Y0_N15
-cycloneive_io_ibuf \GPIO_1[13]~input (
- .i(GPIO_1[13]),
- .ibar(gnd),
- .o(\GPIO_1[13]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[13]~input .bus_hold = "false";
-defparam \GPIO_1[13]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y12_N1
-cycloneive_io_ibuf \GPIO_1[14]~input (
- .i(GPIO_1[14]),
- .ibar(gnd),
- .o(\GPIO_1[14]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[14]~input .bus_hold = "false";
-defparam \GPIO_1[14]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y30_N1
-cycloneive_io_ibuf \GPIO_1[15]~input (
- .i(GPIO_1[15]),
- .ibar(gnd),
- .o(\GPIO_1[15]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[15]~input .bus_hold = "false";
-defparam \GPIO_1[15]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X25_Y0_N15
-cycloneive_io_ibuf \GPIO_1[16]~input (
- .i(GPIO_1[16]),
- .ibar(gnd),
- .o(\GPIO_1[16]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[16]~input .bus_hold = "false";
-defparam \GPIO_1[16]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X34_Y0_N22
-cycloneive_io_ibuf \GPIO_1[17]~input (
- .i(GPIO_1[17]),
- .ibar(gnd),
- .o(\GPIO_1[17]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[17]~input .bus_hold = "false";
-defparam \GPIO_1[17]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y7_N1
-cycloneive_io_ibuf \GPIO_1[18]~input (
- .i(GPIO_1[18]),
- .ibar(gnd),
- .o(\GPIO_1[18]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[18]~input .bus_hold = "false";
-defparam \GPIO_1[18]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y30_N8
-cycloneive_io_ibuf \GPIO_1[19]~input (
- .i(GPIO_1[19]),
- .ibar(gnd),
- .o(\GPIO_1[19]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[19]~input .bus_hold = "false";
-defparam \GPIO_1[19]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y27_N1
-cycloneive_io_ibuf \GPIO_1[20]~input (
- .i(GPIO_1[20]),
- .ibar(gnd),
- .o(\GPIO_1[20]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[20]~input .bus_hold = "false";
-defparam \GPIO_1[20]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X47_Y0_N22
-cycloneive_io_ibuf \GPIO_1[21]~input (
- .i(GPIO_1[21]),
- .ibar(gnd),
- .o(\GPIO_1[21]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[21]~input .bus_hold = "false";
-defparam \GPIO_1[21]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X11_Y34_N1
-cycloneive_io_ibuf \GPIO_1[22]~input (
- .i(GPIO_1[22]),
- .ibar(gnd),
- .o(\GPIO_1[22]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[22]~input .bus_hold = "false";
-defparam \GPIO_1[22]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X20_Y0_N8
-cycloneive_io_ibuf \GPIO_1[23]~input (
- .i(GPIO_1[23]),
- .ibar(gnd),
- .o(\GPIO_1[23]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[23]~input .bus_hold = "false";
-defparam \GPIO_1[23]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X5_Y0_N1
-cycloneive_io_ibuf \GPIO_1[24]~input (
- .i(GPIO_1[24]),
- .ibar(gnd),
- .o(\GPIO_1[24]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[24]~input .bus_hold = "false";
-defparam \GPIO_1[24]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y21_N22
-cycloneive_io_ibuf \GPIO_1[25]~input (
- .i(GPIO_1[25]),
- .ibar(gnd),
- .o(\GPIO_1[25]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[25]~input .bus_hold = "false";
-defparam \GPIO_1[25]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X1_Y0_N15
-cycloneive_io_ibuf \GPIO_1[26]~input (
- .i(GPIO_1[26]),
- .ibar(gnd),
- .o(\GPIO_1[26]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[26]~input .bus_hold = "false";
-defparam \GPIO_1[26]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X7_Y0_N8
-cycloneive_io_ibuf \GPIO_1[27]~input (
- .i(GPIO_1[27]),
- .ibar(gnd),
- .o(\GPIO_1[27]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[27]~input .bus_hold = "false";
-defparam \GPIO_1[27]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y23_N22
-cycloneive_io_ibuf \GPIO_1[28]~input (
- .i(GPIO_1[28]),
- .ibar(gnd),
- .o(\GPIO_1[28]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[28]~input .bus_hold = "false";
-defparam \GPIO_1[28]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X53_Y14_N8
-cycloneive_io_ibuf \GPIO_1[29]~input (
- .i(GPIO_1[29]),
- .ibar(gnd),
- .o(\GPIO_1[29]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[29]~input .bus_hold = "false";
-defparam \GPIO_1[29]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X45_Y0_N22
-cycloneive_io_ibuf \GPIO_1[30]~input (
- .i(GPIO_1[30]),
- .ibar(gnd),
- .o(\GPIO_1[30]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[30]~input .bus_hold = "false";
-defparam \GPIO_1[30]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X49_Y0_N1
-cycloneive_io_ibuf \GPIO_1[31]~input (
- .i(GPIO_1[31]),
- .ibar(gnd),
- .o(\GPIO_1[31]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[31]~input .bus_hold = "false";
-defparam \GPIO_1[31]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X31_Y34_N1
-cycloneive_io_ibuf \GPIO_1[32]~input (
- .i(GPIO_1[32]),
- .ibar(gnd),
- .o(\GPIO_1[32]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[32]~input .bus_hold = "false";
-defparam \GPIO_1[32]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X0_Y6_N15
-cycloneive_io_ibuf \GPIO_1[33]~input (
- .i(GPIO_1[33]),
- .ibar(gnd),
- .o(\GPIO_1[33]~input_o ));
-// synopsys translate_off
-defparam \GPIO_1[33]~input .bus_hold = "false";
-defparam \GPIO_1[33]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-// Location: IOIBUF_X16_Y34_N1
-cycloneive_io_ibuf \GPIO_0_PI[11]~input (
- .i(GPIO_0_PI[11]),
- .ibar(gnd),
- .o(\GPIO_0_PI[11]~input_o ));
-// synopsys translate_off
-defparam \GPIO_0_PI[11]~input .bus_hold = "false";
-defparam \GPIO_0_PI[11]~input .simulate_z_as = "z";
-// synopsys translate_on
-
-assign LED[0] = \LED[0]~output_o ;
-
-assign LED[1] = \LED[1]~output_o ;
-
-assign LED[2] = \LED[2]~output_o ;
-
-assign LED[3] = \LED[3]~output_o ;
-
-assign LED[4] = \LED[4]~output_o ;
-
-assign LED[5] = \LED[5]~output_o ;
-
-assign LED[6] = \LED[6]~output_o ;
-
-assign LED[7] = \LED[7]~output_o ;
-
-assign GPIO_2[0] = \GPIO_2[0]~output_o ;
-
-assign GPIO_2[1] = \GPIO_2[1]~output_o ;
-
-assign GPIO_2[2] = \GPIO_2[2]~output_o ;
-
-assign GPIO_2[3] = \GPIO_2[3]~output_o ;
-
-assign GPIO_2[4] = \GPIO_2[4]~output_o ;
-
-assign GPIO_2[5] = \GPIO_2[5]~output_o ;
-
-assign GPIO_2[6] = \GPIO_2[6]~output_o ;
-
-assign GPIO_2[7] = \GPIO_2[7]~output_o ;
-
-assign GPIO_2[8] = \GPIO_2[8]~output_o ;
-
-assign GPIO_2[9] = \GPIO_2[9]~output_o ;
-
-assign GPIO_2[10] = \GPIO_2[10]~output_o ;
-
-assign GPIO_2[11] = \GPIO_2[11]~output_o ;
-
-assign GPIO_2[12] = \GPIO_2[12]~output_o ;
-
-assign GPIO_0_PI[0] = \GPIO_0_PI[0]~output_o ;
-
-assign GPIO_0_PI[1] = \GPIO_0_PI[1]~output_o ;
-
-assign GPIO_0_PI[2] = \GPIO_0_PI[2]~output_o ;
-
-assign GPIO_0_PI[3] = \GPIO_0_PI[3]~output_o ;
-
-assign GPIO_0_PI[4] = \GPIO_0_PI[4]~output_o ;
-
-assign GPIO_0_PI[5] = \GPIO_0_PI[5]~output_o ;
-
-assign GPIO_0_PI[6] = \GPIO_0_PI[6]~output_o ;
-
-assign GPIO_0_PI[7] = \GPIO_0_PI[7]~output_o ;
-
-assign GPIO_0_PI[12] = \GPIO_0_PI[12]~output_o ;
-
-assign GPIO_0_PI[13] = \GPIO_0_PI[13]~output_o ;
-
-assign GPIO_0_PI[14] = \GPIO_0_PI[14]~output_o ;
-
-assign GPIO_0_PI[15] = \GPIO_0_PI[15]~output_o ;
-
-assign GPIO_0_PI[16] = \GPIO_0_PI[16]~output_o ;
-
-assign GPIO_0_PI[17] = \GPIO_0_PI[17]~output_o ;
-
-assign GPIO_0_PI[18] = \GPIO_0_PI[18]~output_o ;
-
-assign GPIO_0_PI[19] = \GPIO_0_PI[19]~output_o ;
-
-assign GPIO_0_PI[20] = \GPIO_0_PI[20]~output_o ;
-
-assign GPIO_0_PI[21] = \GPIO_0_PI[21]~output_o ;
-
-assign GPIO_0_PI[22] = \GPIO_0_PI[22]~output_o ;
-
-assign GPIO_0_PI[23] = \GPIO_0_PI[23]~output_o ;
-
-assign GPIO_0_PI[24] = \GPIO_0_PI[24]~output_o ;
-
-assign GPIO_0_PI[25] = \GPIO_0_PI[25]~output_o ;
-
-assign GPIO_0_PI[26] = \GPIO_0_PI[26]~output_o ;
-
-assign GPIO_0_PI[27] = \GPIO_0_PI[27]~output_o ;
-
-assign GPIO_0_PI[28] = \GPIO_0_PI[28]~output_o ;
-
-assign GPIO_0_PI[29] = \GPIO_0_PI[29]~output_o ;
-
-assign GPIO_0_PI[30] = \GPIO_0_PI[30]~output_o ;
-
-assign GPIO_0_PI[32] = \GPIO_0_PI[32]~output_o ;
-
-assign GPIO_0_PI[33] = \GPIO_0_PI[33]~output_o ;
-
-assign GPIO_1[0] = \GPIO_1[0]~output_o ;
-
-assign GPIO_1[1] = \GPIO_1[1]~output_o ;
-
-assign GPIO_1[2] = \GPIO_1[2]~output_o ;
-
-assign GPIO_1[3] = \GPIO_1[3]~output_o ;
-
-assign GPIO_1[4] = \GPIO_1[4]~output_o ;
-
-assign GPIO_1[5] = \GPIO_1[5]~output_o ;
-
-assign GPIO_1[6] = \GPIO_1[6]~output_o ;
-
-assign GPIO_1[7] = \GPIO_1[7]~output_o ;
-
-assign GPIO_1[8] = \GPIO_1[8]~output_o ;
-
-assign GPIO_1[9] = \GPIO_1[9]~output_o ;
-
-assign GPIO_1[10] = \GPIO_1[10]~output_o ;
-
-assign GPIO_1[11] = \GPIO_1[11]~output_o ;
-
-assign GPIO_1[12] = \GPIO_1[12]~output_o ;
-
-assign GPIO_1[13] = \GPIO_1[13]~output_o ;
-
-assign GPIO_1[14] = \GPIO_1[14]~output_o ;
-
-assign GPIO_1[15] = \GPIO_1[15]~output_o ;
-
-assign GPIO_1[16] = \GPIO_1[16]~output_o ;
-
-assign GPIO_1[17] = \GPIO_1[17]~output_o ;
-
-assign GPIO_1[18] = \GPIO_1[18]~output_o ;
-
-assign GPIO_1[19] = \GPIO_1[19]~output_o ;
-
-assign GPIO_1[20] = \GPIO_1[20]~output_o ;
-
-assign GPIO_1[21] = \GPIO_1[21]~output_o ;
-
-assign GPIO_1[22] = \GPIO_1[22]~output_o ;
-
-assign GPIO_1[23] = \GPIO_1[23]~output_o ;
-
-assign GPIO_1[24] = \GPIO_1[24]~output_o ;
-
-assign GPIO_1[25] = \GPIO_1[25]~output_o ;
-
-assign GPIO_1[26] = \GPIO_1[26]~output_o ;
-
-assign GPIO_1[27] = \GPIO_1[27]~output_o ;
-
-assign GPIO_1[28] = \GPIO_1[28]~output_o ;
-
-assign GPIO_1[29] = \GPIO_1[29]~output_o ;
-
-assign GPIO_1[30] = \GPIO_1[30]~output_o ;
-
-assign GPIO_1[31] = \GPIO_1[31]~output_o ;
-
-assign GPIO_1[32] = \GPIO_1[32]~output_o ;
-
-assign GPIO_1[33] = \GPIO_1[33]~output_o ;
-
-assign GPIO_0_PI[8] = \GPIO_0_PI[8]~output_o ;
-
-assign GPIO_0_PI[9] = \GPIO_0_PI[9]~output_o ;
-
-assign GPIO_0_PI[10] = \GPIO_0_PI[10]~output_o ;
-
-assign GPIO_0_PI[11] = \GPIO_0_PI[11]~output_o ;
-
-assign GPIO_0_PI[31] = \GPIO_0_PI[31]~output_o ;
-
-endmodule
-
-module hard_block (
-
- devpor,
- devclrn,
- devoe);
-
-// Design Ports Information
-// ~ALTERA_ASDO_DATA1~ => Location: PIN_C1, I/O Standard: 2.5 V, Current Strength: Default
-// ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_D2, I/O Standard: 2.5 V, Current Strength: Default
-// ~ALTERA_DCLK~ => Location: PIN_H1, I/O Standard: 2.5 V, Current Strength: Default
-// ~ALTERA_DATA0~ => Location: PIN_H2, I/O Standard: 2.5 V, Current Strength: Default
-// ~ALTERA_nCEO~ => Location: PIN_F16, I/O Standard: 2.5 V, Current Strength: 8mA
-
-input devpor;
-input devclrn;
-input devoe;
-
-wire gnd;
-wire vcc;
-wire unknown;
-
-assign gnd = 1'b0;
-assign vcc = 1'b1;
-assign unknown = 1'bx;
-
-wire \~ALTERA_ASDO_DATA1~~padout ;
-wire \~ALTERA_FLASH_nCE_nCSO~~padout ;
-wire \~ALTERA_DATA0~~padout ;
-wire \~ALTERA_ASDO_DATA1~~ibuf_o ;
-wire \~ALTERA_FLASH_nCE_nCSO~~ibuf_o ;
-wire \~ALTERA_DATA0~~ibuf_o ;
-
-
-endmodule
diff --git a/SPI/simulation/modelsim/SPI_test_min_1200mv_0c_v_fast.sdo b/SPI/simulation/modelsim/SPI_test_min_1200mv_0c_v_fast.sdo
deleted file mode 100644
index eb3f1c06c7f01da1b14578cf69c000eef33bea57..0000000000000000000000000000000000000000
--- a/SPI/simulation/modelsim/SPI_test_min_1200mv_0c_v_fast.sdo
+++ /dev/null
@@ -1,1172 +0,0 @@
-// Copyright (C) 2018 Intel Corporation. All rights reserved.
-// Your use of Intel Corporation's design tools, logic functions
-// and other software and tools, and its AMPP partner logic
-// functions, and any output files from any of the foregoing
-// (including device programming or simulation files), and any
-// associated documentation or information are expressly subject
-// to the terms and conditions of the Intel Program License
-// Subscription Agreement, the Intel Quartus Prime License Agreement,
-// the Intel FPGA IP License Agreement, or other applicable license
-// agreement, including, without limitation, that your use is for
-// the sole purpose of programming logic devices manufactured by
-// Intel and sold by Intel or its authorized distributors. Please
-// refer to the applicable agreement for further details.
-
-
-//
-// Device: Altera EP4CE22F17C6 Package FBGA256
-//
-
-//
-// This file contains Fast Corner delays for the design using part EP4CE22F17C6,
-// with speed grade M, core voltage 1.2VmV, and temperature 0 Celsius
-//
-
-//
-// This SDF file should be used for ModelSim-Altera (SystemVerilog) only
-//
-
-(DELAYFILE
- (SDFVERSION "2.1")
- (DESIGN "MyDE0_Nano")
- (DATE "11/16/2022 16:51:48")
- (VENDOR "Altera")
- (PROGRAM "Quartus Prime")
- (VERSION "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition")
- (DIVIDER .)
- (TIMESCALE 1 ps)
-
- (CELL
- (CELLTYPE "cycloneive_io_obuf")
- (INSTANCE GPIO_0_PI\[11\]\~output)
- (DELAY
- (ABSOLUTE
- (PORT i (363:363:363) (400:400:400))
- (PORT oe (1826:1826:1826) (1642:1642:1642))
- (IOPATH i o (1593:1593:1593) (1596:1596:1596))
- (IOPATH oe o (1586:1586:1586) (1572:1572:1572))
- )
- )
- )
- (CELL
- (CELLTYPE "cycloneive_io_ibuf")
- (INSTANCE GPIO_0_PI\[8\]\~input)
- (DELAY
- (ABSOLUTE
- (IOPATH i o (238:238:238) (618:618:618))
- )
- )
- )
- (CELL
- (CELLTYPE "cycloneive_clkctrl")
- (INSTANCE GPIO_0_PI\[8\]\~inputclkctrl)
- (DELAY
- (ABSOLUTE
- (IOPATH inclk outclk (129:129:129) (119:119:119))
- )
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|cnt\[0\]\~12)
- (DELAY
- (ABSOLUTE
- (IOPATH datac combout (190:190:190) (195:195:195))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|cnt\[0\])
- (DELAY
- (ABSOLUTE
- (PORT clk (932:932:932) (918:918:918))
- (PORT d (37:37:37) (50:50:50))
- (IOPATH (posedge clk) q (105:105:105) (105:105:105))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (84:84:84))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|cnt\[1\]\~4)
- (DELAY
- (ABSOLUTE
- (PORT dataa (148:148:148) (201:201:201))
- (PORT datab (146:146:146) (196:196:196))
- (IOPATH dataa combout (186:186:186) (180:180:180))
- (IOPATH dataa cout (226:226:226) (171:171:171))
- (IOPATH datab combout (190:190:190) (181:181:181))
- (IOPATH datab cout (227:227:227) (175:175:175))
- (IOPATH datad combout (68:68:68) (63:63:63))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|cnt\[1\])
- (DELAY
- (ABSOLUTE
- (PORT clk (932:932:932) (918:918:918))
- (PORT d (37:37:37) (50:50:50))
- (IOPATH (posedge clk) q (105:105:105) (105:105:105))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (84:84:84))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|cnt\[2\]\~6)
- (DELAY
- (ABSOLUTE
- (PORT datab (216:216:216) (273:273:273))
- (IOPATH datab combout (166:166:166) (176:176:176))
- (IOPATH datab cout (227:227:227) (175:175:175))
- (IOPATH datad combout (68:68:68) (63:63:63))
- (IOPATH cin combout (187:187:187) (204:204:204))
- (IOPATH cin cout (34:34:34) (34:34:34))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|cnt\[2\])
- (DELAY
- (ABSOLUTE
- (PORT clk (932:932:932) (918:918:918))
- (PORT d (37:37:37) (50:50:50))
- (IOPATH (posedge clk) q (105:105:105) (105:105:105))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (84:84:84))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|cnt\[3\]\~8)
- (DELAY
- (ABSOLUTE
- (PORT dataa (147:147:147) (199:199:199))
- (IOPATH dataa combout (186:186:186) (175:175:175))
- (IOPATH dataa cout (226:226:226) (171:171:171))
- (IOPATH datad combout (68:68:68) (63:63:63))
- (IOPATH cin combout (187:187:187) (204:204:204))
- (IOPATH cin cout (34:34:34) (34:34:34))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|cnt\[3\])
- (DELAY
- (ABSOLUTE
- (PORT clk (932:932:932) (918:918:918))
- (PORT d (37:37:37) (50:50:50))
- (IOPATH (posedge clk) q (105:105:105) (105:105:105))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (84:84:84))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|cnt\[4\]\~10)
- (DELAY
- (ABSOLUTE
- (PORT datab (202:202:202) (269:269:269))
- (IOPATH datab combout (196:196:196) (205:205:205))
- (IOPATH cin combout (187:187:187) (204:204:204))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|cnt\[4\])
- (DELAY
- (ABSOLUTE
- (PORT clk (932:932:932) (918:918:918))
- (PORT d (37:37:37) (50:50:50))
- (IOPATH (posedge clk) q (105:105:105) (105:105:105))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (84:84:84))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_io_ibuf")
- (INSTANCE GPIO_0_PI\[31\]\~input)
- (DELAY
- (ABSOLUTE
- (IOPATH i o (238:238:238) (617:617:617))
- )
- )
- )
- (CELL
- (CELLTYPE "cycloneive_io_ibuf")
- (INSTANCE GPIO_0_PI\[9\]\~input)
- (DELAY
- (ABSOLUTE
- (IOPATH i o (238:238:238) (617:617:617))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[0\])
- (DELAY
- (ABSOLUTE
- (PORT clk (923:923:923) (928:928:928))
- (PORT asdata (2123:2123:2123) (2380:2380:2380))
- (IOPATH (posedge clk) q (105:105:105) (105:105:105))
- )
- )
- (TIMINGCHECK
- (HOLD asdata (posedge clk) (84:84:84))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|Equal0\~0)
- (DELAY
- (ABSOLUTE
- (PORT dataa (147:147:147) (201:201:201))
- (PORT datab (148:148:148) (198:198:198))
- (PORT datac (129:129:129) (170:170:170))
- (PORT datad (135:135:135) (174:174:174))
- (IOPATH dataa combout (158:158:158) (157:157:157))
- (IOPATH datab combout (160:160:160) (156:156:156))
- (IOPATH datac combout (120:120:120) (124:124:124))
- (IOPATH datad combout (68:68:68) (63:63:63))
- )
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~31)
- (DELAY
- (ABSOLUTE
- (PORT dataa (268:268:268) (336:336:336))
- (PORT datab (2094:2094:2094) (2392:2392:2392))
- (PORT datac (119:119:119) (160:160:160))
- (PORT datad (216:216:216) (248:248:248))
- (IOPATH dataa combout (166:166:166) (157:157:157))
- (IOPATH datab combout (167:167:167) (158:158:158))
- (IOPATH datac combout (119:119:119) (124:124:124))
- (IOPATH datad combout (68:68:68) (63:63:63))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[1\])
- (DELAY
- (ABSOLUTE
- (PORT clk (923:923:923) (928:928:928))
- (PORT d (37:37:37) (50:50:50))
- (IOPATH (posedge clk) q (105:105:105) (105:105:105))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (84:84:84))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~30)
- (DELAY
- (ABSOLUTE
- (PORT dataa (269:269:269) (337:337:337))
- (PORT datac (117:117:117) (157:157:157))
- (PORT datad (216:216:216) (248:248:248))
- (IOPATH dataa combout (166:166:166) (163:163:163))
- (IOPATH datac combout (119:119:119) (124:124:124))
- (IOPATH datad combout (68:68:68) (63:63:63))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[2\])
- (DELAY
- (ABSOLUTE
- (PORT clk (923:923:923) (928:928:928))
- (PORT d (37:37:37) (50:50:50))
- (IOPATH (posedge clk) q (105:105:105) (105:105:105))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (84:84:84))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~29)
- (DELAY
- (ABSOLUTE
- (PORT dataa (271:271:271) (339:339:339))
- (PORT datab (130:130:130) (178:178:178))
- (PORT datad (215:215:215) (248:248:248))
- (IOPATH dataa combout (159:159:159) (163:163:163))
- (IOPATH datab combout (168:168:168) (167:167:167))
- (IOPATH datad combout (68:68:68) (63:63:63))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[3\])
- (DELAY
- (ABSOLUTE
- (PORT clk (923:923:923) (928:928:928))
- (PORT d (37:37:37) (50:50:50))
- (IOPATH (posedge clk) q (105:105:105) (105:105:105))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (84:84:84))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~28)
- (DELAY
- (ABSOLUTE
- (PORT dataa (263:263:263) (330:330:330))
- (PORT datac (119:119:119) (161:161:161))
- (PORT datad (216:216:216) (248:248:248))
- (IOPATH dataa combout (166:166:166) (163:163:163))
- (IOPATH datac combout (119:119:119) (124:124:124))
- (IOPATH datad combout (68:68:68) (63:63:63))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[4\])
- (DELAY
- (ABSOLUTE
- (PORT clk (923:923:923) (928:928:928))
- (PORT d (37:37:37) (50:50:50))
- (IOPATH (posedge clk) q (105:105:105) (105:105:105))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (84:84:84))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~27)
- (DELAY
- (ABSOLUTE
- (PORT dataa (267:267:267) (335:335:335))
- (PORT datac (118:118:118) (159:159:159))
- (PORT datad (216:216:216) (248:248:248))
- (IOPATH dataa combout (166:166:166) (163:163:163))
- (IOPATH datac combout (119:119:119) (124:124:124))
- (IOPATH datad combout (68:68:68) (63:63:63))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[5\])
- (DELAY
- (ABSOLUTE
- (PORT clk (923:923:923) (928:928:928))
- (PORT d (37:37:37) (50:50:50))
- (IOPATH (posedge clk) q (105:105:105) (105:105:105))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (84:84:84))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~26)
- (DELAY
- (ABSOLUTE
- (PORT dataa (270:270:270) (338:338:338))
- (PORT datab (131:131:131) (179:179:179))
- (PORT datad (215:215:215) (248:248:248))
- (IOPATH dataa combout (159:159:159) (163:163:163))
- (IOPATH datab combout (168:168:168) (167:167:167))
- (IOPATH datad combout (68:68:68) (63:63:63))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[6\])
- (DELAY
- (ABSOLUTE
- (PORT clk (923:923:923) (928:928:928))
- (PORT d (37:37:37) (50:50:50))
- (IOPATH (posedge clk) q (105:105:105) (105:105:105))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (84:84:84))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~25)
- (DELAY
- (ABSOLUTE
- (PORT dataa (264:264:264) (331:331:331))
- (PORT datab (132:132:132) (182:182:182))
- (PORT datad (216:216:216) (248:248:248))
- (IOPATH dataa combout (159:159:159) (163:163:163))
- (IOPATH datab combout (168:168:168) (167:167:167))
- (IOPATH datad combout (68:68:68) (63:63:63))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[7\])
- (DELAY
- (ABSOLUTE
- (PORT clk (923:923:923) (928:928:928))
- (PORT d (37:37:37) (50:50:50))
- (IOPATH (posedge clk) q (105:105:105) (105:105:105))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (84:84:84))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~24)
- (DELAY
- (ABSOLUTE
- (PORT datab (204:204:204) (273:273:273))
- (PORT datac (188:188:188) (240:240:240))
- (PORT datad (152:152:152) (185:185:185))
- (IOPATH datab combout (167:167:167) (167:167:167))
- (IOPATH datac combout (119:119:119) (124:124:124))
- (IOPATH datad combout (68:68:68) (63:63:63))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[8\])
- (DELAY
- (ABSOLUTE
- (PORT clk (922:922:922) (928:928:928))
- (PORT d (37:37:37) (50:50:50))
- (IOPATH (posedge clk) q (105:105:105) (105:105:105))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (84:84:84))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~23)
- (DELAY
- (ABSOLUTE
- (PORT datab (132:132:132) (180:180:180))
- (PORT datac (191:191:191) (254:254:254))
- (PORT datad (153:153:153) (185:185:185))
- (IOPATH datab combout (168:168:168) (167:167:167))
- (IOPATH datac combout (119:119:119) (124:124:124))
- (IOPATH datad combout (68:68:68) (63:63:63))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[9\])
- (DELAY
- (ABSOLUTE
- (PORT clk (922:922:922) (928:928:928))
- (PORT d (37:37:37) (50:50:50))
- (IOPATH (posedge clk) q (105:105:105) (105:105:105))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (84:84:84))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~22)
- (DELAY
- (ABSOLUTE
- (PORT datab (129:129:129) (178:178:178))
- (PORT datac (192:192:192) (254:254:254))
- (PORT datad (154:154:154) (185:185:185))
- (IOPATH datab combout (168:168:168) (167:167:167))
- (IOPATH datac combout (119:119:119) (124:124:124))
- (IOPATH datad combout (68:68:68) (63:63:63))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[10\])
- (DELAY
- (ABSOLUTE
- (PORT clk (922:922:922) (928:928:928))
- (PORT d (37:37:37) (50:50:50))
- (IOPATH (posedge clk) q (105:105:105) (105:105:105))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (84:84:84))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~21)
- (DELAY
- (ABSOLUTE
- (PORT datab (208:208:208) (277:277:277))
- (PORT datac (116:116:116) (158:158:158))
- (PORT datad (153:153:153) (184:184:184))
- (IOPATH datab combout (167:167:167) (167:167:167))
- (IOPATH datac combout (119:119:119) (124:124:124))
- (IOPATH datad combout (68:68:68) (63:63:63))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[11\])
- (DELAY
- (ABSOLUTE
- (PORT clk (922:922:922) (928:928:928))
- (PORT d (37:37:37) (50:50:50))
- (IOPATH (posedge clk) q (105:105:105) (105:105:105))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (84:84:84))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~20)
- (DELAY
- (ABSOLUTE
- (PORT datab (130:130:130) (178:178:178))
- (PORT datac (191:191:191) (253:253:253))
- (PORT datad (153:153:153) (184:184:184))
- (IOPATH datab combout (168:168:168) (167:167:167))
- (IOPATH datac combout (119:119:119) (124:124:124))
- (IOPATH datad combout (68:68:68) (63:63:63))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[12\])
- (DELAY
- (ABSOLUTE
- (PORT clk (922:922:922) (928:928:928))
- (PORT d (37:37:37) (50:50:50))
- (IOPATH (posedge clk) q (105:105:105) (105:105:105))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (84:84:84))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~19)
- (DELAY
- (ABSOLUTE
- (PORT dataa (268:268:268) (335:335:335))
- (PORT datac (196:196:196) (248:248:248))
- (PORT datad (216:216:216) (248:248:248))
- (IOPATH dataa combout (166:166:166) (163:163:163))
- (IOPATH datac combout (119:119:119) (124:124:124))
- (IOPATH datad combout (68:68:68) (63:63:63))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[13\])
- (DELAY
- (ABSOLUTE
- (PORT clk (923:923:923) (928:928:928))
- (PORT d (37:37:37) (50:50:50))
- (IOPATH (posedge clk) q (105:105:105) (105:105:105))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (84:84:84))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~18)
- (DELAY
- (ABSOLUTE
- (PORT datab (205:205:205) (275:275:275))
- (PORT datac (188:188:188) (240:240:240))
- (PORT datad (152:152:152) (184:184:184))
- (IOPATH datab combout (167:167:167) (167:167:167))
- (IOPATH datac combout (119:119:119) (124:124:124))
- (IOPATH datad combout (68:68:68) (63:63:63))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[14\])
- (DELAY
- (ABSOLUTE
- (PORT clk (922:922:922) (928:928:928))
- (PORT d (37:37:37) (50:50:50))
- (IOPATH (posedge clk) q (105:105:105) (105:105:105))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (84:84:84))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~17)
- (DELAY
- (ABSOLUTE
- (PORT datab (131:131:131) (179:179:179))
- (PORT datac (184:184:184) (246:246:246))
- (PORT datad (153:153:153) (185:185:185))
- (IOPATH datab combout (168:168:168) (167:167:167))
- (IOPATH datac combout (119:119:119) (124:124:124))
- (IOPATH datad combout (68:68:68) (63:63:63))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[15\])
- (DELAY
- (ABSOLUTE
- (PORT clk (922:922:922) (928:928:928))
- (PORT d (37:37:37) (50:50:50))
- (IOPATH (posedge clk) q (105:105:105) (105:105:105))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (84:84:84))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~16)
- (DELAY
- (ABSOLUTE
- (PORT datab (207:207:207) (276:276:276))
- (PORT datac (189:189:189) (236:236:236))
- (PORT datad (153:153:153) (184:184:184))
- (IOPATH datab combout (167:167:167) (167:167:167))
- (IOPATH datac combout (119:119:119) (124:124:124))
- (IOPATH datad combout (68:68:68) (63:63:63))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[16\])
- (DELAY
- (ABSOLUTE
- (PORT clk (922:922:922) (928:928:928))
- (PORT d (37:37:37) (50:50:50))
- (IOPATH (posedge clk) q (105:105:105) (105:105:105))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (84:84:84))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~15)
- (DELAY
- (ABSOLUTE
- (PORT datab (131:131:131) (178:178:178))
- (PORT datac (189:189:189) (251:251:251))
- (PORT datad (153:153:153) (183:183:183))
- (IOPATH datab combout (168:168:168) (167:167:167))
- (IOPATH datac combout (119:119:119) (124:124:124))
- (IOPATH datad combout (68:68:68) (63:63:63))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[17\])
- (DELAY
- (ABSOLUTE
- (PORT clk (922:922:922) (928:928:928))
- (PORT d (37:37:37) (50:50:50))
- (IOPATH (posedge clk) q (105:105:105) (105:105:105))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (84:84:84))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~14)
- (DELAY
- (ABSOLUTE
- (PORT datab (200:200:200) (267:267:267))
- (PORT datac (119:119:119) (161:161:161))
- (PORT datad (155:155:155) (186:186:186))
- (IOPATH datab combout (167:167:167) (167:167:167))
- (IOPATH datac combout (119:119:119) (124:124:124))
- (IOPATH datad combout (68:68:68) (63:63:63))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[18\])
- (DELAY
- (ABSOLUTE
- (PORT clk (922:922:922) (928:928:928))
- (PORT d (37:37:37) (50:50:50))
- (IOPATH (posedge clk) q (105:105:105) (105:105:105))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (84:84:84))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~13)
- (DELAY
- (ABSOLUTE
- (PORT datab (320:320:320) (400:400:400))
- (PORT datac (205:205:205) (261:261:261))
- (PORT datad (251:251:251) (301:301:301))
- (IOPATH datab combout (167:167:167) (167:167:167))
- (IOPATH datac combout (119:119:119) (124:124:124))
- (IOPATH datad combout (68:68:68) (63:63:63))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[19\])
- (DELAY
- (ABSOLUTE
- (PORT clk (922:922:922) (927:927:927))
- (PORT d (37:37:37) (50:50:50))
- (IOPATH (posedge clk) q (105:105:105) (105:105:105))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (84:84:84))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~12)
- (DELAY
- (ABSOLUTE
- (PORT datab (133:133:133) (182:182:182))
- (PORT datac (290:290:290) (369:369:369))
- (PORT datad (254:254:254) (304:304:304))
- (IOPATH datab combout (168:168:168) (167:167:167))
- (IOPATH datac combout (119:119:119) (124:124:124))
- (IOPATH datad combout (68:68:68) (63:63:63))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[20\])
- (DELAY
- (ABSOLUTE
- (PORT clk (922:922:922) (927:927:927))
- (PORT d (37:37:37) (50:50:50))
- (IOPATH (posedge clk) q (105:105:105) (105:105:105))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (84:84:84))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~10)
- (DELAY
- (ABSOLUTE
- (PORT dataa (216:216:216) (275:275:275))
- (PORT datac (291:291:291) (370:370:370))
- (PORT datad (201:201:201) (247:247:247))
- (IOPATH dataa combout (170:170:170) (163:163:163))
- (IOPATH datac combout (119:119:119) (124:124:124))
- (IOPATH datad combout (68:68:68) (63:63:63))
- )
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~11)
- (DELAY
- (ABSOLUTE
- (PORT dataa (239:239:239) (299:299:299))
- (PORT datab (133:133:133) (181:181:181))
- (PORT datac (214:214:214) (267:267:267))
- (PORT datad (92:92:92) (110:110:110))
- (IOPATH dataa combout (170:170:170) (163:163:163))
- (IOPATH datab combout (168:168:168) (167:167:167))
- (IOPATH datac combout (119:119:119) (124:124:124))
- (IOPATH datad combout (68:68:68) (63:63:63))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[21\])
- (DELAY
- (ABSOLUTE
- (PORT clk (922:922:922) (927:927:927))
- (PORT d (37:37:37) (50:50:50))
- (IOPATH (posedge clk) q (105:105:105) (105:105:105))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (84:84:84))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~9)
- (DELAY
- (ABSOLUTE
- (PORT dataa (133:133:133) (185:185:185))
- (PORT datac (292:292:292) (371:371:371))
- (PORT datad (253:253:253) (303:303:303))
- (IOPATH dataa combout (170:170:170) (163:163:163))
- (IOPATH datac combout (119:119:119) (124:124:124))
- (IOPATH datad combout (68:68:68) (63:63:63))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[22\])
- (DELAY
- (ABSOLUTE
- (PORT clk (922:922:922) (927:927:927))
- (PORT d (37:37:37) (50:50:50))
- (IOPATH (posedge clk) q (105:105:105) (105:105:105))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (84:84:84))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~8)
- (DELAY
- (ABSOLUTE
- (PORT dataa (131:131:131) (182:182:182))
- (PORT datac (290:290:290) (369:369:369))
- (PORT datad (254:254:254) (304:304:304))
- (IOPATH dataa combout (170:170:170) (163:163:163))
- (IOPATH datac combout (119:119:119) (124:124:124))
- (IOPATH datad combout (68:68:68) (63:63:63))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[23\])
- (DELAY
- (ABSOLUTE
- (PORT clk (922:922:922) (927:927:927))
- (PORT d (37:37:37) (50:50:50))
- (IOPATH (posedge clk) q (105:105:105) (105:105:105))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (84:84:84))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~7)
- (DELAY
- (ABSOLUTE
- (PORT dataa (131:131:131) (182:182:182))
- (PORT datac (289:289:289) (368:368:368))
- (PORT datad (254:254:254) (305:305:305))
- (IOPATH dataa combout (170:170:170) (163:163:163))
- (IOPATH datac combout (119:119:119) (124:124:124))
- (IOPATH datad combout (68:68:68) (63:63:63))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[24\])
- (DELAY
- (ABSOLUTE
- (PORT clk (922:922:922) (927:927:927))
- (PORT d (37:37:37) (50:50:50))
- (IOPATH (posedge clk) q (105:105:105) (105:105:105))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (84:84:84))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~6)
- (DELAY
- (ABSOLUTE
- (PORT datab (134:134:134) (183:183:183))
- (PORT datac (298:298:298) (378:378:378))
- (PORT datad (251:251:251) (301:301:301))
- (IOPATH datab combout (168:168:168) (167:167:167))
- (IOPATH datac combout (119:119:119) (124:124:124))
- (IOPATH datad combout (68:68:68) (63:63:63))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[25\])
- (DELAY
- (ABSOLUTE
- (PORT clk (922:922:922) (927:927:927))
- (PORT d (37:37:37) (50:50:50))
- (IOPATH (posedge clk) q (105:105:105) (105:105:105))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (84:84:84))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~5)
- (DELAY
- (ABSOLUTE
- (PORT dataa (132:132:132) (183:183:183))
- (PORT datac (295:295:295) (375:375:375))
- (PORT datad (252:252:252) (302:302:302))
- (IOPATH dataa combout (170:170:170) (163:163:163))
- (IOPATH datac combout (119:119:119) (124:124:124))
- (IOPATH datad combout (68:68:68) (63:63:63))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[26\])
- (DELAY
- (ABSOLUTE
- (PORT clk (922:922:922) (927:927:927))
- (PORT d (37:37:37) (50:50:50))
- (IOPATH (posedge clk) q (105:105:105) (105:105:105))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (84:84:84))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~4)
- (DELAY
- (ABSOLUTE
- (PORT datab (131:131:131) (179:179:179))
- (PORT datac (292:292:292) (371:371:371))
- (PORT datad (253:253:253) (303:303:303))
- (IOPATH datab combout (168:168:168) (167:167:167))
- (IOPATH datac combout (119:119:119) (124:124:124))
- (IOPATH datad combout (68:68:68) (63:63:63))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[27\])
- (DELAY
- (ABSOLUTE
- (PORT clk (922:922:922) (927:927:927))
- (PORT d (37:37:37) (50:50:50))
- (IOPATH (posedge clk) q (105:105:105) (105:105:105))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (84:84:84))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~3)
- (DELAY
- (ABSOLUTE
- (PORT datab (130:130:130) (179:179:179))
- (PORT datac (294:294:294) (373:373:373))
- (PORT datad (253:253:253) (302:302:302))
- (IOPATH datab combout (168:168:168) (167:167:167))
- (IOPATH datac combout (119:119:119) (124:124:124))
- (IOPATH datad combout (68:68:68) (63:63:63))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[28\])
- (DELAY
- (ABSOLUTE
- (PORT clk (922:922:922) (927:927:927))
- (PORT d (37:37:37) (50:50:50))
- (IOPATH (posedge clk) q (105:105:105) (105:105:105))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (84:84:84))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~2)
- (DELAY
- (ABSOLUTE
- (PORT datab (130:130:130) (179:179:179))
- (PORT datac (295:295:295) (374:374:374))
- (PORT datad (252:252:252) (302:302:302))
- (IOPATH datab combout (168:168:168) (167:167:167))
- (IOPATH datac combout (119:119:119) (124:124:124))
- (IOPATH datad combout (68:68:68) (63:63:63))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[29\])
- (DELAY
- (ABSOLUTE
- (PORT clk (922:922:922) (927:927:927))
- (PORT d (37:37:37) (50:50:50))
- (IOPATH (posedge clk) q (105:105:105) (105:105:105))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (84:84:84))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~1)
- (DELAY
- (ABSOLUTE
- (PORT datab (131:131:131) (179:179:179))
- (PORT datac (296:296:296) (376:376:376))
- (PORT datad (252:252:252) (301:301:301))
- (IOPATH datab combout (168:168:168) (167:167:167))
- (IOPATH datac combout (119:119:119) (124:124:124))
- (IOPATH datad combout (68:68:68) (63:63:63))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[30\])
- (DELAY
- (ABSOLUTE
- (PORT clk (922:922:922) (927:927:927))
- (PORT d (37:37:37) (50:50:50))
- (IOPATH (posedge clk) q (105:105:105) (105:105:105))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (84:84:84))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~0)
- (DELAY
- (ABSOLUTE
- (PORT datab (131:131:131) (178:178:178))
- (PORT datac (296:296:296) (375:375:375))
- (PORT datad (252:252:252) (302:302:302))
- (IOPATH datab combout (168:168:168) (167:167:167))
- (IOPATH datac combout (119:119:119) (124:124:124))
- (IOPATH datad combout (68:68:68) (63:63:63))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[31\])
- (DELAY
- (ABSOLUTE
- (PORT clk (922:922:922) (927:927:927))
- (PORT d (37:37:37) (50:50:50))
- (IOPATH (posedge clk) q (105:105:105) (105:105:105))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (84:84:84))
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|qdelayed)
- (DELAY
- (ABSOLUTE
- (PORT clk (931:931:931) (918:918:918))
- (PORT asdata (296:296:296) (336:336:336))
- (IOPATH (posedge clk) q (105:105:105) (105:105:105))
- )
- )
- (TIMINGCHECK
- (HOLD asdata (posedge clk) (84:84:84))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|miso\~0)
- (DELAY
- (ABSOLUTE
- (PORT datab (308:308:308) (387:387:387))
- (PORT datad (254:254:254) (304:304:304))
- (IOPATH datab combout (167:167:167) (167:167:167))
- (IOPATH datac combout (190:190:190) (195:195:195))
- (IOPATH datad combout (68:68:68) (63:63:63))
- )
- )
- )
- (CELL
- (CELLTYPE "cycloneive_io_ibuf")
- (INSTANCE GPIO_0_PI\[10\]\~input)
- (DELAY
- (ABSOLUTE
- (IOPATH i o (238:238:238) (617:617:617))
- )
- )
- )
-)
diff --git a/SPI/simulation/modelsim/SPI_test_modelsim.xrf b/SPI/simulation/modelsim/SPI_test_modelsim.xrf
deleted file mode 100644
index 6610a4ccc551a594ef4fdad7ea20db14c74dd307..0000000000000000000000000000000000000000
--- a/SPI/simulation/modelsim/SPI_test_modelsim.xrf
+++ /dev/null
@@ -1,268 +0,0 @@
-vendor_name = ModelSim
-source_file = 1, C:/Users/damie/Documents/Minibot/SPI/MyTestbench.sv
-source_file = 1, C:/Users/damie/Documents/Minibot/SPI/MySPI.sv
-source_file = 1, C:/Users/damie/Documents/Minibot/SPI/MyDE0_Nano.sv
-source_file = 1, C:/Users/damie/Documents/Minibot/SPI/db/SPI_test.cbx.xml
-design_name = MyDE0_Nano
-instance = comp, \GPIO_2[0]~output , GPIO_2[0]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_2[1]~output , GPIO_2[1]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_2[2]~output , GPIO_2[2]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_2[3]~output , GPIO_2[3]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_2[4]~output , GPIO_2[4]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_2[5]~output , GPIO_2[5]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_2[6]~output , GPIO_2[6]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_2[7]~output , GPIO_2[7]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_2[8]~output , GPIO_2[8]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_2[9]~output , GPIO_2[9]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_2[10]~output , GPIO_2[10]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_2[11]~output , GPIO_2[11]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_2[12]~output , GPIO_2[12]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[0]~output , GPIO_0_PI[0]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[1]~output , GPIO_0_PI[1]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[2]~output , GPIO_0_PI[2]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[3]~output , GPIO_0_PI[3]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[4]~output , GPIO_0_PI[4]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[5]~output , GPIO_0_PI[5]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[6]~output , GPIO_0_PI[6]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[7]~output , GPIO_0_PI[7]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[12]~output , GPIO_0_PI[12]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[13]~output , GPIO_0_PI[13]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[14]~output , GPIO_0_PI[14]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[15]~output , GPIO_0_PI[15]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[16]~output , GPIO_0_PI[16]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[17]~output , GPIO_0_PI[17]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[18]~output , GPIO_0_PI[18]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[19]~output , GPIO_0_PI[19]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[20]~output , GPIO_0_PI[20]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[21]~output , GPIO_0_PI[21]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[22]~output , GPIO_0_PI[22]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[23]~output , GPIO_0_PI[23]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[24]~output , GPIO_0_PI[24]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[25]~output , GPIO_0_PI[25]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[26]~output , GPIO_0_PI[26]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[27]~output , GPIO_0_PI[27]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[28]~output , GPIO_0_PI[28]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[29]~output , GPIO_0_PI[29]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[30]~output , GPIO_0_PI[30]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[32]~output , GPIO_0_PI[32]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[33]~output , GPIO_0_PI[33]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_1[0]~output , GPIO_1[0]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_1[1]~output , GPIO_1[1]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_1[2]~output , GPIO_1[2]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_1[3]~output , GPIO_1[3]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_1[4]~output , GPIO_1[4]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_1[5]~output , GPIO_1[5]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_1[6]~output , GPIO_1[6]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_1[7]~output , GPIO_1[7]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_1[8]~output , GPIO_1[8]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_1[9]~output , GPIO_1[9]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_1[10]~output , GPIO_1[10]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_1[11]~output , GPIO_1[11]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_1[12]~output , GPIO_1[12]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_1[13]~output , GPIO_1[13]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_1[14]~output , GPIO_1[14]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_1[15]~output , GPIO_1[15]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_1[16]~output , GPIO_1[16]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_1[17]~output , GPIO_1[17]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_1[18]~output , GPIO_1[18]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_1[19]~output , GPIO_1[19]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_1[20]~output , GPIO_1[20]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_1[21]~output , GPIO_1[21]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_1[22]~output , GPIO_1[22]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_1[23]~output , GPIO_1[23]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_1[24]~output , GPIO_1[24]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_1[25]~output , GPIO_1[25]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_1[26]~output , GPIO_1[26]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_1[27]~output , GPIO_1[27]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_1[28]~output , GPIO_1[28]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_1[29]~output , GPIO_1[29]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_1[30]~output , GPIO_1[30]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_1[31]~output , GPIO_1[31]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_1[32]~output , GPIO_1[32]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_1[33]~output , GPIO_1[33]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[8]~output , GPIO_0_PI[8]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[9]~output , GPIO_0_PI[9]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[10]~output , GPIO_0_PI[10]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[11]~output , GPIO_0_PI[11]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[31]~output , GPIO_0_PI[31]~output, MyDE0_Nano, 1
-instance = comp, \LED[0]~output , LED[0]~output, MyDE0_Nano, 1
-instance = comp, \LED[1]~output , LED[1]~output, MyDE0_Nano, 1
-instance = comp, \LED[2]~output , LED[2]~output, MyDE0_Nano, 1
-instance = comp, \LED[3]~output , LED[3]~output, MyDE0_Nano, 1
-instance = comp, \LED[4]~output , LED[4]~output, MyDE0_Nano, 1
-instance = comp, \LED[5]~output , LED[5]~output, MyDE0_Nano, 1
-instance = comp, \LED[6]~output , LED[6]~output, MyDE0_Nano, 1
-instance = comp, \LED[7]~output , LED[7]~output, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[8]~input , GPIO_0_PI[8]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[8]~inputclkctrl , GPIO_0_PI[8]~inputclkctrl, MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|cnt[0]~12 , spi_slave_instance|cnt[0]~12, MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|cnt[0] , spi_slave_instance|cnt[0], MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|cnt[1]~4 , spi_slave_instance|cnt[1]~4, MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|cnt[1] , spi_slave_instance|cnt[1], MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|cnt[2]~6 , spi_slave_instance|cnt[2]~6, MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|cnt[2] , spi_slave_instance|cnt[2], MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|cnt[3]~8 , spi_slave_instance|cnt[3]~8, MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|cnt[3] , spi_slave_instance|cnt[3], MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|cnt[4]~10 , spi_slave_instance|cnt[4]~10, MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|cnt[4] , spi_slave_instance|cnt[4], MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[31]~input , GPIO_0_PI[31]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[9]~input , GPIO_0_PI[9]~input, MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q[0] , spi_slave_instance|q[0], MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|Equal0~0 , spi_slave_instance|Equal0~0, MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q~31 , spi_slave_instance|q~31, MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q[1] , spi_slave_instance|q[1], MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q~30 , spi_slave_instance|q~30, MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q[2] , spi_slave_instance|q[2], MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q~29 , spi_slave_instance|q~29, MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q[3] , spi_slave_instance|q[3], MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q~28 , spi_slave_instance|q~28, MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q[4] , spi_slave_instance|q[4], MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q~27 , spi_slave_instance|q~27, MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q[5] , spi_slave_instance|q[5], MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q~26 , spi_slave_instance|q~26, MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q[6] , spi_slave_instance|q[6], MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q~25 , spi_slave_instance|q~25, MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q[7] , spi_slave_instance|q[7], MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q~24 , spi_slave_instance|q~24, MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q[8] , spi_slave_instance|q[8], MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q~23 , spi_slave_instance|q~23, MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q[9] , spi_slave_instance|q[9], MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q~22 , spi_slave_instance|q~22, MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q[10] , spi_slave_instance|q[10], MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q~21 , spi_slave_instance|q~21, MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q[11] , spi_slave_instance|q[11], MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q~20 , spi_slave_instance|q~20, MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q[12] , spi_slave_instance|q[12], MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q~19 , spi_slave_instance|q~19, MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q[13] , spi_slave_instance|q[13], MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q~18 , spi_slave_instance|q~18, MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q[14] , spi_slave_instance|q[14], MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q~17 , spi_slave_instance|q~17, MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q[15] , spi_slave_instance|q[15], MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q~16 , spi_slave_instance|q~16, MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q[16] , spi_slave_instance|q[16], MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q~15 , spi_slave_instance|q~15, MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q[17] , spi_slave_instance|q[17], MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q~14 , spi_slave_instance|q~14, MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q[18] , spi_slave_instance|q[18], MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q~13 , spi_slave_instance|q~13, MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q[19] , spi_slave_instance|q[19], MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q~12 , spi_slave_instance|q~12, MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q[20] , spi_slave_instance|q[20], MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q~10 , spi_slave_instance|q~10, MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q~11 , spi_slave_instance|q~11, MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q[21] , spi_slave_instance|q[21], MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q~9 , spi_slave_instance|q~9, MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q[22] , spi_slave_instance|q[22], MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q~8 , spi_slave_instance|q~8, MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q[23] , spi_slave_instance|q[23], MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q~7 , spi_slave_instance|q~7, MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q[24] , spi_slave_instance|q[24], MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q~6 , spi_slave_instance|q~6, MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q[25] , spi_slave_instance|q[25], MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q~5 , spi_slave_instance|q~5, MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q[26] , spi_slave_instance|q[26], MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q~4 , spi_slave_instance|q~4, MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q[27] , spi_slave_instance|q[27], MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q~3 , spi_slave_instance|q~3, MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q[28] , spi_slave_instance|q[28], MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q~2 , spi_slave_instance|q~2, MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q[29] , spi_slave_instance|q[29], MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q~1 , spi_slave_instance|q~1, MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q[30] , spi_slave_instance|q[30], MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q~0 , spi_slave_instance|q~0, MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|q[31] , spi_slave_instance|q[31], MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|qdelayed , spi_slave_instance|qdelayed, MyDE0_Nano, 1
-instance = comp, \spi_slave_instance|miso~0 , spi_slave_instance|miso~0, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[10]~input , GPIO_0_PI[10]~input, MyDE0_Nano, 1
-instance = comp, \CLOCK_50~input , CLOCK_50~input, MyDE0_Nano, 1
-instance = comp, \KEY[0]~input , KEY[0]~input, MyDE0_Nano, 1
-instance = comp, \KEY[1]~input , KEY[1]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_2_IN[0]~input , GPIO_2_IN[0]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_2_IN[1]~input , GPIO_2_IN[1]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_2_IN[2]~input , GPIO_2_IN[2]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI_IN[0]~input , GPIO_0_PI_IN[0]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI_IN[1]~input , GPIO_0_PI_IN[1]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_1_IN[0]~input , GPIO_1_IN[0]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_1_IN[1]~input , GPIO_1_IN[1]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_2[0]~input , GPIO_2[0]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_2[1]~input , GPIO_2[1]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_2[2]~input , GPIO_2[2]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_2[3]~input , GPIO_2[3]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_2[4]~input , GPIO_2[4]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_2[5]~input , GPIO_2[5]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_2[6]~input , GPIO_2[6]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_2[7]~input , GPIO_2[7]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_2[8]~input , GPIO_2[8]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_2[9]~input , GPIO_2[9]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_2[10]~input , GPIO_2[10]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_2[11]~input , GPIO_2[11]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_2[12]~input , GPIO_2[12]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[0]~input , GPIO_0_PI[0]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[1]~input , GPIO_0_PI[1]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[2]~input , GPIO_0_PI[2]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[3]~input , GPIO_0_PI[3]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[4]~input , GPIO_0_PI[4]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[5]~input , GPIO_0_PI[5]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[6]~input , GPIO_0_PI[6]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[7]~input , GPIO_0_PI[7]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[12]~input , GPIO_0_PI[12]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[13]~input , GPIO_0_PI[13]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[14]~input , GPIO_0_PI[14]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[15]~input , GPIO_0_PI[15]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[16]~input , GPIO_0_PI[16]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[17]~input , GPIO_0_PI[17]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[18]~input , GPIO_0_PI[18]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[19]~input , GPIO_0_PI[19]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[20]~input , GPIO_0_PI[20]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[21]~input , GPIO_0_PI[21]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[22]~input , GPIO_0_PI[22]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[23]~input , GPIO_0_PI[23]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[24]~input , GPIO_0_PI[24]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[25]~input , GPIO_0_PI[25]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[26]~input , GPIO_0_PI[26]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[27]~input , GPIO_0_PI[27]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[28]~input , GPIO_0_PI[28]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[29]~input , GPIO_0_PI[29]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[30]~input , GPIO_0_PI[30]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[32]~input , GPIO_0_PI[32]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[33]~input , GPIO_0_PI[33]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_1[0]~input , GPIO_1[0]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_1[1]~input , GPIO_1[1]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_1[2]~input , GPIO_1[2]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_1[3]~input , GPIO_1[3]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_1[4]~input , GPIO_1[4]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_1[5]~input , GPIO_1[5]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_1[6]~input , GPIO_1[6]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_1[7]~input , GPIO_1[7]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_1[8]~input , GPIO_1[8]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_1[9]~input , GPIO_1[9]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_1[10]~input , GPIO_1[10]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_1[11]~input , GPIO_1[11]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_1[12]~input , GPIO_1[12]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_1[13]~input , GPIO_1[13]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_1[14]~input , GPIO_1[14]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_1[15]~input , GPIO_1[15]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_1[16]~input , GPIO_1[16]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_1[17]~input , GPIO_1[17]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_1[18]~input , GPIO_1[18]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_1[19]~input , GPIO_1[19]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_1[20]~input , GPIO_1[20]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_1[21]~input , GPIO_1[21]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_1[22]~input , GPIO_1[22]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_1[23]~input , GPIO_1[23]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_1[24]~input , GPIO_1[24]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_1[25]~input , GPIO_1[25]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_1[26]~input , GPIO_1[26]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_1[27]~input , GPIO_1[27]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_1[28]~input , GPIO_1[28]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_1[29]~input , GPIO_1[29]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_1[30]~input , GPIO_1[30]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_1[31]~input , GPIO_1[31]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_1[32]~input , GPIO_1[32]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_1[33]~input , GPIO_1[33]~input, MyDE0_Nano, 1
-instance = comp, \GPIO_0_PI[11]~input , GPIO_0_PI[11]~input, MyDE0_Nano, 1
-design_name = hard_block
-instance = comp, \~ALTERA_ASDO_DATA1~~ibuf , ~ALTERA_ASDO_DATA1~~ibuf, hard_block, 1
-instance = comp, \~ALTERA_FLASH_nCE_nCSO~~ibuf , ~ALTERA_FLASH_nCE_nCSO~~ibuf, hard_block, 1
-instance = comp, \~ALTERA_DATA0~~ibuf , ~ALTERA_DATA0~~ibuf, hard_block, 1
diff --git a/SPI/simulation/modelsim/SPI_test_v.sdo b/SPI/simulation/modelsim/SPI_test_v.sdo
deleted file mode 100644
index 1d05890a89b84c463240dcc0e93718077dae1a55..0000000000000000000000000000000000000000
--- a/SPI/simulation/modelsim/SPI_test_v.sdo
+++ /dev/null
@@ -1,1172 +0,0 @@
-// Copyright (C) 2018 Intel Corporation. All rights reserved.
-// Your use of Intel Corporation's design tools, logic functions
-// and other software and tools, and its AMPP partner logic
-// functions, and any output files from any of the foregoing
-// (including device programming or simulation files), and any
-// associated documentation or information are expressly subject
-// to the terms and conditions of the Intel Program License
-// Subscription Agreement, the Intel Quartus Prime License Agreement,
-// the Intel FPGA IP License Agreement, or other applicable license
-// agreement, including, without limitation, that your use is for
-// the sole purpose of programming logic devices manufactured by
-// Intel and sold by Intel or its authorized distributors. Please
-// refer to the applicable agreement for further details.
-
-
-//
-// Device: Altera EP4CE22F17C6 Package FBGA256
-//
-
-//
-// This file contains Slow Corner delays for the design using part EP4CE22F17C6,
-// with speed grade 6, core voltage 1.2VmV, and temperature 85 Celsius
-//
-
-//
-// This SDF file should be used for ModelSim-Altera (SystemVerilog) only
-//
-
-(DELAYFILE
- (SDFVERSION "2.1")
- (DESIGN "MyDE0_Nano")
- (DATE "11/16/2022 16:51:48")
- (VENDOR "Altera")
- (PROGRAM "Quartus Prime")
- (VERSION "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition")
- (DIVIDER .)
- (TIMESCALE 1 ps)
-
- (CELL
- (CELLTYPE "cycloneive_io_obuf")
- (INSTANCE GPIO_0_PI\[11\]\~output)
- (DELAY
- (ABSOLUTE
- (PORT i (699:699:699) (676:676:676))
- (PORT oe (3075:3075:3075) (2835:2835:2835))
- (IOPATH i o (2593:2593:2593) (2562:2562:2562))
- (IOPATH oe o (2615:2615:2615) (2536:2536:2536))
- )
- )
- )
- (CELL
- (CELLTYPE "cycloneive_io_ibuf")
- (INSTANCE GPIO_0_PI\[8\]\~input)
- (DELAY
- (ABSOLUTE
- (IOPATH i o (516:516:516) (681:681:681))
- )
- )
- )
- (CELL
- (CELLTYPE "cycloneive_clkctrl")
- (INSTANCE GPIO_0_PI\[8\]\~inputclkctrl)
- (DELAY
- (ABSOLUTE
- (IOPATH inclk outclk (206:206:206) (195:195:195))
- )
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|cnt\[0\]\~12)
- (DELAY
- (ABSOLUTE
- (IOPATH datac combout (353:353:353) (369:369:369))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|cnt\[0\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1549:1549:1549) (1551:1551:1551))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|cnt\[1\]\~4)
- (DELAY
- (ABSOLUTE
- (PORT dataa (274:274:274) (364:364:364))
- (PORT datab (270:270:270) (355:355:355))
- (IOPATH dataa combout (339:339:339) (367:367:367))
- (IOPATH dataa cout (436:436:436) (315:315:315))
- (IOPATH datab combout (344:344:344) (369:369:369))
- (IOPATH datab cout (446:446:446) (318:318:318))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|cnt\[1\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1549:1549:1549) (1551:1551:1551))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|cnt\[2\]\~6)
- (DELAY
- (ABSOLUTE
- (PORT datab (409:409:409) (483:483:483))
- (IOPATH datab combout (365:365:365) (373:373:373))
- (IOPATH datab cout (446:446:446) (318:318:318))
- (IOPATH datad combout (130:130:130) (120:120:120))
- (IOPATH cin combout (455:455:455) (437:437:437))
- (IOPATH cin cout (58:58:58) (58:58:58))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|cnt\[2\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1549:1549:1549) (1551:1551:1551))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|cnt\[3\]\~8)
- (DELAY
- (ABSOLUTE
- (PORT dataa (272:272:272) (361:361:361))
- (IOPATH dataa combout (354:354:354) (367:367:367))
- (IOPATH dataa cout (436:436:436) (315:315:315))
- (IOPATH datad combout (130:130:130) (120:120:120))
- (IOPATH cin combout (455:455:455) (437:437:437))
- (IOPATH cin cout (58:58:58) (58:58:58))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|cnt\[3\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1549:1549:1549) (1551:1551:1551))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|cnt\[4\]\~10)
- (DELAY
- (ABSOLUTE
- (PORT datab (367:367:367) (478:478:478))
- (IOPATH datab combout (365:365:365) (373:373:373))
- (IOPATH cin combout (455:455:455) (437:437:437))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|cnt\[4\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1549:1549:1549) (1551:1551:1551))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_io_ibuf")
- (INSTANCE GPIO_0_PI\[31\]\~input)
- (DELAY
- (ABSOLUTE
- (IOPATH i o (514:514:514) (679:679:679))
- )
- )
- )
- (CELL
- (CELLTYPE "cycloneive_io_ibuf")
- (INSTANCE GPIO_0_PI\[9\]\~input)
- (DELAY
- (ABSOLUTE
- (IOPATH i o (514:514:514) (679:679:679))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[0\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1543:1543:1543) (1559:1559:1559))
- (PORT asdata (3670:3670:3670) (3988:3988:3988))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD asdata (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|Equal0\~0)
- (DELAY
- (ABSOLUTE
- (PORT dataa (273:273:273) (364:364:364))
- (PORT datab (272:272:272) (357:357:357))
- (PORT datac (237:237:237) (313:313:313))
- (PORT datad (246:246:246) (319:319:319))
- (IOPATH dataa combout (350:350:350) (366:366:366))
- (IOPATH datab combout (350:350:350) (368:368:368))
- (IOPATH datac combout (241:241:241) (241:241:241))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~31)
- (DELAY
- (ABSOLUTE
- (PORT dataa (491:491:491) (582:582:582))
- (PORT datab (3612:3612:3612) (3959:3959:3959))
- (PORT datac (218:218:218) (295:295:295))
- (PORT datad (406:406:406) (430:430:430))
- (IOPATH dataa combout (325:325:325) (320:320:320))
- (IOPATH datab combout (306:306:306) (308:308:308))
- (IOPATH datac combout (243:243:243) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[1\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1543:1543:1543) (1559:1559:1559))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~30)
- (DELAY
- (ABSOLUTE
- (PORT dataa (492:492:492) (583:583:583))
- (PORT datac (217:217:217) (293:293:293))
- (PORT datad (407:407:407) (429:429:429))
- (IOPATH dataa combout (304:304:304) (307:307:307))
- (IOPATH datac combout (243:243:243) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[2\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1543:1543:1543) (1559:1559:1559))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~29)
- (DELAY
- (ABSOLUTE
- (PORT dataa (494:494:494) (582:582:582))
- (PORT datab (244:244:244) (327:327:327))
- (PORT datad (410:410:410) (429:429:429))
- (IOPATH dataa combout (300:300:300) (308:308:308))
- (IOPATH datab combout (355:355:355) (369:369:369))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[3\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1543:1543:1543) (1559:1559:1559))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~28)
- (DELAY
- (ABSOLUTE
- (PORT dataa (482:482:482) (574:574:574))
- (PORT datac (219:219:219) (296:296:296))
- (PORT datad (410:410:410) (430:430:430))
- (IOPATH dataa combout (304:304:304) (307:307:307))
- (IOPATH datac combout (243:243:243) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[4\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1543:1543:1543) (1559:1559:1559))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~27)
- (DELAY
- (ABSOLUTE
- (PORT dataa (492:492:492) (581:581:581))
- (PORT datac (218:218:218) (296:296:296))
- (PORT datad (405:405:405) (428:428:428))
- (IOPATH dataa combout (304:304:304) (307:307:307))
- (IOPATH datac combout (243:243:243) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[5\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1543:1543:1543) (1559:1559:1559))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~26)
- (DELAY
- (ABSOLUTE
- (PORT dataa (493:493:493) (582:582:582))
- (PORT datab (245:245:245) (327:327:327))
- (PORT datad (409:409:409) (428:428:428))
- (IOPATH dataa combout (300:300:300) (308:308:308))
- (IOPATH datab combout (355:355:355) (369:369:369))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[6\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1543:1543:1543) (1559:1559:1559))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~25)
- (DELAY
- (ABSOLUTE
- (PORT dataa (483:483:483) (576:576:576))
- (PORT datab (246:246:246) (330:330:330))
- (PORT datad (410:410:410) (433:433:433))
- (IOPATH dataa combout (300:300:300) (308:308:308))
- (IOPATH datab combout (355:355:355) (369:369:369))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[7\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1543:1543:1543) (1559:1559:1559))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~24)
- (DELAY
- (ABSOLUTE
- (PORT datab (369:369:369) (483:483:483))
- (PORT datac (361:361:361) (431:431:431))
- (PORT datad (281:281:281) (328:328:328))
- (IOPATH datab combout (306:306:306) (308:308:308))
- (IOPATH datac combout (243:243:243) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[8\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1542:1542:1542) (1558:1558:1558))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~23)
- (DELAY
- (ABSOLUTE
- (PORT datab (246:246:246) (329:329:329))
- (PORT datac (338:338:338) (447:447:447))
- (PORT datad (279:279:279) (326:326:326))
- (IOPATH datab combout (355:355:355) (369:369:369))
- (IOPATH datac combout (241:241:241) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[9\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1542:1542:1542) (1558:1558:1558))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~22)
- (DELAY
- (ABSOLUTE
- (PORT datab (244:244:244) (326:326:326))
- (PORT datac (338:338:338) (448:448:448))
- (PORT datad (280:280:280) (326:326:326))
- (IOPATH datab combout (355:355:355) (369:369:369))
- (IOPATH datac combout (241:241:241) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[10\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1542:1542:1542) (1558:1558:1558))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~21)
- (DELAY
- (ABSOLUTE
- (PORT datab (368:368:368) (485:485:485))
- (PORT datac (216:216:216) (293:293:293))
- (PORT datad (280:280:280) (325:325:325))
- (IOPATH datab combout (306:306:306) (308:308:308))
- (IOPATH datac combout (243:243:243) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[11\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1542:1542:1542) (1558:1558:1558))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~20)
- (DELAY
- (ABSOLUTE
- (PORT datab (244:244:244) (326:326:326))
- (PORT datac (337:337:337) (446:446:446))
- (PORT datad (279:279:279) (325:325:325))
- (IOPATH datab combout (355:355:355) (369:369:369))
- (IOPATH datac combout (241:241:241) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[12\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1542:1542:1542) (1558:1558:1558))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~19)
- (DELAY
- (ABSOLUTE
- (PORT dataa (493:493:493) (582:582:582))
- (PORT datac (382:382:382) (442:442:442))
- (PORT datad (405:405:405) (429:429:429))
- (IOPATH dataa combout (304:304:304) (307:307:307))
- (IOPATH datac combout (243:243:243) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[13\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1543:1543:1543) (1559:1559:1559))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~18)
- (DELAY
- (ABSOLUTE
- (PORT datab (366:366:366) (485:485:485))
- (PORT datac (360:360:360) (431:431:431))
- (PORT datad (281:281:281) (331:331:331))
- (IOPATH datab combout (306:306:306) (308:308:308))
- (IOPATH datac combout (243:243:243) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[14\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1542:1542:1542) (1558:1558:1558))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~17)
- (DELAY
- (ABSOLUTE
- (PORT datab (246:246:246) (329:329:329))
- (PORT datac (332:332:332) (442:442:442))
- (PORT datad (281:281:281) (331:331:331))
- (IOPATH datab combout (355:355:355) (369:369:369))
- (IOPATH datac combout (241:241:241) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[15\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1542:1542:1542) (1558:1558:1558))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~16)
- (DELAY
- (ABSOLUTE
- (PORT datab (372:372:372) (486:486:486))
- (PORT datac (364:364:364) (424:424:424))
- (PORT datad (281:281:281) (328:328:328))
- (IOPATH datab combout (306:306:306) (308:308:308))
- (IOPATH datac combout (243:243:243) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[16\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1542:1542:1542) (1558:1558:1558))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~15)
- (DELAY
- (ABSOLUTE
- (PORT datab (245:245:245) (327:327:327))
- (PORT datac (335:335:335) (444:444:444))
- (PORT datad (281:281:281) (327:327:327))
- (IOPATH datab combout (355:355:355) (369:369:369))
- (IOPATH datac combout (241:241:241) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[17\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1542:1542:1542) (1558:1558:1558))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~14)
- (DELAY
- (ABSOLUTE
- (PORT datab (360:360:360) (475:475:475))
- (PORT datac (219:219:219) (296:296:296))
- (PORT datad (280:280:280) (328:328:328))
- (IOPATH datab combout (306:306:306) (308:308:308))
- (IOPATH datac combout (243:243:243) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[18\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1542:1542:1542) (1558:1558:1558))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~13)
- (DELAY
- (ABSOLUTE
- (PORT datab (570:570:570) (668:668:668))
- (PORT datac (396:396:396) (461:461:461))
- (PORT datad (464:464:464) (508:508:508))
- (IOPATH datab combout (306:306:306) (308:308:308))
- (IOPATH datac combout (243:243:243) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[19\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1541:1541:1541) (1557:1557:1557))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~12)
- (DELAY
- (ABSOLUTE
- (PORT datab (246:246:246) (329:329:329))
- (PORT datac (517:517:517) (627:627:627))
- (PORT datad (465:465:465) (514:514:514))
- (IOPATH datab combout (355:355:355) (369:369:369))
- (IOPATH datac combout (241:241:241) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[20\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1541:1541:1541) (1557:1557:1557))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~10)
- (DELAY
- (ABSOLUTE
- (PORT dataa (412:412:412) (491:491:491))
- (PORT datac (519:519:519) (627:627:627))
- (PORT datad (383:383:383) (444:444:444))
- (IOPATH dataa combout (354:354:354) (367:367:367))
- (IOPATH datac combout (243:243:243) (241:241:241))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~11)
- (DELAY
- (ABSOLUTE
- (PORT dataa (460:460:460) (530:530:530))
- (PORT datab (246:246:246) (330:330:330))
- (PORT datac (412:412:412) (477:477:477))
- (PORT datad (176:176:176) (202:202:202))
- (IOPATH dataa combout (339:339:339) (367:367:367))
- (IOPATH datab combout (344:344:344) (369:369:369))
- (IOPATH datac combout (243:243:243) (241:241:241))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[21\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1541:1541:1541) (1557:1557:1557))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~9)
- (DELAY
- (ABSOLUTE
- (PORT dataa (248:248:248) (336:336:336))
- (PORT datac (522:522:522) (627:627:627))
- (PORT datad (464:464:464) (513:513:513))
- (IOPATH dataa combout (354:354:354) (367:367:367))
- (IOPATH datac combout (241:241:241) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[22\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1541:1541:1541) (1557:1557:1557))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~8)
- (DELAY
- (ABSOLUTE
- (PORT dataa (246:246:246) (333:333:333))
- (PORT datac (519:519:519) (624:624:624))
- (PORT datad (465:465:465) (515:515:515))
- (IOPATH dataa combout (354:354:354) (367:367:367))
- (IOPATH datac combout (241:241:241) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[23\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1541:1541:1541) (1557:1557:1557))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~7)
- (DELAY
- (ABSOLUTE
- (PORT dataa (246:246:246) (333:333:333))
- (PORT datac (520:520:520) (621:621:621))
- (PORT datad (467:467:467) (515:515:515))
- (IOPATH dataa combout (354:354:354) (367:367:367))
- (IOPATH datac combout (241:241:241) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[24\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1541:1541:1541) (1557:1557:1557))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~6)
- (DELAY
- (ABSOLUTE
- (PORT datab (247:247:247) (331:331:331))
- (PORT datac (532:532:532) (632:632:632))
- (PORT datad (465:465:465) (508:508:508))
- (IOPATH datab combout (355:355:355) (369:369:369))
- (IOPATH datac combout (241:241:241) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[25\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1541:1541:1541) (1557:1557:1557))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~5)
- (DELAY
- (ABSOLUTE
- (PORT dataa (246:246:246) (335:335:335))
- (PORT datac (533:533:533) (633:633:633))
- (PORT datad (460:460:460) (510:510:510))
- (IOPATH dataa combout (354:354:354) (367:367:367))
- (IOPATH datac combout (241:241:241) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[26\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1541:1541:1541) (1557:1557:1557))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~4)
- (DELAY
- (ABSOLUTE
- (PORT datab (245:245:245) (329:329:329))
- (PORT datac (524:524:524) (631:631:631))
- (PORT datad (464:464:464) (513:513:513))
- (IOPATH datab combout (355:355:355) (369:369:369))
- (IOPATH datac combout (241:241:241) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[27\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1541:1541:1541) (1557:1557:1557))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~3)
- (DELAY
- (ABSOLUTE
- (PORT datab (245:245:245) (329:329:329))
- (PORT datac (531:531:531) (632:632:632))
- (PORT datad (462:462:462) (514:514:514))
- (IOPATH datab combout (355:355:355) (369:369:369))
- (IOPATH datac combout (241:241:241) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[28\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1541:1541:1541) (1557:1557:1557))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~2)
- (DELAY
- (ABSOLUTE
- (PORT datab (245:245:245) (329:329:329))
- (PORT datac (532:532:532) (632:632:632))
- (PORT datad (459:459:459) (509:509:509))
- (IOPATH datab combout (355:355:355) (369:369:369))
- (IOPATH datac combout (241:241:241) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[29\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1541:1541:1541) (1557:1557:1557))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~1)
- (DELAY
- (ABSOLUTE
- (PORT datab (245:245:245) (326:326:326))
- (PORT datac (529:529:529) (635:635:635))
- (PORT datad (462:462:462) (500:500:500))
- (IOPATH datab combout (355:355:355) (369:369:369))
- (IOPATH datac combout (241:241:241) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[30\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1541:1541:1541) (1557:1557:1557))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|q\~0)
- (DELAY
- (ABSOLUTE
- (PORT datab (245:245:245) (327:327:327))
- (PORT datac (528:528:528) (635:635:635))
- (PORT datad (461:461:461) (503:503:503))
- (IOPATH datab combout (355:355:355) (369:369:369))
- (IOPATH datac combout (241:241:241) (242:242:242))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|q\[31\])
- (DELAY
- (ABSOLUTE
- (PORT clk (1541:1541:1541) (1557:1557:1557))
- (PORT d (74:74:74) (91:91:91))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD d (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "dffeas")
- (INSTANCE spi_slave_instance\|qdelayed)
- (DELAY
- (ABSOLUTE
- (PORT clk (1548:1548:1548) (1550:1550:1550))
- (PORT asdata (561:561:561) (635:635:635))
- (IOPATH (posedge clk) q (199:199:199) (199:199:199))
- )
- )
- (TIMINGCHECK
- (HOLD asdata (posedge clk) (157:157:157))
- )
- )
- (CELL
- (CELLTYPE "cycloneive_lcell_comb")
- (INSTANCE spi_slave_instance\|miso\~0)
- (DELAY
- (ABSOLUTE
- (PORT datab (558:558:558) (655:655:655))
- (PORT datad (465:465:465) (501:501:501))
- (IOPATH datab combout (306:306:306) (308:308:308))
- (IOPATH datac combout (353:353:353) (369:369:369))
- (IOPATH datad combout (130:130:130) (120:120:120))
- )
- )
- )
- (CELL
- (CELLTYPE "cycloneive_io_ibuf")
- (INSTANCE GPIO_0_PI\[10\]\~input)
- (DELAY
- (ABSOLUTE
- (IOPATH i o (514:514:514) (679:679:679))
- )
- )
- )
-)
diff --git a/controller.c b/controller.c
new file mode 100644
index 0000000000000000000000000000000000000000..0747e94a410350c7dbddb0440959369255eaf99b
--- /dev/null
+++ b/controller.c
@@ -0,0 +1,110 @@
+# include "main.h"
+
+
+//modélise les deux moteur séparément ? -> deux K et tau distinc et donc 2 controller différent aussi
+#define K 1
+#define Tau 1
+#define Kp 1
+#define Ki 1
+#define Kp_dist 1
+#define Kp_angl 1
+
+#define pwm_start 565
+#define pwm_end 665
+
+
+double e[2];
+double e_pos[2];
+
+void low_level(regulation *myregulation){
+ //printf("LOW level unit\n");
+
+ double timestep = 0.01; //a définir plus tard soit avec une clock soit un import time
+ e[0] = myregulation->myspeed->w_ref[0]-myregulation->myspeed->speed[0];
+ e[1] = myregulation->myspeed->w_ref[1]-myregulation->myspeed->speed[1];
+
+ //integral part
+ myregulation->myspeed->e_int[0] += e[0]*timestep;
+ myregulation->myspeed->e_int[1] += e[1]*timestep;
+
+ //REGULATEUR PI
+ myregulation->myspeed->wheel_command[0] = e[0]*Kp + myregulation->myspeed->e_int[0]*Ki;
+ myregulation->myspeed->wheel_command[1] = e[1]*Kp + myregulation->myspeed->e_int[1]*Ki;
+ limiter(myregulation);
+ convert_pwm(myregulation);
+
+}
+
+void middle_level(regulation *myregulation){
+ //printf("MIDDLE level unit\n");
+
+ /*
+ if (myregulation->myspeed->w_robot[1]==0.0){ //d abord annuler l erreur sur l angle
+ myregulation->myspeed->w_ref[0]=myregulation->myspeed->w_robot[0]; //vitesse linéaire => vitesse de chaque roue égale
+ myregulation->myspeed->w_ref[1]=-myregulation->myspeed->w_robot[0];
+ }else{
+ myregulation->myspeed->w_ref[0]=dist_roue_axe*myregulation->myspeed->w_robot[1];
+ myregulation->myspeed->w_ref[1]=dist_roue_axe*myregulation->myspeed->w_robot[1]; //positif ou négatif ?
+ }
+ */
+
+ //%%%%tourner et rouler en meme temps//
+
+ myregulation->myspeed->w_ref[0]=(myregulation->myspeed->w_robot[0]-myregulation->myspeed->w_robot[1]*dist_roue_axe)/rayon_roue;
+ myregulation->myspeed->w_ref[1]=-(myregulation->myspeed->w_robot[0]+myregulation->myspeed->w_robot[1]*dist_roue_axe)/rayon_roue;
+
+ low_level(myregulation);
+}
+
+void high_level(regulation *myregulation){
+ //printf("HIGH level unit\n");
+
+ e_pos[0]=myregulation->mybeacon->beacon_data[0]; //ici dis_ref et angle_ref = 0 car on veut venir proche sur beacon
+ e_pos[1]=myregulation->mybeacon->beacon_data[1];
+
+ //REGULATEUR P
+ myregulation->myspeed->w_robot[0]=Kp_dist*e_pos[0];
+ myregulation->myspeed->w_robot[1]=Kp_angl*e_pos[1];
+
+ middle_level(myregulation);
+}
+
+void limiter(regulation *myregulation){
+ //printf("LIMITER unit\n");
+
+ int i;
+ for(i=0; i<2; i++){ //pour chaque roue on regarde si on est pas hors de la zone liénaire
+ if (myregulation->myspeed->wheel_command[i] > 100){
+ myregulation->myspeed->wheel_command[i] = 100;
+ }
+ else if (myregulation->myspeed->wheel_command[i] < -100){
+ myregulation->myspeed->wheel_command[i] = -100;
+ }
+ }
+}
+
+void convert_pwm(regulation *myregulation){
+ //printf("PWM CONVERTOR unit\n");
+
+ //pour chaque roue venir regarder dans quel sens on veut qu'elle aille et de la venir assigner
+ //la valeur 0 ou 1 selon la roue considéré !! à vérifier
+ if (myregulation->myspeed->wheel_command[0]>0){
+ myregulation->myspeed->wheel_direction[0]=0;
+ }
+ else if (myregulation->myspeed->wheel_command[0]<0){
+ myregulation->myspeed->wheel_direction[0]=1;
+ }
+
+ if (myregulation->myspeed->wheel_command[1]<0){
+ myregulation->myspeed->wheel_direction[1]=1;
+
+ }
+ else if (myregulation->myspeed->wheel_command[1]>0){
+ myregulation->myspeed->wheel_direction[1]=0;
+
+ }
+ //0 -> 565 ?
+ //100 -> 655?
+ myregulation->myspeed->wheel_command[0]=pwm_start + ((pwm_end-pwm_start)/100)*fabs(myregulation->myspeed->wheel_command[0]);
+ myregulation->myspeed->wheel_command[1]=pwm_start + ((pwm_end-pwm_start)/100)*fabs(myregulation->myspeed->wheel_command[1]);
+}
\ No newline at end of file
diff --git a/lidar_detect.c b/lidar_detect.c
new file mode 100644
index 0000000000000000000000000000000000000000..b165daa33eae926b35e4649c139b0962a5ba19d2
--- /dev/null
+++ b/lidar_detect.c
@@ -0,0 +1,49 @@
+#include "main.h"
+
+double treshold_dist=4000;
+double treshold_dist_compare=3;
+double data_factor;
+double old_angle;
+double old_dist;
+double angle;
+double dist;
+
+double angle_beacon[2]; //premier et dernière valeur du beacon
+double dist_beacon[2];
+int first_data=0; //0 -> chercher première valeur ; 1 -> chercher dernière valeur ; 2 -> vérif si beacon
+
+void lidar_detect(regulation *myregulation){
+ //printf("Lidar process\n");
+
+ for(int i; i<res_lidar; i++){
+ dist=myregulation->mylidardata->dist[i];
+ angle=myregulation->mylidardata->angle[i];
+ if ((old_dist-dist<treshold_dist_compare) & (first_data==0)){
+ angle_beacon[0]=old_angle;
+ dist_beacon[0]=old_dist;
+ first_data=1;
+ }
+ else if ((old_dist-dist>treshold_dist_compare) & (first_data==1)){
+ angle_beacon[1]=old_angle;
+ dist_beacon[1]=old_dist;
+ first_data=2;
+ }
+
+ else if (first_data==2){
+ data_factor=((dist_beacon[0]+dist_beacon[1])/2)*tan((angle_beacon[1]-angle_beacon[0])/2);
+ if ((data_factor>form_factor+form_factor*0.2) | (data_factor<form_factor-form_factor*0.2)){
+ first_data=0;
+ }
+ else {
+ myregulation->mybeacon->beacon_data[0]=(dist_beacon[0]+dist_beacon[1])/2;
+ myregulation->mybeacon->beacon_data[1]=(angle_beacon[0]+angle_beacon[1])/2;
+ break;
+ }
+ }
+
+ old_angle=angle;
+ old_dist=dist;
+ }
+ }
+
+
diff --git a/main.c b/main.c
new file mode 100644
index 0000000000000000000000000000000000000000..6fe19aa1bcc408763972b98d1ed8b25b0225ce8e
--- /dev/null
+++ b/main.c
@@ -0,0 +1,57 @@
+#include "main.h"
+
+int main(void) {
+
+ //%%%%%%%%%MALLOC%%%%%%%%
+ regulation *myregulation = malloc(sizeof(regulation));
+ myregulation->mylidardata = malloc(sizeof(lidardata));
+ myregulation->mybeacon = malloc(sizeof(beacon));
+ myregulation->myspeed = malloc(sizeof(speed));
+
+ myregulation->mylidardata->angle=malloc(sizeof(double)*res_lidar);
+ myregulation->mylidardata->dist=malloc(sizeof(double)*res_lidar);
+
+ //%%%%%%%%%FCT%%%%%%%%
+ for (int i=0; i<2; i++){
+ myregulation->myspeed->speed[i]=0;
+ myregulation->myspeed->w_ref[i]=0;
+ myregulation->myspeed->w_robot[i]=0;
+ myregulation->myspeed->wheel_command[i]=0;
+ myregulation->myspeed->wheel_direction[i]=0;
+ myregulation->myspeed->e_int[i]=0;
+ }
+
+
+
+ //%%%%%%%%%FCT%%%%%%%%
+ //printf("Main process\n");
+ /*
+ while (myregulation->mybeacon->beacon_data[0]>10)
+ {
+ update_lidar(myregulation);
+ encoder(myregulation);
+ lidar_detect(myregulation);
+ high_level(myregulation);
+ motor(myregulation);
+ }
+ */
+
+ myregulation->mybeacon->beacon_data[0]=10;
+ myregulation->mybeacon->beacon_data[1]=1;
+ printf("dist beacon: %lf - angle beacon: %lf\n", myregulation->mybeacon->beacon_data[0], myregulation->mybeacon->beacon_data[1]);
+
+ lidar_detect(myregulation);
+ high_level(myregulation);
+
+ printf("wheel command: %lf - %lf\n", myregulation->myspeed->wheel_command[0], myregulation->myspeed->wheel_command[1]);
+ printf("wheel direction: %d - %d\n", myregulation->myspeed->wheel_direction[0], myregulation->myspeed->wheel_direction[1]);
+
+ //%%%%%%%%%FREE%%%%%%%%
+ free(myregulation->mylidardata->angle);
+ free(myregulation->mylidardata->dist);
+ free(myregulation->mylidardata);
+ free(myregulation->mybeacon);
+ free(myregulation);
+
+ exit(0);
+}
diff --git a/main.h b/main.h
new file mode 100644
index 0000000000000000000000000000000000000000..6b129e5be9117b04eaf9df7a2830b8de6d31c491
--- /dev/null
+++ b/main.h
@@ -0,0 +1,45 @@
+# include <stdio.h>
+# include <stdlib.h>
+# include <math.h>
+# include <string.h>
+# include <assert.h>
+
+# define res_lidar 1068
+# define form_factor 5 //diamètre beacon
+#define dist_roue_axe 10 //cm
+#define rayon_roue 2 //cm
+
+typedef struct {
+ double *dist;
+ double *angle;
+} lidardata;
+
+typedef struct {
+ double beacon_data[2];
+} beacon;
+
+typedef struct {
+ double speed[2];
+ double w_ref[2];
+ double e_int[2];
+ double wheel_command[2];
+ int wheel_direction[2];
+ double w_robot[2]; //vitesse linéaire et rotation
+} speed;
+
+typedef struct {
+ lidardata *mylidardata;
+ beacon *mybeacon;
+ speed *myspeed;
+} regulation;
+
+int main(void);
+void lidar_detect(regulation *myregulation);
+void low_level(regulation *myregulation);
+void middle_level(regulation *myregulation);
+void high_level(regulation *myregulation);
+void limiter(regulation *myregulation);
+void convert_pwm(regulation *myregulation);
+
+//gcc -o test main.c lidar_detect.c
+//sudo ./test
\ No newline at end of file
diff --git a/mapLiDAR.py b/mapLiDAR.py
index 001fd6bc76fac7c1c25c5a7d7de6a61026e6e370..e66d16120d885ac70463aaf9f304e03c8180a1f6 100644
--- a/mapLiDAR.py
+++ b/mapLiDAR.py
@@ -5,17 +5,22 @@ import pandas as pd
data = pd.read_csv("lidar.csv", sep='\t')
-theta = data["theta"]
+theta = np.deg2rad(data["theta"])
dist = data["dist"]
+plt.axes(polar=True)
+plt.grid(True)
+
+ax = plt.subplot(111, polar=True)
+
-posx = dist * np.cos(theta)
-posy = dist * np.sin(theta)
for i in range(len(dist)) :
if dist[i] != 0 :
- plt.plot(posx[i], posy[i], 'ob')
+ plt.polar(theta[i],dist[i], '.b')
-plt.axis("equal")
+ax.set_theta_zero_location("N")
+ax.set_rmax(4)
+ax.set_rlabel_position(270)
plt.show()
\ No newline at end of file
diff --git a/test b/test
new file mode 100755
index 0000000000000000000000000000000000000000..1276f20ae22a96dab250282664d2d37f0e3159f7
Binary files /dev/null and b/test differ