diff --git a/SPI/MySPI.sv b/SPI/MySPI.sv deleted file mode 100644 index 89e65463e0d9f133ae97cb0ddc90f0f3dd16c733..0000000000000000000000000000000000000000 --- a/SPI/MySPI.sv +++ /dev/null @@ -1,30 +0,0 @@ -module spi_slave( - input logic sck, // From master - input logic mosi, // From master - output logic miso, // To master - input logic reset, // System reset - input logic[31:0] d, // Data to send - output logic[31:0] q // Data received -); - - logic [4:0] cnt; - logic qdelayed; - - // 5-bit counter tracks when full 32-bit word is transmitted - always_ff @(negedge sck, posedge reset) - if (reset) cnt <= 0; - else cnt <= cnt + 5'b1; - - // Loadable shift register - // Loads d at the start, shifts mosi into bottom on each step - always_ff @(posedge sck) - q <= (cnt == 0) ? {d[30:0], mosi} : {q[30:0], mosi}; - - // Align miso to falling edge of sck - // Load d at the start - always_ff @(negedge sck) - qdelayed <= q[31]; - - assign miso = (cnt == 0) ? d[31] : qdelayed; - -endmodule diff --git a/encoder.cpp b/encoder.cpp index 4415f02e9f7608a0cbdefc266ee7d87705c96679..6be99d0cd5a2bdd0c42e1c2fb1f8d8f036d787a8 100644 --- a/encoder.cpp +++ b/encoder.cpp @@ -1,52 +1,55 @@ -#include <stdlib.h> #include <stdio.h> +#include <stdlib.h> +#include <unistd.h> +#include <iostream> +#include <string.h> + #include <wiringPi.h> #include <wiringPiSPI.h> -/* -const int MOSI_PIN = 12; //from RASPI to FPGA -const int MISO_PIN = 13; //from RASPI to FPGA -const int MOSI_PIN_FPGA = 14; //from RASPI to FPGA -const int MISO_PIN_FPGA = 16; //from RASPI to FPGA -const int VDD_PIN_FPGA = 29; //from FPGA to ENCODER -> ouput data from encoder -const int ENC_PIN_1A = 38; //from FPGA to ENCODER -> ouput data from encoder -const int ENC_PIN_1B = 36; //from FPGA to ENCODER -> ouput data from encoder -const int ENC_PIN_2A = 35; //from FPGA to ENCODER -> ouput data from encoder -const int ENC_PIN_2B = 34; //from FPGA to ENCODER -> ouput data from encoder -const int SCK_PIN = 14; //from RASPI to FPGA -> clock signal -const int SCK_PIN_FPGA = 13; //from FPGA to ENCODER -> clock signal -const int SS_PIN_2 = 11; //CE1 from RASPI to FPGA -> enable encoder -const int CE1_PIN_FPGA = 15; -*/ +using namespace std; -unsigned char rawData[32]; +unsigned char rawData[4]; const int len = 32; -const int CHANNEL_DEO = 1; int main(int argc, char const *argv[]) { - int result, fd; - for (int i = 0; i<32; i++){ - rawData[i] = 0x01;} - + if (wiringPiSetup() == -1) { printf("WiringPiSetup failed\n"); exit(EXIT_FAILURE); } - fd = wiringPiSPISetup(CHANNEL_DEO, 500000); - result = wiringPiSPIDataRW(CHANNEL_DEO, rawData, len); - - //read(wiringPiSPIGetFd (0), data, len); + //memset(rawData,0x33,8); + rawData[0]=0x0F; + rawData[7]=0x0F; + int fd = wiringPiSPISetup(0, 500000); - for (int i = 0; i<32; i++){ - printf("speed: ", rawData[i], "\n"); - } + //for (int i=0; i<8; i++){ + // printf("%d", rawData[i]); + //} + + while(1) { + int result = wiringPiSPIDataRW(0, rawData, len); + //printf("speed\n"); + + printf("\r%02X %02X %02X %02X", rawData[0], rawData[1], rawData[2], rawData[3]); + fflush(stdout); + + + delay(500); + } + return 0; + + + + + /* pinMode(ENC_PIN_1A, INPUT); pinMode(ENC_PIN_1B, INPUT); pinMode(ENC_PIN_2A, INPUT); pinMode(ENC_PIN_2B, INPUT); */ -} +} \ No newline at end of file diff --git a/led_control.cpp b/led_control.cpp new file mode 100644 index 0000000000000000000000000000000000000000..44d5ab7413c0e34e6e1f96482f9fc817577cf7e6 --- /dev/null +++ b/led_control.cpp @@ -0,0 +1,31 @@ +#include <stdio.h> +#include <stdlib.h> +#include <unistd.h> +#include <iostream> +#include <string.h> + +#include <wiringPi.h> +#include <wiringPiSPI.h> + +using namespace std; + +unsigned char rawData[4]; +const int len = 32; + +int main(int argc, char const *argv[]) +{ + + if (wiringPiSetup() == -1) { + printf("WiringPiSetup failed\n"); + exit(EXIT_FAILURE); + } + + memset(rawData,0x00000007,4); + + int fd = wiringPiSPISetup(0, 500000); + int result = wiringPiSPIDataRW(0, rawData, len); + + printf("speed: %d \n", *rawData); + + return 0; +} \ No newline at end of file