SPI file

SPI/MyDE0_Nano.sv

+module MyDE0_Nano(
+
+//////////// CLOCK //////////
+input logic 		          		CLOCK_50,
+
+//////////// LED //////////
+output logic		     [7:0]		LED,
+
+//////////// KEY //////////
+input logic 		     [1:0]		KEY,
+
+//////////// 2x13 GPIO Header //////////
+inout logic 		    [12:0]		GPIO_2,
+input logic 		     [2:0]		GPIO_2_IN,
+
+//////////// GPIO_0, GPIO_0 connect to GPIO Default //////////
+inout logic 		    [33:0]		GPIO_0_PI,
+input logic 		     [1:0]		GPIO_0_PI_IN,
+
+//////////// GPIO_1, GPIO_1 connect to GPIO Default //////////
+inout logic 		    [33:0]		GPIO_1,
+input logic 		     [1:0]		GPIO_1_IN
+);
+
+//=======================================================
+//  SPI
+//=======================================================
+
+	logic spi_clk, spi_cs, spi_mosi, spi_miso;
+	logic [31:0] DataToPI, DataFromPI;
+	
+	spi_slave spi_slave_instance(
+		.sck(spi_clk),
+		.mosi(spi_mosi),
+		.miso(spi_miso),
+		.reset(),
+		.d(DataToPI),
+		.q(DataFromPI)
+	);
+
+	assign spi_clk  		= GPIO_0_PI[8];		// SCLK = pin 13 
+	assign spi_cs   		= GPIO_0_PI[10];	// CE0  = pin 15
+	assign spi_mosi     	= GPIO_0_PI[9];		// MOSI = pin 14
+	
+	assign GPIO_0_PI[11] = spi_cs ? 1'bz : spi_miso;  // MISO = pin 16 	 
+
+	logic ENC_1A, ENC_1B, ENC_2A, ENC_2B; 
+
+	assign ENC_1A = GPIO_0_PI[31]; //pin 38
+	assign ENC_1B = GPIO_0_PI[29]; //pin 36
+	assign ENC_2A = GPIO_0_PI[28]; //pin 35
+	assign ENC_2B = GPIO_0_PI[27]; //pin 34
+
+	always_ff(negedge spi_clk)
+		assign DataToPI = ENC_1A;
+
+endmodule
+

SPI/MySPI.sv

+module spi_slave(
+	input  logic 		sck,		// From master 
+	input  logic 		mosi,		// From master 
+	output logic 		miso,		// To master 
+	input  logic 		reset,		// System reset 
+	input  logic[31:0] 	d,		// Data to send
+	output logic[31:0] 	q		// Data received
+);
+
+	logic [4:0] cnt; 
+	logic qdelayed;
+
+	// 5-bit counter tracks when full 32-bit word is transmitted
+	always_ff @(negedge sck, posedge reset)
+		if (reset) 	cnt <= 0;
+		else     	cnt <= cnt + 5'b1;
+
+	// Loadable shift register
+	// Loads d at the start, shifts mosi into bottom on each step 
+	always_ff @(posedge sck)
+		q <= (cnt == 0) ? {d[30:0], mosi} : {q[30:0], mosi};
+	
+	// Align miso to falling edge of sck 
+	// Load d at the start
+	always_ff @(negedge sck)
+		qdelayed <= q[31];
+	
+	assign miso = (cnt == 0) ? d[31] : qdelayed;
+
+endmodule

SPI/MyTestbench.sv

+module MyTestbench();
+
+  logic        clk;
+  logic        reset;
+
+  logic [15:0] PC;
+  logic [15:0] WriteData;
+  logic [12:0] DataAdr;
+  logic        MemWrite;
+  
+  wire [33:0]	GPIO_0_PI;
+  wire [33:0]	GPIO_1;
+  wire [12:0]	GPIO_2;
+
+  // instantiate device to be tested
+  MyDE0_Nano dut(
+	.CLOCK_50(clk), 
+	.GPIO_0_PI(GPIO_0_PI),
+	.GPIO_1(GPIO_1),  
+	.GPIO_2(GPIO_2)
+	);
+
+  assign GPIO_0_PI[1] = reset;
+  
+  // initialize test
+  initial
+    begin
+      reset <= 1; # 22; reset <= 0;
+    end
+
+  // generate clock to sequence tests
+  always
+    begin
+      clk <= 1; # 5; clk <= 0; # 5;
+    end
+
+  // check results
+  always @(negedge clk)
+    begin
+      if(MemWrite) begin
+        if(DataAdr === 128 & WriteData === 254) begin
+          $display("Simulation succeeded");
+          $stop;
+        end else if (DataAdr === 128) begin
+          $display("Simulation failed");
+          $stop;
+        end
+      end
+    end
+ 
+  // Simulate SPI
+     
+endmodule
\ No newline at end of file

SPI/SPI_test.qpf

+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2018  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
+# Date created = 11:33:52  November 14, 2022
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "18.1"
+DATE = "11:33:52  November 14, 2022"
+
+# Revisions
+
+PROJECT_REVISION = "SPI_test"

SPI/SPI_test.qsf

+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2018  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
+# Date created = 11:33:52  November 14, 2022
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		SPI_test_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus Prime software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone IV E"
+set_global_assignment -name DEVICE EP4CE22F17C6
+set_global_assignment -name TOP_LEVEL_ENTITY MyDE0_Nano
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:33:52  NOVEMBER 14, 2022"
+set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
+set_global_assignment -name SYSTEMVERILOG_FILE MyTestbench.sv
+set_global_assignment -name SYSTEMVERILOG_FILE MySPI.sv
+set_global_assignment -name SYSTEMVERILOG_FILE MyDE0_Nano.sv
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
+set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_location_assignment PIN_R7 -to CLOCK_50
+set_location_assignment PIN_E1 -to KEY[1]
+set_location_assignment PIN_J15 -to KEY[0]
+set_location_assignment PIN_A15 -to LED[0]
+set_location_assignment PIN_D5 -to GPIO_0_PI[9]
+set_location_assignment PIN_A13 -to LED[1]
+set_location_assignment PIN_L3 -to LED[7]
+set_location_assignment PIN_A11 -to LED[3]
+set_location_assignment PIN_B1 -to LED[6]
+set_location_assignment PIN_B13 -to LED[2]
+set_location_assignment PIN_D1 -to LED[4]
+set_location_assignment PIN_F3 -to LED[5]
+set_location_assignment PIN_A5 -to GPIO_0_PI[5]
+set_location_assignment PIN_B6 -to GPIO_0_PI[17]
+set_location_assignment PIN_C11 -to GPIO_0_PI[28]
+set_location_assignment PIN_B11 -to GPIO_0_PI[29]
+set_location_assignment PIN_D11 -to GPIO_0_PI[31]
+set_location_assignment PIN_E10 -to GPIO_0_PI[27]
+set_location_assignment PIN_A6 -to GPIO_0_PI[11]
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file

SPI/cr_ie_info.json

+{
+	"system" : {
+		"platform" : "windows64",
+		"os_name" : "Windows 10",
+		"os_version" : "10.0"
+	},
+	"error" : {
+		"executable" : "quartus_map",
+		"comment" : "none",
+		"error_message" : "cdb_is_connected(tri_data) && !tri_data->is_vcc_or_gnd()",
+		"source_file" : "/quartus/synth/mls/mls_process_tri.cpp",
+		"line" : "6076",
+		"stack_trace" : "\t0x7ff8b4c22039: SYNTH_MLS + 0x82039 (?error_multiple_drivers@OPT_TRI_PROCESSOR@@AEAAXPEAVCDB_SGATE_OTERM@@PEAVCDB_SGATE_NODE@@1@Z + 0x38d)\n\t0x7ff8b4bc615a: SYNTH_MLS + 0x2615a (?process_tribus@OPT_TRI_PROCESSOR@@AEAA?AW4PROCESS_STATUS@@PEAVCDB_SGATE_TRI_BUS@@@Z + 0x352)\n\t0x7ff8b4bc7233: SYNTH_MLS + 0x27233 (?do_processing_loop@OPT_TRI_PROCESSOR@@AEAA?AW4PROCESS_STATUS@@XZ + 0x2b3)\n\t0x7ff8b4bc3143: SYNTH_MLS + 0x23143 (OPT_TRI_PROCESSOR::perform_function + 0x147)\n\t0x7ff8b4bc2c55: SYNTH_MLS + 0x22c55 (OPT_TRI_PROCESSOR::synthesize_tristates + 0x285)\n\t0x7ff8b4be37de: SYNTH_MLS + 0x437de (?opt_process_tri@@YA?AW4PROCESS_STATUS@@PEAVCDB_SGATE_NETLIST@@VMLS_CONFIGURATION@@PEAVCMP_FACADE@@@Z + 0x6e)\n\t0x7ff8b4bb0397: SYNTH_MLS + 0x10397 (?call_named_function@MLS_NETLIST@@QEAAXAEBV?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@00@Z + 0x1a37)\n\t0x7ff8b4bbd799: SYNTH_MLS + 0x1d799 (MLS_NETLIST::call_fn + 0x109)\n\t0x7ff8b4badd0b: SYNTH_MLS + 0xdd0b (MLS_NETLIST::run_script + 0x3d7)\n\t0x7ff8b4ba280b: SYNTH_MLS + 0x280b (MLS_ROOT::start_from_mls_netlist + 0x43)\n\t0x7ff8b3efa7f5: SYNTH_SCL + 0x5a7f5 (?synthesize_with_script@SCL_SYN_HIER@@AEAA_NPEAPEAVMLS_NETLIST@@PEAVCDB_SGATE_NETLIST@@AEBW4SCRIPT_TYPE@MLS_SCRIPT_MANAGER@@PEAPEAVCDB_ATOM_NETLIST@@@Z + 0x195)\n\t0x7ff8b3efb8f7: SYNTH_SCL + 0x5b8f7 (?work_normal_flow@SCL_SYN_HIER@@AEAA_NXZ + 0x637)\n\t0x7ff8b3ec3b25: SYNTH_SCL + 0x23b25 (?process_one_hierarchy@SCL_SYN_STATE@@AEAA_NPEAVCDB_SGATE_HIERARCHY@@PEAPEAVCDB_ATOM_NETLIST@@@Z + 0x95)\n\t0x7ff8b3ec68c6: SYNTH_SCL + 0x268c6 (?synthesize_design@SCL_SYN_STATE@@QEAA_NXZ + 0x446)\n\t0x7ff8b3ec553c: SYNTH_SCL + 0x2553c (?scl_execute_syn@@YA_NPEAVCMP_FACADE@@@Z + 0x9c)\n\t0x7ff8b3ea5794: SYNTH_SCL + 0x5794 (?scl_execute_normal_flow@@YA_NPEAVCMP_FACADE@@_N@Z + 0x134)\n\t0x7ff6f49e56a5: quartus_map + 0x56a5 (?qsyn_execute_scl@@YA_NPEAVQSYN_FRAMEWORK@@PEAVIDU_PARTITION@@_N@Z + 0x255)\n\t0x7ff6f4a0063d: quartus_map + 0x2063d (?scl_iteration@QSYN_FRAMEWORK@@AEAA_NXZ + 0xa8d)\n\t0x7ff6f49f4070: quartus_map + 0x14070 (?execute_core@QSYN_FRAMEWORK@@AEAA_NPEAVTHR_NAMED_PIPE@@0@Z + 0x200)\n\t0x7ff6f49f3aa6: quartus_map + 0x13aa6 (?execute@QSYN_FRAMEWORK@@UEAA_NXZ + 0x496)\n\t0x7ff93c6212bc: comp_qexe + 0x112bc (qexe_do_normal + 0x1ec)\n\t0x7ff93c626142: comp_qexe + 0x16142 (qexe_run + 0x432)\n\t0x7ff93c626e51: comp_qexe + 0x16e51 (?qexe_standard_main@@YAHPEAVQEXE_FRAMEWORK@@PEAPEBUQEXE_OPTION_DEFINITION@@HPEAPEBD@Z + 0xc1)\n\t0x7ff6f49fb08b: quartus_map + 0x1b08b (?qsyn_main@@YAHHPEAPEBD@Z + 0x51b)\n\t0x7ff954b32e98: CCL_MSG + 0x12e98 (?msg_main_thread@@YAPEAXPEAX@Z + 0x18)\n\t0x7ff954b3467e: CCL_MSG + 0x1467e (?msg_thread_wrapper@@YAPEAXP6APEAXPEAX@Z0@Z + 0x6e)\n\t0x7ff954c46660: ccl_mem + 0x16660 (?mem_thread_wrapper@@YAPEAXP6APEAXPEAX@Z0@Z + 0x70)\n\t0x7ff954b32761: CCL_MSG + 0x12761 (?msg_exe_main@@YAHHPEAPEBDP6AHH0@Z@Z + 0xa1)\n\t0x7ff6f4a09872: quartus_map + 0x29872 (__tmainCRTStartup + 0x10e)\n\t0x7ff96ae674b3: KERNEL32 + 0x174b3 (BaseThreadInitThunk + 0x13)\n\t0x7ff96b7226a0: ntdll + 0x526a0 (RtlUserThreadStart + 0x20)\n",
+		"subsystem" : "MLS"
+	},
+	"quartus" : {
+		"quartus_bits" : "64",
+		"version" : "18.1.0",
+		"build" : "625",
+		"edition" : "Lite Edition"
+	}
+}
\ No newline at end of file

SPI/db/SPI_test.asm.qmsg

+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1668613902148 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1668613902155 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 16 16:51:42 2022 " "Processing started: Wed Nov 16 16:51:42 2022" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1668613902155 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1668613902155 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off SPI_test -c SPI_test " "Command: quartus_asm --read_settings_files=off --write_settings_files=off SPI_test -c SPI_test" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1668613902156 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1668613902439 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1668613902988 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1668613903012 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4674 " "Peak virtual memory: 4674 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1668613903151 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 16 16:51:43 2022 " "Processing ended: Wed Nov 16 16:51:43 2022" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1668613903151 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1668613903151 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1668613903151 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1668613903151 ""}

SPI/db/SPI_test.cbx.xml

+<?xml version="1.0" ?>
+<LOG_ROOT>
+	<PROJECT NAME="SPI_test">
+	</PROJECT>
+</LOG_ROOT>