\item\textbf{How many Systems LEDs the DE10-Nano has and what are they function?}
There are 11 in total:
There are 6 in total (+8 fpga +1 hps user LED):
\begin{itemize}
\item 8 for personal use of the user
\item 1 as power light indicator
\item 2 as indicator for UART communication (Tx-Rx) % Je crois
\item 2 as indicator for JTAG communication (Tx-Rx)
\item 1 as CONF DONE when FPGA is successfully configured
\item 1 as 3.3 V when the 3.3 V is available
\end{itemize}
\vspace{5pt}\hrule
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@@ -160,13 +158,19 @@
\vspace{5pt}\hrule
\item\textbf{Describe the different boot options of the Cyclone V SoC.}
The processor can boot from the following sources:
There is 3 boot options:
\begin{itemize}
\item independ boot of the CPU and the FPGA as they were 2 discrete devices
\item CPU boot first (default option)
\item FPGA boot first
\end{itemize}
The CPU can boot from the following sources:
\begin{itemize}
\item NAND flash memory through the NAND flash controller
\item SD/MMC flash memory through the SD/MMC flash controller
\item SPI and QSPI flash memory through the QSPI flash controller using Slave Select 0
\item FPGA fabric on-chip memory
\item FPGA fabric on-chip memory%?
\end{itemize}
The choice of the boot source is done by modifying the BOOTSEL and CLKSEL values \textbf{before the device is powered up}. Therefore, the Cyclone V device normally uses a \textbf{physical dip switch} to configure the BOOTSEL and CLKSEL.
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@@ -252,6 +256,8 @@
\vspace{5pt}\hrule
\item\textbf{Describe the different ways to access the DE10-Nano board at run time and for development.}
% TO DO
\end{enumerate}
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@@ -300,11 +306,11 @@
\begin{enumerate}
\item 10 Kb M10K blocks: blocks of dedicated memory resources. The M10K blocks are ideal for larger memory arrays while still providing a large number of independent ports.
Total capacity of those blocks for the Cyclone V: 5500 Kb.
Total capacity of those blocks for the Cyclone V: 5530 Kb (553 blocks).
\item 640 bit memory logic array blocks (MLABs): enhanced memory blocks that are configured from dualpurpose logic array blocks (LABs). The MLABs are ideal for wide and shallow memory arrays. The MLABs are optimized for implementation of shift registers for digital signal processing (DSP) applications, wide shallow FIFO buffers, and filter delay lines. Each MLAB is made up of ten adaptive logic modules (ALMs). In the Cyclone V devices, you can configured these ALMs as then 32 x 2 blocks, giving you one 32 x 20 simple dual-port SRAM block per MLAB.
Total capacity of those blocks for the Cyclone V: 621 Kb.
Total capacity of those blocks for the Cyclone V: 621 Kb (994 MLABs).
\end{enumerate}
\vspace{5pt}\hrule
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@@ -312,7 +318,7 @@
\item\textbf{Give the general variable precision DSP blocks architecture (only the main resources). Explain how can be implemented an independent complex multiplication. How many DSP blocks does the Cyclone V in the DE10-Nano kit contain?}
The following variable precision DSP block signals control the output register per variable precision DSP
block:
block:% ??
\begin{itemize}
\item\texttt{clk[2..0]}
\item\texttt{ena[2..0]}
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@@ -323,14 +329,21 @@
The imaginary part $[(a \times d)+(b \times c)]$ is implemented in the first variable-precision DSP block, while the
real part $[(a \times c)-(b \times d)]$ is implemented in the second variable-precision DSP block.
There are 112 variable precision DSP blocks
\vspace{5pt}\hrule
\item\textbf{Explain the main function of the SCU and ACP blocks?}
Snoop control unit (SCU) ensures coherency between processors.
Snoop control unit (SCU) ensures coherency between processors. The SCU manages data traffic for the Cortex-A9 processors and the memory system, including the L2 cache. In a multi-master system, the processors and other masters can operate on shared data. The SCU ensures that each processor operates on the most up-to-date copy of data, maintaining cache coherency.
Accelerator coherency port (ACP) accepts coherency memory access requests
Accelerator coherency port (ACP) accepts coherency memory access requests.
\begin{figure}[H]
\centering
\includegraphics[width=0.7\textwidth]{SCU.png}
\end{figure}
\vspace{5pt}\hrule
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@@ -349,7 +362,7 @@
\vspace{5pt}\hrule
\item\textbf{Explain the main features of these serial interfaces: I2C, UART, CAN, SPI.}
\item\textbf{Explain the main features of these serial interfaces: I2C, UART, CAN, SPI.}%
\begin{itemize}
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@@ -420,6 +433,17 @@
The FPGA manager in the hard processor system (HPS) manages and monitors the FPGA portion of the system on a chip (SoC) device. The FPGA manager can configure the FPGA fabric from the HPS, monitor the state of the FPGA, and drive or sample signals to or from the FPGA fabric.
The FPGA manager provides the following functionality and features:
\begin{itemize}
\item Full configuration and partial reconfiguration of the FPGA portion of the SoC device
\item Drives 32 general-purpose output signals to the FPGA fabric
\item Receives 32 general-purpose input signals from the FPGA fabric
\item Receives two boot handshaking input signals from the FPGA fabric (used when the HPS boots from the FPGA)
\item Monitors the FPGA configuration and power status
\item Generates interrupts based on the FPGA status changes
\item Can reset the FPGA
\end{itemize}
\vspace{5pt}\hrule
\item\textbf{Give and explain the HPS-FPGA bridges block diagram and system integration.}
