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Valider 39309292 rédigé par Damien Wiame's avatar Damien Wiame
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controller

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Quartus_Version = Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
Version_Index = 486699264
Creation_Time = Wed Nov 16 15:08:01 2022
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1668613907481 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1668613907487 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 16 16:51:47 2022 " "Processing started: Wed Nov 16 16:51:47 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1668613907487 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1668613907487 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off SPI_test -c SPI_test " "Command: quartus_eda --read_settings_files=off --write_settings_files=off SPI_test -c SPI_test" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1668613907487 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1668613908108 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "SPI_test_6_1200mv_85c_slow.svo C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/ simulation " "Generated file SPI_test_6_1200mv_85c_slow.svo in folder \"C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1668613908223 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "SPI_test_6_1200mv_0c_slow.svo C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/ simulation " "Generated file SPI_test_6_1200mv_0c_slow.svo in folder \"C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1668613908245 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "SPI_test_min_1200mv_0c_fast.svo C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/ simulation " "Generated file SPI_test_min_1200mv_0c_fast.svo in folder \"C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1668613908266 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "SPI_test.svo C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/ simulation " "Generated file SPI_test.svo in folder \"C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1668613908286 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "SPI_test_6_1200mv_85c_v_slow.sdo C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/ simulation " "Generated file SPI_test_6_1200mv_85c_v_slow.sdo in folder \"C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1668613908307 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "SPI_test_6_1200mv_0c_v_slow.sdo C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/ simulation " "Generated file SPI_test_6_1200mv_0c_v_slow.sdo in folder \"C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1668613908327 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "SPI_test_min_1200mv_0c_v_fast.sdo C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/ simulation " "Generated file SPI_test_min_1200mv_0c_v_fast.sdo in folder \"C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1668613908344 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "SPI_test_v.sdo C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/ simulation " "Generated file SPI_test_v.sdo in folder \"C:/Users/damie/Documents/Minibot/SPI/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1668613908361 ""}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4635 " "Peak virtual memory: 4635 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1668613908422 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 16 16:51:48 2022 " "Processing ended: Wed Nov 16 16:51:48 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1668613908422 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1668613908422 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1668613908422 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1668613908422 ""}
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|MyDE0_Nano
CLOCK_50 => ~NO_FANOUT~
LED[0] << <GND>
LED[1] << <GND>
LED[2] << <GND>
LED[3] << <GND>
LED[4] << <GND>
LED[5] << <GND>
LED[6] << <GND>
LED[7] << <GND>
KEY[0] => ~NO_FANOUT~
KEY[1] => ~NO_FANOUT~
GPIO_2[0] <> <UNC>
GPIO_2[1] <> <UNC>
GPIO_2[2] <> <UNC>
GPIO_2[3] <> <UNC>
GPIO_2[4] <> <UNC>
GPIO_2[5] <> <UNC>
GPIO_2[6] <> <UNC>
GPIO_2[7] <> <UNC>
GPIO_2[8] <> <UNC>
GPIO_2[9] <> <UNC>
GPIO_2[10] <> <UNC>
GPIO_2[11] <> <UNC>
GPIO_2[12] <> <UNC>
GPIO_2_IN[0] => ~NO_FANOUT~
GPIO_2_IN[1] => ~NO_FANOUT~
GPIO_2_IN[2] => ~NO_FANOUT~
GPIO_0_PI[0] <> <UNC>
GPIO_0_PI[1] <> <UNC>
GPIO_0_PI[2] <> <UNC>
GPIO_0_PI[3] <> <UNC>
GPIO_0_PI[4] <> <UNC>
GPIO_0_PI[5] <> <UNC>
GPIO_0_PI[6] <> <UNC>
GPIO_0_PI[7] <> <UNC>
GPIO_0_PI[11] <> GPIO_0_PI[11]
GPIO_0_PI[12] <> <UNC>
GPIO_0_PI[13] <> <UNC>
GPIO_0_PI[14] <> <UNC>
GPIO_0_PI[15] <> <UNC>
GPIO_0_PI[16] <> <UNC>
GPIO_0_PI[17] <> <UNC>
GPIO_0_PI[18] <> <UNC>
GPIO_0_PI[19] <> <UNC>
GPIO_0_PI[20] <> <UNC>
GPIO_0_PI[21] <> <UNC>
GPIO_0_PI[22] <> <UNC>
GPIO_0_PI[23] <> <UNC>
GPIO_0_PI[24] <> <UNC>
GPIO_0_PI[25] <> <UNC>
GPIO_0_PI[26] <> <UNC>
GPIO_0_PI[27] <> <UNC>
GPIO_0_PI[28] <> <UNC>
GPIO_0_PI[29] <> <UNC>
GPIO_0_PI[30] <> <UNC>
GPIO_0_PI[32] <> <UNC>
GPIO_0_PI[33] <> <UNC>
GPIO_0_PI_IN[0] => ~NO_FANOUT~
GPIO_0_PI_IN[1] => ~NO_FANOUT~
GPIO_1[0] <> <UNC>
GPIO_1[1] <> <UNC>
GPIO_1[2] <> <UNC>
GPIO_1[3] <> <UNC>
GPIO_1[4] <> <UNC>
GPIO_1[5] <> <UNC>
GPIO_1[6] <> <UNC>
GPIO_1[7] <> <UNC>
GPIO_1[8] <> <UNC>
GPIO_1[9] <> <UNC>
GPIO_1[10] <> <UNC>
GPIO_1[11] <> <UNC>
GPIO_1[12] <> <UNC>
GPIO_1[13] <> <UNC>
GPIO_1[14] <> <UNC>
GPIO_1[15] <> <UNC>
GPIO_1[16] <> <UNC>
GPIO_1[17] <> <UNC>
GPIO_1[18] <> <UNC>
GPIO_1[19] <> <UNC>
GPIO_1[20] <> <UNC>
GPIO_1[21] <> <UNC>
GPIO_1[22] <> <UNC>
GPIO_1[23] <> <UNC>
GPIO_1[24] <> <UNC>
GPIO_1[25] <> <UNC>
GPIO_1[26] <> <UNC>
GPIO_1[27] <> <UNC>
GPIO_1[28] <> <UNC>
GPIO_1[29] <> <UNC>
GPIO_1[30] <> <UNC>
GPIO_1[31] <> <UNC>
GPIO_1[32] <> <UNC>
GPIO_1[33] <> <UNC>
GPIO_1_IN[0] => ~NO_FANOUT~
GPIO_1_IN[1] => ~NO_FANOUT~
|MyDE0_Nano|spi_slave:spi_slave_instance
sck => q[0]~reg0.CLK
sck => q[1]~reg0.CLK
sck => q[2]~reg0.CLK
sck => q[3]~reg0.CLK
sck => q[4]~reg0.CLK
sck => q[5]~reg0.CLK
sck => q[6]~reg0.CLK
sck => q[7]~reg0.CLK
sck => q[8]~reg0.CLK
sck => q[9]~reg0.CLK
sck => q[10]~reg0.CLK
sck => q[11]~reg0.CLK
sck => q[12]~reg0.CLK
sck => q[13]~reg0.CLK
sck => q[14]~reg0.CLK
sck => q[15]~reg0.CLK
sck => q[16]~reg0.CLK
sck => q[17]~reg0.CLK
sck => q[18]~reg0.CLK
sck => q[19]~reg0.CLK
sck => q[20]~reg0.CLK
sck => q[21]~reg0.CLK
sck => q[22]~reg0.CLK
sck => q[23]~reg0.CLK
sck => q[24]~reg0.CLK
sck => q[25]~reg0.CLK
sck => q[26]~reg0.CLK
sck => q[27]~reg0.CLK
sck => q[28]~reg0.CLK
sck => q[29]~reg0.CLK
sck => q[30]~reg0.CLK
sck => q[31]~reg0.CLK
sck => cnt[0].CLK
sck => cnt[1].CLK
sck => cnt[2].CLK
sck => cnt[3].CLK
sck => cnt[4].CLK
sck => qdelayed.CLK
mosi => q[0]~reg0.DATAIN
miso <= miso.DB_MAX_OUTPUT_PORT_TYPE
reset => cnt[0].ACLR
reset => cnt[1].ACLR
reset => cnt[2].ACLR
reset => cnt[3].ACLR
reset => cnt[4].ACLR
d[0] => q.DATAB
d[1] => q.DATAB
d[2] => q.DATAB
d[3] => q.DATAB
d[4] => q.DATAB
d[5] => q.DATAB
d[6] => q.DATAB
d[7] => q.DATAB
d[8] => q.DATAB
d[9] => q.DATAB
d[10] => q.DATAB
d[11] => q.DATAB
d[12] => q.DATAB
d[13] => q.DATAB
d[14] => q.DATAB
d[15] => q.DATAB
d[16] => q.DATAB
d[17] => q.DATAB
d[18] => q.DATAB
d[19] => q.DATAB
d[20] => q.DATAB
d[21] => q.DATAB
d[22] => q.DATAB
d[23] => q.DATAB
d[24] => q.DATAB
d[25] => q.DATAB
d[26] => q.DATAB
d[27] => q.DATAB
d[28] => q.DATAB
d[29] => q.DATAB
d[30] => q.DATAB
d[31] => miso.DATAB
q[0] <= q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[1] <= q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[2] <= q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[3] <= q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[4] <= q[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[5] <= q[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[6] <= q[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[7] <= q[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[8] <= q[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[9] <= q[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[10] <= q[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[11] <= q[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[12] <= q[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[13] <= q[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[14] <= q[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[15] <= q[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[16] <= q[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[17] <= q[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[18] <= q[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[19] <= q[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[20] <= q[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[21] <= q[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[22] <= q[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[23] <= q[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[24] <= q[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[25] <= q[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[26] <= q[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[27] <= q[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[28] <= q[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[29] <= q[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[30] <= q[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[31] <= q[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE
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<TABLE>
<TR bgcolor="#C0C0C0">
<TH>Hierarchy</TH>
<TH>Input</TH>
<TH>Constant Input</TH>
<TH>Unused Input</TH>
<TH>Floating Input</TH>
<TH>Output</TH>
<TH>Constant Output</TH>
<TH>Unused Output</TH>
<TH>Floating Output</TH>
<TH>Bidir</TH>
<TH>Constant Bidir</TH>
<TH>Unused Bidir</TH>
<TH>Input only Bidir</TH>
<TH>Output only Bidir</TH>
</TR>
<TR >
<TD >spi_slave_instance</TD>
<TD >34</TD>
<TD >31</TD>
<TD >0</TD>
<TD >31</TD>
<TD >33</TD>
<TD >31</TD>
<TD >31</TD>
<TD >31</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
</TABLE>
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+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Legal Partition Candidates ;
+--------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+--------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; spi_slave_instance ; 34 ; 31 ; 0 ; 31 ; 33 ; 31 ; 31 ; 31 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+--------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
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